From nobody Fri Oct 3 08:50:30 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D4B7302770; Wed, 3 Sep 2025 12:48:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903687; cv=none; b=MWyEyzSpIgV9rUnz2+DfR5KOhbb1z/bXaKAeJ883TCwzyGQLf/S2G/JeBNHHCei/AFxS2NQWY+86XvOdjOOrqimoqhSTsDoQP6jF7Cg4nvSrQbFWhslhGMva3l02Mw7VCSudMKrPZLg4UvSjGGJw+1Lchlw3nUALdM6X06Fbetc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903687; c=relaxed/simple; bh=EPqmwwZ0f90bOzU8V5eQYfHIX7JI0YJEm0PuKVv+4Pw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J/jQeqUq+ozOqU2FBrjzbaWriK1HOvyvW5xKlOaJL9S6Jhmpiuj9DKaCmLsluwwhQ72QYV34ldeUGP5kPV4yqOuil8qsmnbs0ps/JpKC0dSMgEmwppm9lTVUxZ/BnfuLg1omUNgSwtq++XAebIuIiR+CyWx/SEnT1qSekZBxW8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=N2H2I/zY; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="N2H2I/zY" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 835421A08CE; Wed, 3 Sep 2025 12:48:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5BF2E606C3; Wed, 3 Sep 2025 12:48:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A17131C22DDD0; Wed, 3 Sep 2025 14:48:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903682; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=DJ1DuDyv3KQPQ4Ddd0dIiiyvMJY53s+wrB6U+LwgtA0=; b=N2H2I/zY0L63M0PS1CHma/SUEbnQBdKalT5Xw4uZ/8DnzisuylKoi9gOsKNRvzHQWKY2eV CKjHzHvxDZaBQGVYs6/U9l37n57gVW5Jk/RAhlneqrPt3MqAt4RowKsYxpzSPfuiq6gUPm iKp9KBpE8f4JuUZVJ6wn3IsgoZitYYAUD3NnkBpT4kKofn5wB2/ELKGaWynEWcZS9Z2x23 q64bdsR9Ao8ztNK7k0ZZe6teZvX/XaOEqKN0eMLvUlJHqQJHsoUAyDAHV+3V8Qrt6hBNWI E9Ks6dWzmEuFKsyplISPhHLD4xKK+u1th0w5l3gmonF8zAln9/xDOKKs4wat/g== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:21 +0200 Subject: [PATCH 14/19] clk: eyeq: rename the reg64 field of eqc_pll Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-14-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Not all PLL types need a 64 bits access, make the field name more generic by renaming it to reg. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 64 +++++++++++++++++++++++++---------------------= ---- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 63093a3099261e6798a6752651d25efa1b3e7592..0379fe7593453e72dd8983c7435= 61caa385a3fbd 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -73,7 +73,7 @@ struct eqc_pll { unsigned int index; const char *name; - unsigned int reg64; + unsigned int reg; }; =20 /* @@ -239,7 +239,7 @@ static void eqc_probe_init_plls(struct device *dev, con= st struct eqc_match_data for (i =3D 0; i < data->pll_count; i++) { pll =3D &data->plls[i]; =20 - val =3D readq(base + pll->reg64); + val =3D readq(base + pll->reg); r0 =3D val; r1 =3D val >> 32; =20 @@ -422,19 +422,19 @@ static int eqc_probe(struct platform_device *pdev) =20 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */ static const struct eqc_pll eqc_eyeq5_early_plls[] =3D { - { .index =3D EQ5C_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x02C }, - { .index =3D EQ5C_PLL_PER, .name =3D "pll-per", .reg64 =3D 0x05C }, + { .index =3D EQ5C_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C }, + { .index =3D EQ5C_PLL_PER, .name =3D "pll-per", .reg =3D 0x05C }, }; =20 static const struct eqc_pll eqc_eyeq5_plls[] =3D { - { .index =3D EQ5C_PLL_VMP, .name =3D "pll-vmp", .reg64 =3D 0x034 }, - { .index =3D EQ5C_PLL_PMA, .name =3D "pll-pma", .reg64 =3D 0x03C }, - { .index =3D EQ5C_PLL_VDI, .name =3D "pll-vdi", .reg64 =3D 0x044 }, - { .index =3D EQ5C_PLL_DDR0, .name =3D "pll-ddr0", .reg64 =3D 0x04C }, - { .index =3D EQ5C_PLL_PCI, .name =3D "pll-pci", .reg64 =3D 0x054 }, - { .index =3D EQ5C_PLL_PMAC, .name =3D "pll-pmac", .reg64 =3D 0x064 }, - { .index =3D EQ5C_PLL_MPC, .name =3D "pll-mpc", .reg64 =3D 0x06C }, - { .index =3D EQ5C_PLL_DDR1, .name =3D "pll-ddr1", .reg64 =3D 0x074 }, + { .index =3D EQ5C_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x034 }, + { .index =3D EQ5C_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x03C }, + { .index =3D EQ5C_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044 }, + { .index =3D EQ5C_PLL_DDR0, .name =3D "pll-ddr0", .reg =3D 0x04C }, + { .index =3D EQ5C_PLL_PCI, .name =3D "pll-pci", .reg =3D 0x054 }, + { .index =3D EQ5C_PLL_PMAC, .name =3D "pll-pmac", .reg =3D 0x064 }, + { .index =3D EQ5C_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x06C }, + { .index =3D EQ5C_PLL_DDR1, .name =3D "pll-ddr1", .reg =3D 0x074 }, }; =20 enum { @@ -562,10 +562,10 @@ static const struct eqc_match_data eqc_eyeq5_match_da= ta =3D { }; =20 static const struct eqc_pll eqc_eyeq6l_plls[] =3D { - { .index =3D EQ6LC_PLL_DDR, .name =3D "pll-ddr", .reg64 =3D 0x02C }, - { .index =3D EQ6LC_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x034 }, /* a= lso acc */ - { .index =3D EQ6LC_PLL_PER, .name =3D "pll-per", .reg64 =3D 0x03C }, - { .index =3D EQ6LC_PLL_VDI, .name =3D "pll-vdi", .reg64 =3D 0x044 }, + { .index =3D EQ6LC_PLL_DDR, .name =3D "pll-ddr", .reg =3D 0x02C }, + { .index =3D EQ6LC_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x034 }, /* als= o acc */ + { .index =3D EQ6LC_PLL_PER, .name =3D "pll-per", .reg =3D 0x03C }, + { .index =3D EQ6LC_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044 }, }; =20 static const struct eqc_match_data eqc_eyeq6l_match_data =3D { @@ -580,7 +580,7 @@ static const struct eqc_match_data eqc_eyeq6h_west_matc= h_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_east_plls[] =3D { - { .index =3D 0, .name =3D "pll-east", .reg64 =3D 0x074 }, + { .index =3D 0, .name =3D "pll-east", .reg =3D 0x074 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_east_match_data =3D { @@ -591,10 +591,10 @@ static const struct eqc_match_data eqc_eyeq6h_east_ma= tch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_south_plls[] =3D { - { .index =3D EQ6HC_SOUTH_PLL_VDI, .name =3D "pll-vdi", .reg64 =3D 0x000= }, - { .index =3D EQ6HC_SOUTH_PLL_PCIE, .name =3D "pll-pcie", .reg64 =3D 0x008= }, - { .index =3D EQ6HC_SOUTH_PLL_PER, .name =3D "pll-per", .reg64 =3D 0x010= }, - { .index =3D EQ6HC_SOUTH_PLL_ISP, .name =3D "pll-isp", .reg64 =3D 0x018= }, + { .index =3D EQ6HC_SOUTH_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x000 }, + { .index =3D EQ6HC_SOUTH_PLL_PCIE, .name =3D "pll-pcie", .reg =3D 0x008 }, + { .index =3D EQ6HC_SOUTH_PLL_PER, .name =3D "pll-per", .reg =3D 0x010 }, + { .index =3D EQ6HC_SOUTH_PLL_ISP, .name =3D "pll-isp", .reg =3D 0x018 }, }; =20 static const struct eqc_div eqc_eyeq6h_south_divs[] =3D { @@ -641,7 +641,7 @@ static const struct eqc_match_data eqc_eyeq6h_south_mat= ch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] =3D { - { .index =3D 0, .name =3D "pll-ddr0", .reg64 =3D 0x074 }, + { .index =3D 0, .name =3D "pll-ddr0", .reg =3D 0x074 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data =3D { @@ -650,7 +650,7 @@ static const struct eqc_match_data eqc_eyeq6h_ddr0_matc= h_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] =3D { - { .index =3D 0, .name =3D "pll-ddr1", .reg64 =3D 0x074 }, + { .index =3D 0, .name =3D "pll-ddr1", .reg =3D 0x074 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data =3D { @@ -659,11 +659,11 @@ static const struct eqc_match_data eqc_eyeq6h_ddr1_ma= tch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_acc_plls[] =3D { - { .index =3D EQ6HC_ACC_PLL_XNN, .name =3D "pll-xnn", .reg64 =3D 0x040 }, - { .index =3D EQ6HC_ACC_PLL_VMP, .name =3D "pll-vmp", .reg64 =3D 0x050 }, - { .index =3D EQ6HC_ACC_PLL_PMA, .name =3D "pll-pma", .reg64 =3D 0x05C }, - { .index =3D EQ6HC_ACC_PLL_MPC, .name =3D "pll-mpc", .reg64 =3D 0x068 }, - { .index =3D EQ6HC_ACC_PLL_NOC, .name =3D "pll-noc", .reg64 =3D 0x070 }, + { .index =3D EQ6HC_ACC_PLL_XNN, .name =3D "pll-xnn", .reg =3D 0x040 }, + { .index =3D EQ6HC_ACC_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x050 }, + { .index =3D EQ6HC_ACC_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x05C }, + { .index =3D EQ6HC_ACC_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x068 }, + { .index =3D EQ6HC_ACC_PLL_NOC, .name =3D "pll-noc", .reg =3D 0x070 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_acc_match_data =3D { @@ -697,7 +697,7 @@ builtin_platform_driver(eqc_driver); =20 /* Required early for GIC timer. */ static const struct eqc_pll eqc_eyeq6h_central_early_plls[] =3D { - { .index =3D EQ6HC_CENTRAL_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x02C= }, + { .index =3D EQ6HC_CENTRAL_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C }, }; =20 static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factor= s[] =3D { @@ -714,7 +714,7 @@ static const struct eqc_early_match_data eqc_eyeq6h_cen= tral_early_match_data __i =20 /* Required early for UART. */ static const struct eqc_pll eqc_eyeq6h_west_early_plls[] =3D { - { .index =3D EQ6HC_WEST_PLL_PER, .name =3D "pll-west", .reg64 =3D 0x074 }, + { .index =3D EQ6HC_WEST_PLL_PER, .name =3D "pll-west", .reg =3D 0x074 }, }; =20 static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[]= =3D { @@ -758,7 +758,7 @@ static void __init eqc_early_init(struct device_node *n= p, for (i =3D 0; i < clk_count; i++) cells->hws[i] =3D ERR_PTR(-EPROBE_DEFER); =20 - /* Offsets (reg64) of early PLLs are relative to OLB block. */ + /* Offsets (reg) of early PLLs are relative to OLB block. */ base =3D of_iomap(np, 0); if (!base) { ret =3D -ENODEV; @@ -772,7 +772,7 @@ static void __init eqc_early_init(struct device_node *n= p, u32 r0, r1; u64 val; =20 - val =3D readq(base + pll->reg64); + val =3D readq(base + pll->reg); r0 =3D val; r1 =3D val >> 32; =20 --=20 2.51.0