From nobody Fri Oct 3 08:49:06 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B962E3009FE; Wed, 3 Sep 2025 12:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903682; cv=none; b=EBGChezN8dGNQHeeSIAL7DGzQr+QuOzz7P4idpvTe/EMzgipaIUEPRqXceQo8NfIAl0Vh1hbHq8T8iE6yKsheVpLcxCAfrahpbkOPKfpsmC7dXJ8OkevMvdAsIvUNRaIl0l1vDADNHu8X0qB3nVrd9AF3O9/MCnV+5hZ9PTf4GA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903682; c=relaxed/simple; bh=t9Cj2vsk9A2IypF0ZbhgnScvYQTKAJSuu1sLgL93Sw0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TrtN6P4htfyHBIGYzVXquymiYBDEdXkMcNfuti0SmSY7PDULztwGl8s4n0eZ5VWFoi2td7lPHWAD2iVHSrXobDFKFnF+ESMDyRV/Obc/tcYNERhDLISN9tL2reMbCz7dOwcns7GPWoKSBXwgHMW89HRK4rAQT3WGK/U+D2TX/dU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=MDKetlJE; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="MDKetlJE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 99B581A08CE; Wed, 3 Sep 2025 12:47:57 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 72788606C3; Wed, 3 Sep 2025 12:47:57 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 100511C228A5D; Wed, 3 Sep 2025 14:47:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903675; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=cG4E+ChNi7Pq9aaCdZ3+CMHo9z6hvO9a8YfEiX5GW9w=; b=MDKetlJEgtj5kCgTTIDxg7bUP//0qIPgaS2Y99jXiJ4vb9v0pATsiERS2r8tFnY4Ifxnry gQV58rNFDRbX9gxdlPbOzhvdYV3NyoV5oCbRAfyaoYbbDc7MtrXjnEn4Xqrdt/NThvfLvf Q/XNBsp3z5m4PCrtPo54D315K+lmO4zjzaDY57JR8ObJ9ujozEUo74UjEyTtL/A0v8C6JS ixFPTehfn7wlegKeOtmTc78AcIGLHGkrvAZOKDCnTfhLZAEKStzdcuZ8pruJBnIyEnPmCM pJnKCpbxiLEy5SK0Nvgia3I8Xcr28Xe88lonYnKtmXvK3017XH4And8R5UjiwA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:18 +0200 Subject: [PATCH 11/19] clk: eyeq: rename the parent field to parent_idx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-11-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Make some room for introducing a new field to refer to the parent clock by its name for divisors and fixed factors. No functional code change in this patch, this is a rename only. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index cbba4a21cca47efb8ab554ecf7322e47437c9c6a..89e0782b5cbe16a7c2010d9d441= ace139fd0deb5 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -83,7 +83,7 @@ struct eqc_pll { struct eqc_div { unsigned int index; const char *name; - unsigned int parent; + unsigned int parent_idx; unsigned int reg; u8 shift; u8 width; @@ -94,7 +94,7 @@ struct eqc_fixed_factor { const char *name; unsigned int mult; unsigned int div; - unsigned int parent; + unsigned int parent_idx; }; =20 struct eqc_match_data { @@ -269,11 +269,11 @@ static void eqc_probe_init_divs(struct device *dev, c= onst struct eqc_match_data for (i =3D 0; i < data->div_count; i++) { div =3D &data->divs[i]; reg =3D base + div->reg; - parent =3D cells->hws[div->parent]; + parent =3D cells->hws[div->parent_idx]; =20 if (IS_ERR(parent)) { /* Parent is in early clk provider. */ - parent_data.index =3D div->parent; + parent_data.index =3D div->parent_idx; parent_data.hw =3D NULL; } else { /* Avoid clock lookup when we already have the hw reference. */ @@ -301,12 +301,12 @@ static void eqc_probe_init_fixed_factors(struct devic= e *dev, =20 for (i =3D 0; i < data->fixed_factor_count; i++) { ff =3D &data->fixed_factors[i]; - parent_hw =3D cells->hws[ff->parent]; + parent_hw =3D cells->hws[ff->parent_idx]; =20 if (IS_ERR(parent_hw)) { /* Parent is in early clk provider. */ hw =3D clk_hw_register_fixed_factor_index(dev, ff->name, - ff->parent, 0, ff->mult, ff->div); + ff->parent_idx, 0, ff->mult, ff->div); } else { /* Avoid clock lookup when we already have the hw reference. */ hw =3D clk_hw_register_fixed_factor_parent_hw(dev, ff->name, @@ -522,7 +522,7 @@ static const struct eqc_div eqc_eyeq5_divs[] =3D { { .index =3D EQ5C_DIV_OSPI, .name =3D "div-ospi", - .parent =3D EQ5C_PLL_PER, + .parent_idx =3D EQ5C_PLL_PER, .reg =3D 0x11C, .shift =3D 0, .width =3D 4, @@ -597,7 +597,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_EMMC, .name =3D "div-emmc", - .parent =3D EQ6HC_SOUTH_PLL_PER, + .parent_idx =3D EQ6HC_SOUTH_PLL_PER, .reg =3D 0x070, .shift =3D 4, .width =3D 4, @@ -605,7 +605,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_OSPI_REF, .name =3D "div-ospi-ref", - .parent =3D EQ6HC_SOUTH_PLL_PER, + .parent_idx =3D EQ6HC_SOUTH_PLL_PER, .reg =3D 0x090, .shift =3D 4, .width =3D 4, @@ -613,7 +613,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_OSPI_SYS, .name =3D "div-ospi-sys", - .parent =3D EQ6HC_SOUTH_PLL_PER, + .parent_idx =3D EQ6HC_SOUTH_PLL_PER, .reg =3D 0x090, .shift =3D 8, .width =3D 1, @@ -621,7 +621,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_TSU, .name =3D "div-tsu", - .parent =3D EQ6HC_SOUTH_PLL_PCIE, + .parent_idx =3D EQ6HC_SOUTH_PLL_PCIE, .reg =3D 0x098, .shift =3D 4, .width =3D 8, @@ -790,7 +790,7 @@ static void __init eqc_early_init(struct device_node *n= p, =20 for (i =3D 0; i < early_data->early_fixed_factor_count; i++) { const struct eqc_fixed_factor *ff =3D &early_data->early_fixed_factors[i= ]; - struct clk_hw *parent_hw =3D cells->hws[ff->parent]; + struct clk_hw *parent_hw =3D cells->hws[ff->parent_idx]; struct clk_hw *hw; =20 hw =3D clk_hw_register_fixed_factor_parent_hw(NULL, ff->name, --=20 2.51.0