From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C16ED3002D9; Wed, 3 Sep 2025 12:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903660; cv=none; b=UUtZPJBTx4+X0PgZz5R5FAnbqUWjZH8Jhzo+kMa3tDTZPv/42c9XsxZzefICq4vSwGwZv2ZwmZJ6IQHwrUH3MZnLFqoGh3f1Y9HW1VMLQlKNKaHf4PzG61mSXkc9zmZrTpB/ZwSUQ0b+95d35OSS5GeR0AMSoxGW/DV19V7w5XQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903660; c=relaxed/simple; bh=VM3OVD/vWiYiSOkeqjWoIBwv1wDYZB8pk3Bp3cycWMA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fNKqRcxZVwWg+vtXSk7tEZBKyA62mPnq0xfQgQYtTlrXUEPADlxvRSE4pWwSMTt+xbdQkKJsk4MSZExTt37CBcakxh1uLynrPGGKXgZ8XV5jAuC/G0Qg9e9e8AOUySTfglGwKv9Dqzs26aMiNAZcq8gHobDn6R3H0P446KRGr8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=xd7pnMZu; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="xd7pnMZu" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id EF3E91A08EC; Wed, 3 Sep 2025 12:47:36 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C67A6606C3; Wed, 3 Sep 2025 12:47:36 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 44E061C22CD91; Wed, 3 Sep 2025 14:47:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903655; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=y7/3uUqHDVMs8kf6yCzPNaMJlbjeqZRZRUZYl68nr5c=; b=xd7pnMZuiROl4gry4SM/mQcrhE0lAgzhWG10AXQp8YgcIZMWUTsTiT3BbCqLKVJJAgN9Au g9GSHs2roJNSHoGHUI6duywQ2vp4hCvF/W8Kh7epTdpmj2hlSW9LajHxsxJX1mRVtcxTIC 9PWZrrNgxONdxs+kqpQfd+evy1rRXP4D9yBd5nA5hbwTyomzFgU+3/+SzJLsPDv4UFFiXS J7vIDN43/YrB9E1wi/XTfu1tWxwwpPXi6m+9gYY1o5HWtX/fpyBMiE5Yq0S118v2121fqA DpvcgTgatPkvoWVBpYoAFwMkv1rnW00JBgW/pDU4sB2eYV1Hg1DD1/jjE2PqdQ== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:08 +0200 Subject: [PATCH 01/19] dt-bindings: soc: mobileye: rename to eyeq-olb.yaml Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-1-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Drop the 5 from the binding name as the OLB described in it are found in multiple Mobileye eyeQ SoCs. The binding already contains entries for eyeQ6L and eyeQ6H OLBs alongside the one for the eyeQ5. Signed-off-by: Beno=C3=AEt Monin --- .../soc/mobileye/{mobileye,eyeq5-olb.yaml =3D> mobileye,eyeq-olb.yaml} = | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-= olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb= .yaml similarity index 99% rename from Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-o= lb.yaml rename to Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.= yaml index 6d11472ba5a704d5d20f43776e5867f507a39242..a1fb33ab4399cca52fad1e589be= ede54e09e5512 100644 --- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml# +$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq-olb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mobileye EyeQ SoC system controller --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EF432FC876; Wed, 3 Sep 2025 12:47:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903663; cv=none; b=AwubQIzvHrkFYolfbM5kW5iosg23RyZ/Ij178lpaRPicQ8FVAx2VS8g5hdzXxcT1bak6vnGSbMRGYnLlhBsGu3/ZDLJIIlRE0K5cLkbdEz5jL/DGAwfPD/gMeHu4tfuK5rBJcn4h7HdoDyps1A1laJ/SOwTomGwrAlvILmf6Hm8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903663; c=relaxed/simple; bh=VNuLiSygwxmgYwmleuSLXCuPI5cvRlnKciRPEbwy97g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=APKyJ+nfO/7BFpSvzqdeJVK2BWLYyMQwJcS9NaPWIwcdHyGp4X75tJDYmL4nPACJMctccyFG8zaWxDIcl59Q0gpxqJnH7skBzy5MqKzpfHZ0kjJ0DvvA8HLlej2letdm6P8dmAsIjfYDr/gbgOD9CyGWg/g/OVEDv8e7pJTb4Uo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=kVKBigKN; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="kVKBigKN" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 834EC4E40C12; Wed, 3 Sep 2025 12:47:39 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5B189606C3; Wed, 3 Sep 2025 12:47:39 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 240181C22CCD6; Wed, 3 Sep 2025 14:47:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903658; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=CvWsUbWQSdNgJusFenlHc7IBkEUqAY4aanAKhM5h1HM=; b=kVKBigKNZtOzY/QhvAUkK41mqalkDBNwtVTAbHn52rvB2DLYza9YPHPeMDw3uyy1ztYKnJ A/jIMojl7J2plGICszXuoc87TSChcN7O57lj1G34lVamMxaJ398C1SjYCDsVk7MGr2+kUp dTXHvvH8K2pm19yUB1I8ghUsa1Ljus2YSGYqQ/0Nq/DXh/U6f217X0VdycsDm6mBwlvARY f5H0luHwTOb70qFkwgfrGSLorvYBhraLXYPqG4RmTHf9/6bttPoo/N480TMFttfMUxLkv6 9Lu+tMHu9+05TmTT8xsR6T18mGRb1ImBK7e9ecEa6LY5TwV+49ybBG2XWzPVCA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:09 +0200 Subject: [PATCH 02/19] dt-bindings: clock: mobileye: rename to eyeq-clk.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-2-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Rename the header from mobileye,eyeq5-clk.h to mobileye,eyeq-clk.h as it covers more SoCs than just the eyeQ5, but also the eyeQ6L and eyeQ6H. Also changes all includes to point to the renamed header. Signed-off-by: Beno=C3=AEt Monin --- MAINTAINERS | 2 = +- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 2 = +- arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 2 = +- drivers/clk/clk-eyeq.c | 2 = +- .../dt-bindings/clock/{mobileye,eyeq5-clk.h =3D> mobileye,eyeq-clk.h} | = 4 ++-- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 6dcfbd11efef87927041f5cf58d70633dbb4b18d..c56f17e4c585fe3e719fbae18b7= 0a0c132c5da48 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17112,7 +17112,7 @@ F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq.c F: drivers/pinctrl/pinctrl-eyeq5.c F: drivers/reset/reset-eyeq.c -F: include/dt-bindings/clock/mobileye,eyeq5-clk.h +F: include/dt-bindings/clock/mobileye,eyeq-clk.h =20 MODULE SUPPORT M: Luis Chamberlain diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mo= bileye/eyeq5.dtsi index 36a73e8a63a1ab32d1c300d17c4491b175428cdf..206afeff80ccf618fae80a832ee= 2268cad598f71 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ =20 #include =20 -#include +#include =20 / { #address-cells =3D <2>; diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/m= obileye/eyeq6h.dtsi index 5ae939d25ea87ddc15cb848c249beed3d07e32e0..a6ffdf1764b3e66295ee17b2d0d= 2eee8024f95f3 100644 --- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -5,7 +5,7 @@ =20 #include =20 -#include +#include =20 / { #address-cells =3D <2>; diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index ea1c3d78e7cd47c2698483f58ae1d691ce6d399d..8fbc8eb31185a9e82216a38a81d= fbdaa1a700858 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -44,7 +44,7 @@ #include #include =20 -#include +#include =20 /* In frac mode, it enables fractional noise canceling DAC. Else, no funct= ion. */ #define PCSR0_DAC_EN BIT(0) diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bi= ndings/clock/mobileye,eyeq-clk.h similarity index 93% rename from include/dt-bindings/clock/mobileye,eyeq5-clk.h rename to include/dt-bindings/clock/mobileye,eyeq-clk.h index f353c2988035f7c9fb84e4b59c6c4a220436454b..8424ec59a02d037ddd5b049cb4b= 7f26764ae2542 100644 --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq-clk.h @@ -3,8 +3,8 @@ * Copyright (C) 2024 Mobileye Vision Technologies Ltd. */ =20 -#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H -#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ_CLK_H =20 #define EQ5C_PLL_CPU 0 #define EQ5C_PLL_VMP 1 --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25E8B3019AC for ; Wed, 3 Sep 2025 12:47:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903665; cv=none; b=gADLLueqSxsnmu704t/ZhtgnCElMSBfwDe+HHlgR+AM0DgUM4VYP+61zwu3sNIV2CYDZ8Q1mpBsrLcEBQOP8CktdnJZRlHpKcu+K8VtHJArS/gNWpZX43UpzGr9Kw+npQ57pudVsXk8ShfxdXQFg9LOu8bfQVBH9iu/cq16RKjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903665; c=relaxed/simple; bh=0saqy2ank/kQSz4Ww8r9z1PPHZuOJXL00GI6uyCUJ88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ohUDVP19ODOnrr/SOFEPob5wCJn4WKS5U8VYxDY7YC3iZVpswJbuvJBe77LPXQ1zq5NDPftmZUl9evfusXPSwI1SbkCa+U0/JFxnlEsDVH30IwPJvfYFbFUy6s2ZVIjVAuLr7eu4ULb4YozpfGQtDzesuQ/fK2+ou1iTTMWFk5s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=raYVsq3B; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="raYVsq3B" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 856A61A08CE; Wed, 3 Sep 2025 12:47:41 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5F022606C3; Wed, 3 Sep 2025 12:47:41 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9BE171C22D526; Wed, 3 Sep 2025 14:47:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903660; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=+pP4bWwzyG5YF07Boql4xgFZkgldjwexeze/csRTuZ4=; b=raYVsq3BQY6IYcs3JlCSSFm4gJbadYGrSCQHOD3EEfGy/cVhb5/puDc3cYuwMzDzCVXxXi E01+aTiXFfBrU4DHtIT+4aMlOcqe/TiuDb4q7FCf7AxmCRX/Evy/NXf8DzJwIzp46nqk7i E/syakBZwMrSGRnkjmNk+JTRGaO2qnsu4JAdCPxTDo7rQPcVA4FMq8cce7gJOkLQ/2IJ+C MlS46y1fYw5N8qCoCuCwgOOb7Z7gPBYsg7mG/fRhaFssuWdTcr5oLo2Gs/ExZW3B+jETNG Z1R5vb/SseIcVFUk7kXLym7hRo3Qmo4ThNWmIJWeoIVvJnezoRyw3yN8blHG3A== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:10 +0200 Subject: [PATCH 03/19] dt-bindings: soc: mobileye: add eyeQ7H compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-3-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The eyeQ7H features 14 OLB. The main differences with the previous generation of SoC is that some blocks have two clock sources instead of one and that the clock source can be the one of the clock output of another OLB instead of the main oscillator. For the blocks with a single parent clock, the name if that clock is "ref", similar to what is done for the OLB of the previous SoC. The blocks with two parent clocks use the names of the reference clocks generated by the other OLB or the main oscillator. Some OLB also contain a reset controller with one or more reset domain, like the blocks found in the eyeQ6H. Signed-off-by: Beno=C3=AEt Monin --- .../bindings/soc/mobileye/mobileye,eyeq-olb.yaml | 135 +++++++++++++++++= +++- 1 file changed, 130 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-o= lb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.= yaml index a1fb33ab4399cca52fad1e589beede54e09e5512..5800396d39f050c11fa5a401329= 7f756b97a2b02 100644 --- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml @@ -14,7 +14,7 @@ maintainers: description: OLB ("Other Logic Block") is a hardware block grouping smaller blocks. C= locks, resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a sin= gle - instance. EyeQ6H hosts seven instances. + instance. EyeQ6H hosts seven instances. EyeQ7H hosts 14 instances. =20 properties: compatible: @@ -29,6 +29,20 @@ properties: - mobileye,eyeq6h-south-olb - mobileye,eyeq6h-ddr0-olb - mobileye,eyeq6h-ddr1-olb + - mobileye,eyeq7h-south-olb + - mobileye,eyeq7h-east-olb + - mobileye,eyeq7h-west-olb + - mobileye,eyeq7h-periph-east-olb + - mobileye,eyeq7h-periph-west-olb + - mobileye,eyeq7h-ddr0-olb + - mobileye,eyeq7h-ddr1-olb + - mobileye,eyeq7h-mips0-olb + - mobileye,eyeq7h-mips1-olb + - mobileye,eyeq7h-mips2-olb + - mobileye,eyeq7h-acc0-olb + - mobileye,eyeq7h-acc1-olb + - mobileye,eyeq7h-xnn0-olb + - mobileye,eyeq7h-xnn1-olb - const: syscon =20 reg: @@ -44,12 +58,12 @@ properties: const: 1 =20 clocks: - maxItems: 1 - description: - Input parent clock to all PLLs. Expected to be the main crystal. + minItems: 1 + maxItems: 2 =20 clock-names: - const: ref + minItems: 1 + maxItems: 2 =20 patternProperties: '-pins?$': @@ -265,6 +279,88 @@ required: additionalProperties: false =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq5-olb + - mobileye,eyeq6l-olb + - mobileye,eyeq6h-acc-olb + - mobileye,eyeq6h-central-olb + - mobileye,eyeq6h-east-olb + - mobileye,eyeq6h-west-olb + - mobileye,eyeq6h-south-olb + - mobileye,eyeq6h-ddr0-olb + - mobileye,eyeq6h-ddr1-olb + - mobileye,eyeq7h-south-olb + - mobileye,eyeq7h-periph-east-olb + - mobileye,eyeq7h-ddr0-olb + - mobileye,eyeq7h-ddr1-olb + - mobileye,eyeq7h-mips0-olb + - mobileye,eyeq7h-mips1-olb + - mobileye,eyeq7h-mips2-olb + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: ref + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-east-olb + - mobileye,eyeq7h-west-olb + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: ref + - const: ref_100p0 + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-periph-west-olb + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: ref_100p0 + - const: ref_106p6_w + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-acc0-olb + - mobileye,eyeq7h-acc1-olb + - mobileye,eyeq7h-xnn0-olb + - mobileye,eyeq7h-xnn1-olb + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: ref_100p0 + - const: ref_106p6_e + # Compatibles exposing a single reset domain. - if: properties: @@ -274,6 +370,12 @@ allOf: - mobileye,eyeq6h-acc-olb - mobileye,eyeq6h-east-olb - mobileye,eyeq6h-west-olb + - mobileye,eyeq7h-east-olb + - mobileye,eyeq7h-west-olb + - mobileye,eyeq7h-periph-east-olb + - mobileye,eyeq7h-periph-west-olb + - mobileye,eyeq7h-ddr0-olb + - mobileye,eyeq7h-ddr1-olb then: properties: '#reset-cells': @@ -289,6 +391,11 @@ allOf: enum: - mobileye,eyeq5-olb - mobileye,eyeq6l-olb + - mobileye,eyeq7h-south-olb + - mobileye,eyeq7h-acc0-olb + - mobileye,eyeq7h-acc1-olb + - mobileye,eyeq7h-xnn0-olb + - mobileye,eyeq7h-xnn1-olb then: properties: '#reset-cells': @@ -306,6 +413,9 @@ allOf: - mobileye,eyeq6h-south-olb - mobileye,eyeq6h-ddr0-olb - mobileye,eyeq6h-ddr1-olb + - mobileye,eyeq7h-mips0-olb + - mobileye,eyeq7h-mips1-olb + - mobileye,eyeq7h-mips2-olb then: properties: '#reset-cells': false @@ -350,3 +460,18 @@ examples: clock-names =3D "ref"; }; }; + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + system-controller0@45000000 { + compatible =3D "mobileye,eyeq7h-acc0-olb", "syscon"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + #reset-cells =3D <2>; + #clock-cells =3D <1>; + clocks =3D <&olb_south 7>, + <&olb_east 5>; + clock-names =3D "ref_100p0", "ref_106p6_e"; + }; + }; --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20C2130274F; Wed, 3 Sep 2025 12:47:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903667; cv=none; b=A0b12CMH9Rfck/95eDXNCbKCgPRszEras/wDtXzhaW09hUAIgNTZpzyt4dpbiL1ncWeFNIHxxsNfYiZnTGwnXoT8ybI4x3eQDx+LrJX+Y4ECI6niYVxHIbVMptfcLwWaSTQ85GUGJ2vO4qJcm8CpO0YqCopgXnYdg9/RKqieuN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903667; c=relaxed/simple; bh=mvgo3A42kq20HDxbEhdc5uVZRhhpfxw9I9kuq6ttNgI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VIVqHg4SG+78fryPn3YqCuxrutCUjMhxsr1+I43HscysEQiCEaZJEppPNXZ1Y0M9I1Z/+Rw0nFKLV8CQR/RhDE1UGsAK2iRf4rR00hx0YRDyakDqnJEeT0t8M+Im4SdiYTBkwHc6USMtS3UD5gxiRIryrF8uq+RiW9O/Xc1Igl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=g898dpFT; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="g898dpFT" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 7195A4E40C0A; Wed, 3 Sep 2025 12:47:43 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 4A6AF606C3; Wed, 3 Sep 2025 12:47:43 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 932821C22DB0A; Wed, 3 Sep 2025 14:47:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903662; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=HASba0lkYrgQRr4XGbui0JEcE9buZeXXfsQR2uXbBSQ=; b=g898dpFThGiVgyu9ccsVPVWwRO7+EqYeusPAZcQYr2Rqkb3q3BEDinA9Wi6t9RKo7avK7j iVfoUZ1sroTg4VzeWFhM6PLou58xhFR9yxFoqjwXV07BLUqhCV8OTg1c98XsxumwgZZP/G 3DpyRwMfgJNfCLYqAfHzZ5QchSAsNgafYH3ksnQiz/2S08+tPupq2pbxdqtGNgbvmVs/sJ s/oVg/ETirqkPis4YzH99Y0/oI90gRD8/s/xZ3iw+bAWirk5ty9/cEvOa8/vTVhyQiqS/X 5HsRLPBoioP7o27Kd28Mb28hvbMnxfPetF+i+IrrQZtnLkU933UyB1H+gW1y5Q== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:11 +0200 Subject: [PATCH 04/19] dt-bindings: clock: mobileye: add eyeQ7H clock indexes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-4-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add the clock indexes for the various OLB found in the eyeQ7H SoC. For some of the OLB, the indexes are common between two or three blocks: * EQ7HC_DDR defines the clock indexes of DDR0 and DDR1 OLB. * EQ7HC_MIPS defines the clock indexes of MIPS0, MIPS1, and MIPS2 OLB. * EQ7HC_ACC defines the clock indexes of ACC0 and ACC1 OLB. * EQ7HC_XNN defines the clock indexes of XNN0 and XNN1 OLB. Signed-off-by: Beno=C3=AEt Monin --- include/dt-bindings/clock/mobileye,eyeq-clk.h | 110 ++++++++++++++++++++++= ++++ 1 file changed, 110 insertions(+) diff --git a/include/dt-bindings/clock/mobileye,eyeq-clk.h b/include/dt-bin= dings/clock/mobileye,eyeq-clk.h index 8424ec59a02d037ddd5b049cb4b7f26764ae2542..0fe9b98c940cbc479ce46fc83fc= 651101bf1b86a 100644 --- a/include/dt-bindings/clock/mobileye,eyeq-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq-clk.h @@ -62,4 +62,114 @@ #define EQ6HC_ACC_PLL_MPC 3 #define EQ6HC_ACC_PLL_NOC 4 =20 +#define EQ7HC_SOUTH_PLL_XSPI 0 +#define EQ7HC_SOUTH_PLL_VDIO 1 +#define EQ7HC_SOUTH_PLL_PER 2 +#define EQ7HC_SOUTH_PLL_100P0 3 + +#define EQ7HC_SOUTH_DIV_VDO_DSI_SYS 4 +#define EQ7HC_SOUTH_DIV_PMA_CMN_REF 5 +#define EQ7HC_SOUTH_DIV_REF_UFS 6 +#define EQ7HC_SOUTH_DIV_REF_100P0 7 +#define EQ7HC_SOUTH_DIV_XSPI_SYS 8 +#define EQ7HC_SOUTH_DIV_XSPI_MBITS 9 +#define EQ7HC_SOUTH_DIV_NOC_S 10 +#define EQ7HC_SOUTH_DIV_PCIE_SYS 11 +#define EQ7HC_SOUTH_DIV_PCIE_SYS_MBITS 12 +#define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY 13 +#define EQ7HC_SOUTH_DIV_UFS_CORE 14 +#define EQ7HC_SOUTH_DIV_UFS_SMS 15 +#define EQ7HC_SOUTH_DIV_UFS_ROM_SMS 16 +#define EQ7HC_SOUTH_DIV_ETH_SYS 17 +#define EQ7HC_SOUTH_DIV_ETH_MBITS 18 +#define EQ7HC_SOUTH_DIV_CFG_S 19 +#define EQ7HC_SOUTH_DIV_TSU 20 +#define EQ7HC_SOUTH_DIV_VDIO 21 +#define EQ7HC_SOUTH_DIV_VDIO_CORE 22 +#define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIT 23 +#define EQ7HC_SOUTH_DIV_VDO_CORE_MBITS 24 +#define EQ7HC_SOUTH_DIV_VDO_P 25 +#define EQ7HC_SOUTH_DIV_VDIO_CFG 26 +#define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC 27 + +#define EQ7HC_EAST_PLL_106P6 0 +#define EQ7HC_EAST_PLL_NOC 1 +#define EQ7HC_EAST_PLL_ISP 2 +#define EQ7HC_EAST_PLL_VEU 3 + +#define EQ7HC_EAST_DIV_REF_DDR_PHY 4 +#define EQ7HC_EAST_DIV_REF_106P6 5 +#define EQ7HC_EAST_DIV_CORE 6 +#define EQ7HC_EAST_DIV_CORE_MBITS 7 +#define EQ7HC_EAST_DIV_ISRAM_MBITS 8 +#define EQ7HC_EAST_DIV_CFG 9 +#define EQ7HC_EAST_DIV_VEU_CORE 10 +#define EQ7HC_EAST_DIV_VEU_MBITS 11 +#define EQ7HC_EAST_DIV_VEU_OCP 12 +#define EQ7HC_EAST_DIV_LBITS 13 +#define EQ7HC_EAST_DIV_ISP0_CORE 14 + +#define EQ7HC_WEST_PLL_106P6 0 +#define EQ7HC_WEST_PLL_NOC 1 +#define EQ7HC_WEST_PLL_GPU 2 +#define EQ7HC_WEST_PLL_SSI 3 + +#define EQ7HC_WEST_DIV_GPU 4 +#define EQ7HC_WEST_DIV_GPU_MBITS 5 +#define EQ7HC_WEST_DIV_LBITS 6 +#define EQ7HC_WEST_DIV_MIPS_TIMER 7 +#define EQ7HC_WEST_DIV_SSI_CORE 8 +#define EQ7HC_WEST_DIV_SSI_CORE_MBITS 9 +#define EQ7HC_WEST_DIV_SSI_ROM 10 +#define EQ7HC_WEST_DIV_SSI_ROM_MBITS 11 +#define EQ7HC_WEST_DIV_REF_DDR_PHY 12 +#define EQ7HC_WEST_DIV_REF_106P6 13 +#define EQ7HC_WEST_DIV_CORE 14 +#define EQ7HC_WEST_DIV_CORE_MBIT 15 +#define EQ7HC_WEST_DIV_CFG 16 +#define EQ7HC_WEST_DIV_CAU 17 +#define EQ7HC_WEST_DIV_CAU_MBITS 18 + +#define EQ7HC_PERIPH_EAST_PLL_PER 0 + +#define EQ7HC_PERIPH_EAST_DIV_PER 1 + +#define EQ7HC_PERIPH_WEST_PLL_PER 0 +#define EQ7HC_PERIPH_WEST_PLL_I2S 1 + +#define EQ7HC_PERIPH_WEST_DIV_PER 2 +#define EQ7HC_PERIPH_WEST_DIV_I2S 3 + +#define EQ7HC_DDR_PLL 0 + +#define EQ7HC_DDR_DIV_APB 1 +#define EQ7HC_DDR_DIV_PLLREF 2 +#define EQ7HC_DDR_DIV_DFI 3 + +#define EQ7HC_MIPS_PLL_CPU 0 + +#define EQ7HC_MIPS_DIV_CM 1 + +#define EQ7HC_ACC_PLL_VMP 0 +#define EQ7HC_ACC_PLL_MPC 1 +#define EQ7HC_ACC_PLL_PMA 2 +#define EQ7HC_ACC_PLL_NOC 3 + +#define EQ7HC_ACC_DIV_PMA 4 +#define EQ7HC_ACC_DIV_NCORE 5 +#define EQ7HC_ACC_DIV_CFG 6 + +#define EQ7HC_XNN_PLL_XNN0 0 +#define EQ7HC_XNN_PLL_XNN1 1 +#define EQ7HC_XNN_PLL_XNN2 2 +#define EQ7HC_XNN_PLL_CLSTR 3 + +#define EQ7HC_XNN_DIV_XNN0 4 +#define EQ7HC_XNN_DIV_XNN1 5 +#define EQ7HC_XNN_DIV_XNN2 6 +#define EQ7HC_XNN_DIV_CLSTR 7 +#define EQ7HC_XNN_DIV_I2 8 +#define EQ7HC_XNN_DIV_I2_SMS 9 +#define EQ7HC_XNN_DIV_CFG 10 + #endif --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AD58302CD9 for ; Wed, 3 Sep 2025 12:47:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903669; cv=none; b=ZLSuUfoQDTHWqk6e4ZBIbjz8490QaXpr9oTd2/kw9MEInOmoHCLNrzLnXm8tc19VPO3KpZ+cjLpDBX3XJBR4S2Z29YZpSKyvLY1kCFoEO7h4wkSPUsVtEzj4xZgVFpuns7O+2N2+f5yaNl5Q+Z4mA1N7o3hVF2kG1ZZB8+D0Bh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903669; c=relaxed/simple; bh=PgOES7Ac1xUOjEyzw95I56CWyH2IDlrdYkxnvVUdyxE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R84ePA8Mhr1preeO59WJsATh2rVOiQkDPU+O3bXsUELjkQWsHstIRs+5cPWc3WOxDQPX1GUGY48Wtp6BM/z6JgRmX8hDwJTjcYJ3roCBxghJNUpoUfV95Ic6u3MnFlgF7MzOdBu3XsTtYYgKuFig3xg9kHu6H77ISAmiOZzjJaE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=A41XRiLx; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="A41XRiLx" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 4BBFE4E40C12; Wed, 3 Sep 2025 12:47:45 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2355E606C3; Wed, 3 Sep 2025 12:47:45 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A3DDC1C22DA0C; Wed, 3 Sep 2025 14:47:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903664; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=y5x1FnQLW3FxdXiusLS7AQ0y+ufAoMqHxcSYyDkM4aQ=; b=A41XRiLxfcBZ1dfmVrMlj36XiCwCROy9D2a2mOfRfFAjqdznh0essjUxvI2fUGqI3AqDz2 f7LoKCGvTP6nrhutjcKrUDttAMPHcsc3KnVVtz4At7MeIBqjbFkObs7zI0TdzSAeHJihfG ceVQ6OZTHu7otssM54cleU4CW4jtDtQr1sZATwNpaEG80kDYysi6ig0irb5WQIkuLg3fb5 cuIBZH/ANKH2fF42Q+pXz0lxcKfQYiaxhYx55UDNz/+dH1VQ0CJrYMFHFFtqYy94n6BvV5 uDP6APHafLI27ayar+zr2WXIo1dNpBoG2Jbk7bHOE6PA1pRLBjfc2X7lAc5Rvg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:12 +0200 Subject: [PATCH 05/19] dt-bindings: reset: add Mobileye eyeQ Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-5-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Define the indexes of the reset controllers present in 11 of the OLB found in Mobileye eyeQ7H SoC. The define names start with EQ7HR, which is the abbreviation of EyeQ7H Reset. For the OLBs with multiple reset domains, the domain number is in the define name (DOMx) and should also be passed in the device tree: resets =3D <&olb_south 0 EQ7HR_SOUTH_DOM0_PCI_CTL>; For the OLBs with a single reset domain, only the reset index is needed: resets =3D <&olb_periph_west EQ7HR_PERIPH_UART>; Some reset indexes are common between two OLB: * EQ7HR_PERIPH defines the reset indexes of OLB periph_east and periph_west. * EQ7HR_DDR defines the reset indexes of OLB ddr0 and ddr1. * EQ7HR_ACC defines the reset indexes of OLB acc0 and acc1. * EQ7HR_XNN defines the reset indexes of OLB xnn0 and xnn1. Signed-off-by: Sari Khoury Signed-off-by: Beno=C3=AEt Monin --- MAINTAINERS | 1 + include/dt-bindings/reset/mobileye,eyeq-reset.h | 75 +++++++++++++++++++++= ++++ 2 files changed, 76 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c56f17e4c585fe3e719fbae18b70a0c132c5da48..6e6bf23e988ad9b8d77268f680e= a4dee0489684f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17113,6 +17113,7 @@ F: drivers/clk/clk-eyeq.c F: drivers/pinctrl/pinctrl-eyeq5.c F: drivers/reset/reset-eyeq.c F: include/dt-bindings/clock/mobileye,eyeq-clk.h +F: include/dt-bindings/reset/mobileye,eyeq-reset.h =20 MODULE SUPPORT M: Luis Chamberlain diff --git a/include/dt-bindings/reset/mobileye,eyeq-reset.h b/include/dt-b= indings/reset/mobileye,eyeq-reset.h new file mode 100644 index 0000000000000000000000000000000000000000..70d3b7140f8d2599186c7ddff32= b8131e90c644e --- /dev/null +++ b/include/dt-bindings/reset/mobileye,eyeq-reset.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_MOBILEYE_EYEQ_RESET_H +#define _DT_BINDINGS_MOBILEYE_EYEQ_RESET_H + +#define EQ7HR_SOUTH_DOM0_PCI_PHY 0 +#define EQ7HR_SOUTH_DOM0_PCI_CTL 1 +#define EQ7HR_SOUTH_DOM0_S_NOC 2 +#define EQ7HR_SOUTH_DOM0_GBE_PHY 3 +#define EQ7HR_SOUTH_DOM0_GBE_CTL 4 + +#define EQ7HR_SOUTH_DOM1_XSPI 0 +#define EQ7HR_SOUTH_DOM1_UFS 1 +#define EQ7HR_SOUTH_DOM1_S_VDIO 2 + +#define EQ7HR_EAST_ISP 0 +#define EQ7HR_EAST_VEU 1 +#define EQ7HR_EAST_LBIST 2 + +#define EQ7HR_WEST_GPU 0 +#define EQ7HR_WEST_CAU 1 +#define EQ7HR_WEST_LBIST 2 +#define EQ7HR_WEST_GPU_LBIST 3 + +#define EQ7HR_PERIPH_GPIO 0 +#define EQ7HR_PERIPH_EXT 1 +#define EQ7HR_PERIPH_UART 2 +#define EQ7HR_PERIPH_SPI 3 +#define EQ7HR_PERIPH_I2C0 4 +#define EQ7HR_PERIPH_I2C1 5 +#define EQ7HR_PERIPH_I2C2 6 +#define EQ7HR_PERIPH_I2S 7 + +#define EQ7HR_DDR_APB 0 +#define EQ7HR_DDR_DMI 1 +#define EQ7HR_DDR_DFI 2 +#define EQ7HR_DDR_PHY_SMS 3 +#define EQ7HR_DDR_CTL_SMS 4 + +#define EQ7HR_ACC_DOM0_VMP0 0 +#define EQ7HR_ACC_DOM0_VMP1 1 +#define EQ7HR_ACC_DOM0_VMP2 2 +#define EQ7HR_ACC_DOM0_VMP3 3 +#define EQ7HR_ACC_DOM0_MPC0 4 +#define EQ7HR_ACC_DOM0_MPC1 5 +#define EQ7HR_ACC_DOM0_PMA0 6 +#define EQ7HR_ACC_DOM0_PMA1 7 + +#define EQ7HR_ACC_DOM1_NCORE0 0 +#define EQ7HR_ACC_DOM1_NCORE1 1 +#define EQ7HR_ACC_DOM1_NCORE0_M 2 +#define EQ7HR_ACC_DOM1_NCORE1_M 3 +#define EQ7HR_ACC_DOM1_NCORE_NOC 4 +#define EQ7HR_ACC_DOM1_VMP_NOC 5 +#define EQ7HR_ACC_DOM1_MPC_NOC 6 +#define EQ7HR_ACC_DOM1_PMA_NOC 7 + +#define EQ7HR_XNN_DOM0_XNN0 0 +#define EQ7HR_XNN_DOM0_XNN1 1 +#define EQ7HR_XNN_DOM0_XNN2 2 + +#define EQ7HR_XNN_DOM1_XNN0 0 +#define EQ7HR_XNN_DOM1_XNN1 1 +#define EQ7HR_XNN_DOM1_XNN2 2 +#define EQ7HR_XNN_DOM1_XNN3 3 +#define EQ7HR_XNN_DOM1_NCORE 4 +#define EQ7HR_XNN_DOM1_I2_0 5 +#define EQ7HR_XNN_DOM1_I2_1 6 +#define EQ7HR_XNN_DOM1_SMS_0 7 +#define EQ7HR_XNN_DOM1_SMS_1 8 + +#endif --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA8E3043A9 for ; Wed, 3 Sep 2025 12:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903672; cv=none; b=QhPfY5bWyEY2fKFa6apXgJVYS4hpjEp7bifo7v+mp2/Vv2Bifh/4TF2SnL62uu09qNwS8OCSpEtCDDvBKUM7AlYN1hk+LrpBXgNDROVCFZf/KTqBad45XFSMjL7rLmIJMk2z5fvnKQvP5YN8zqB9X3GovXhe/dE3Sc8n2+v84Bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903672; c=relaxed/simple; bh=kGI9vrMnZ8OMv3ozZlNZdXDHDwL02sNWL/GPUnr19TA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hUZYsT9O16H9hPsIbOAmCDG06IHWuNaR+wAH2nEPzE0I7puxhBZmIW3cuzeSiqvpFdS/kQsM3gZYf+tqA8qIilZ5qW2hUYvKYDEtZTPZf4AutXK2gNSmydQIwFqSf7QK7FnehMFLk2Iee0hZrXikm+DDYEW/Ues/DlTUp2mvE2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ukmIk4/k; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ukmIk4/k" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 395B91A08EC; Wed, 3 Sep 2025 12:47:47 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 11D7D606C3; Wed, 3 Sep 2025 12:47:47 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 712381C22CD91; Wed, 3 Sep 2025 14:47:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903666; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=hIuBi/1rFuUwp8AeM1BPzxwcWp+eQE6OQjarXfBjdmM=; b=ukmIk4/koyR30YSdaO1nYxVxYMNGFrNvT2+sFAsgltlhws0uBsYVv4rqN3KUNQkcJyprVy fWyVQlGSEZmUa3vWfPxYl5l5FtxHZLbht//vyiIJzyWpA7HjQ3jXBrWni4qKZHtjWQIPDW 9CUJCeV71MflVeFxC2Pj+0UnVdTpb4JSMs9i1G4RcUtzGw3THToW9seuHgVPEtms4WVugE pLOZvCmtFkVW1bHXdPgt+gbrjekVPdiHttxjnQGKg354NdfmI7cReiGZDbG8vwzpERe7tQ ccRYbL03l7eTHTNFVlCAS6jYJ/XUeFuZpUca7adx208p68553P8by27oBmB2ew== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:13 +0200 Subject: [PATCH 06/19] reset: eyeq: add eyeQ7H compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-6-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add support for the reset controllers found in the eyeQ7H OLB. For this, three new types of reset domain are added to the driver. The EQR_EYEQ7H_ACRP reset domain is similar to the EQR_EYEQ5_ACRP domain with a different registers layout. The EQR_EYEQ7H_CFG reset domain is similar to the EQR_EYEQ5_PCIE domain, again with a different registers layout. The EQR_EYEQ7H_ACC reset domain is similar to the EQR_EYEQ6H_SARCR domain, with a different registers layout and no busy waiting. Signed-off-by: Sari Khoury Signed-off-by: Beno=C3=AEt Monin --- drivers/reset/reset-eyeq.c | 248 +++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 246 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c index 02d50041048b42921e3e511148cd29f215b5fc5e..322c05d7e6b818e5b0d395787c6= 9ad91616820e0 100644 --- a/drivers/reset/reset-eyeq.c +++ b/drivers/reset/reset-eyeq.c @@ -1,10 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms. + * Reset driver for the Mobileye EyeQ5, EyeQ6L, EyeQ6H and EyeQ7H platform= s. * * Controllers live in a shared register region called OLB. EyeQ5 and EyeQ= 6L * have a single OLB instance for a single reset controller. EyeQ6H has se= ven - * OLB instances; three host reset controllers. + * OLB instances; three host reset controllers. EyeQ7H has fourteen OLB in= stances; + * eleven host reset controllers. * * Each reset controller has one or more domain. Domains are of a given ty= pe * (see enum eqr_domain_type), with a valid offset mask (up to 32 resets p= er @@ -61,6 +62,40 @@ * 9. PMA0 10. PMA1 11. MPC0 12. MPC1 * 13. MPC2 14. MPC3 15. PERIPH * + * Known resets in EyeQ7H south (type EQR_EYEQ7H_CFG) + * 0. PCI_PHY 1. PCI_CTL 2. S_NOC 3. GBE_PHY + * 4. GBE_CTL 5. XSPI 6. UFS 7. VDIO + * + * Known resets in EyeQ7H east (type EQR_EYEQ7H_CFG) + * 0. ISP 2. VEU 3. LBIST + * + * Known resets in EyeQ7H west (type EQR_EYEQ7H_CFG) + * 0. GPU 2. CAU 3. LBIST 4. GPU_LBIST + * + * Known resets in EyeQ7H periph (type EQR_EYEQ5_SARCR) + * 0. gpio 1.EXT TIMER 3.UART 4. SPI + * 5. I2C0 6. I2C1 7.I2C2 8. I2S + * + * Known resets in EyeQ7H ddr (type EQR_EYEQ7H_CFG) + * 0. APB 2. DMI 3. DFI 4. PHY_SMS + * 5. CTL_SMS + * + * Known resets in EyeQ7H acc (type EQR_EYEQ7H_ACRP) + * 1. VMP0 2. XVMP1 3. VMP2 4. VMP3 + * 5. MPC0 6. MPC1 7. PMA0 8. PMA1 + * + * Known resets in EyeQ7H acc (type EQR_EYEQ7H_ACC) + * 1. NCORE0 2. NCORE1 3. NCORE0_M 4. NCORE1_M + * 5. NCORE_NOC 6. VMP_NOC 7. MPC_NOC 8. PMA_NOC + * + * Known resets in EyeQ7H xnn (type EQR_EYEQ7H_ACRP) + * 1. XNN0 2. XNN1 3.XNN2 + * + * Known resets in EyeQ7H xnn (type EQR_EYEQ7H_ACC) + * 1. XNN0 2. XNN1 3. XNN2 4. XNN3 + * 5. NCORE 6. I2_0 7. I2_1 8. SMS_0 + * 9. SMS_1 + * * Abbreviations: * - PMA: Programmable Macro Array * - MPC: Multi-threaded Processing Clusters @@ -102,6 +137,9 @@ enum eqr_domain_type { EQR_EYEQ5_ACRP, EQR_EYEQ5_PCIE, EQR_EYEQ6H_SARCR, + EQR_EYEQ7H_ACRP, + EQR_EYEQ7H_CFG, + EQR_EYEQ7H_ACC }; =20 /* @@ -126,6 +164,21 @@ enum eqr_domain_type { #define EQR_EYEQ6H_SARCR_RST_STATUS (0x008) #define EQR_EYEQ6H_SARCR_CLK_REQUEST (0x00C) =20 +/* + * Domain type EQR_EYEQ7H_ACRP register masks. + * Registers are: base + 4 * offset. + */ +#define EQR_EYEQ7H_ACRP_PD_REQ BIT(0) +#define EQR_EYEQ7H_ACRP_MBIST_CFG GENMASK(3, 1) +#define EQR_EYEQ7H_ACRP_ST_POWER_DOWN BIT(13) +#define EQR_EYEQ7H_ACRP_ST_ACTIVE BIT(14) + +/* + * Domain type EQR_EYEQ7H_ACC register masks. + */ +#define EQR_EYEQ7H_ACC_CLK_EN (0x000) +#define EQR_EYEQ7H_ACC_RST_EN (0x004) + struct eqr_busy_wait_timings { unsigned long sleep_us; unsigned long timeout_us; @@ -134,7 +187,10 @@ struct eqr_busy_wait_timings { static const struct eqr_busy_wait_timings eqr_timings[] =3D { [EQR_EYEQ5_SARCR] =3D {1, 10}, [EQR_EYEQ5_ACRP] =3D {1, 40 * USEC_PER_MSEC}, /* LBIST implies long timeo= ut. */ + [EQR_EYEQ7H_ACRP] =3D {1, 40 * USEC_PER_MSEC}, /* EQR_EYEQ5_PCIE does no busy waiting. */ + /* EQR_EYEQ7H_CFG does no busy waiting. */ + /* EQR_EYEQ7H_ACC does no busy waiting. */ [EQR_EYEQ6H_SARCR] =3D {1, 400}, }; =20 @@ -209,6 +265,17 @@ static int eqr_busy_wait_locked(struct eqr_private *pr= iv, struct device *dev, sleep_us, timeout_us); break; =20 + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + if (assert) + mask =3D EQR_EYEQ7H_ACRP_ST_POWER_DOWN; + else + mask =3D EQR_EYEQ7H_ACRP_ST_ACTIVE; + + ret =3D readl_poll_timeout(reg, val, !!(val & mask), + sleep_us, timeout_us); + break; + case EQR_EYEQ5_PCIE: ret =3D 0; /* No busy waiting. */ break; @@ -229,6 +296,14 @@ static int eqr_busy_wait_locked(struct eqr_private *pr= iv, struct device *dev, &rst_status, &clk_status); break; =20 + case EQR_EYEQ7H_CFG: + ret =3D 0; /* No busy waiting. */ + break; + + case EQR_EYEQ7H_ACC: + ret =3D 0; /* No busy waiting. */ + break; + default: WARN_ON(1); ret =3D -EINVAL; @@ -261,6 +336,11 @@ static void eqr_assert_locked(struct eqr_private *priv= , u32 domain, u32 offset) writel(readl(reg) | EQR_EYEQ5_ACRP_PD_REQ, reg); break; =20 + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + writel((readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG) | EQR_EYEQ7H_ACRP_PD_RE= Q, reg); + break; + case EQR_EYEQ5_PCIE: writel(readl(base) & ~BIT(offset), base); break; @@ -273,6 +353,18 @@ static void eqr_assert_locked(struct eqr_private *priv= , u32 domain, u32 offset) writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST); break; =20 + case EQR_EYEQ7H_CFG: + writel(readl(base) & ~BIT(2 * offset) & ~BIT(2 * offset + 1), base); + break; + + case EQR_EYEQ7H_ACC: + /* RST_REQUEST and CLK_REQUEST must be kept in sync. */ + val =3D readl(base + EQR_EYEQ7H_ACC_RST_EN); + val &=3D ~BIT(offset); + writel(val, base + EQR_EYEQ7H_ACC_RST_EN); + writel(val, base + EQR_EYEQ7H_ACC_CLK_EN); + break; + default: WARN_ON(1); break; @@ -315,6 +407,11 @@ static void eqr_deassert_locked(struct eqr_private *pr= iv, u32 domain, writel(readl(reg) & ~EQR_EYEQ5_ACRP_PD_REQ, reg); break; =20 + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + writel((readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG) & ~EQR_EYEQ7H_ACRP_PD_R= EQ, reg); + break; + case EQR_EYEQ5_PCIE: writel(readl(base) | BIT(offset), base); break; @@ -327,6 +424,18 @@ static void eqr_deassert_locked(struct eqr_private *pr= iv, u32 domain, writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST); break; =20 + case EQR_EYEQ7H_CFG: + writel(readl(base) | BIT(2 * offset) | BIT(2 * offset + 1), base); + break; + + case EQR_EYEQ7H_ACC: + /* RST_REQUEST and CLK_REQUEST must be kept in sync. */ + val =3D readl(base + EQR_EYEQ7H_ACC_RST_EN); + val |=3D BIT(offset); + writel(val, base + EQR_EYEQ7H_ACC_RST_EN); + writel(val, base + EQR_EYEQ7H_ACC_CLK_EN); + break; + default: WARN_ON(1); break; @@ -368,11 +477,19 @@ static int eqr_status(struct reset_controller_dev *rc= dev, unsigned long id) case EQR_EYEQ5_ACRP: reg =3D base + 4 * offset; return !(readl(reg) & EQR_EYEQ5_ACRP_ST_ACTIVE); + case EQR_EYEQ7H_ACRP: + reg =3D base + 4 * offset; + return !(readl(reg) & EQR_EYEQ7H_ACRP_ST_ACTIVE); case EQR_EYEQ5_PCIE: return !(readl(base) & BIT(offset)); case EQR_EYEQ6H_SARCR: reg =3D base + EQR_EYEQ6H_SARCR_RST_STATUS; return !(readl(reg) & BIT(offset)); + case EQR_EYEQ7H_CFG: + return !(readl(base) & BIT(2 * offset)); + case EQR_EYEQ7H_ACC: + reg =3D base + EQR_EYEQ7H_ACC_RST_EN; + return !(readl(reg) & BIT(offset)); default: return -EINVAL; } @@ -537,6 +654,113 @@ static const struct eqr_match_data eqr_eyeq6h_acc_dat= a =3D { .domains =3D eqr_eyeq6h_acc_domains, }; =20 +static const struct eqr_domain_descriptor eqr_eyeq7h_south_domains[] =3D { + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0x1F, + .offset =3D 0x070, + }, + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0x7, + .offset =3D 0x074, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_south_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_south_domains), + .domains =3D eqr_eyeq7h_south_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_east_domains[] =3D { + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0x7, + .offset =3D 0x060, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_east_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_east_domains), + .domains =3D eqr_eyeq7h_east_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_west_domains[] =3D { + { + .type =3D EQR_EYEQ7H_CFG, + .valid_mask =3D 0xf, + .offset =3D 0x068, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_west_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_west_domains), + .domains =3D eqr_eyeq7h_west_domains, +}; + +/* Periph OLBs each have an instance. */ +static const struct eqr_domain_descriptor eqr_eyeq7h_per_domains[] =3D { + { + .type =3D EQR_EYEQ6H_SARCR, + .valid_mask =3D 0xFF, + .offset =3D 0x030, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_per_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_per_domains), + .domains =3D eqr_eyeq7h_per_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_ddr_domains[] =3D { + { + .type =3D EQR_EYEQ7H_ACRP, + .valid_mask =3D 0x1F, + .offset =3D 0x008, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_ddr_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_ddr_domains), + .domains =3D eqr_eyeq7h_ddr_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_acc_domains[] =3D { + { + .type =3D EQR_EYEQ7H_ACRP, + .valid_mask =3D 0xFF, + .offset =3D 0x000, + }, + { + .type =3D EQR_EYEQ7H_ACC, + .valid_mask =3D 0xFF, + .offset =3D 0x060, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_acc_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_acc_domains), + .domains =3D eqr_eyeq7h_acc_domains, +}; + +static const struct eqr_domain_descriptor eqr_eyeq7h_xnn_domains[] =3D { + { + .type =3D EQR_EYEQ7H_ACRP, + .valid_mask =3D 0x7, + .offset =3D 0x000, + }, + { + .type =3D EQR_EYEQ7H_ACC, + .valid_mask =3D 0x1FF, + .offset =3D 0x060, + }, +}; + +static const struct eqr_match_data eqr_eyeq7h_xnn_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq7h_xnn_domains), + .domains =3D eqr_eyeq7h_xnn_domains, +}; + /* * Table describes OLB system-controller compatibles. * It does not get used to match against devicetree node. @@ -547,6 +771,17 @@ static const struct of_device_id eqr_match_table[] =3D= { { .compatible =3D "mobileye,eyeq6h-west-olb", .data =3D &eqr_eyeq6h_we_da= ta }, { .compatible =3D "mobileye,eyeq6h-east-olb", .data =3D &eqr_eyeq6h_we_da= ta }, { .compatible =3D "mobileye,eyeq6h-acc-olb", .data =3D &eqr_eyeq6h_acc_da= ta }, + { .compatible =3D "mobileye,eyeq7h-south-olb", .data =3D &eqr_eyeq7h_sout= h_data }, + { .compatible =3D "mobileye,eyeq7h-east-olb", .data =3D &eqr_eyeq7h_east_= data }, + { .compatible =3D "mobileye,eyeq7h-west-olb", .data =3D &eqr_eyeq7h_west_= data }, + { .compatible =3D "mobileye,eyeq7h-periph-east-olb", .data =3D &eqr_eyeq7= h_per_data }, + { .compatible =3D "mobileye,eyeq7h-periph-west-olb", .data =3D &eqr_eyeq7= h_per_data }, + { .compatible =3D "mobileye,eyeq7h-ddr0-olb", .data =3D &eqr_eyeq7h_ddr_d= ata }, + { .compatible =3D "mobileye,eyeq7h-ddr1-olb", .data =3D &eqr_eyeq7h_ddr_d= ata }, + { .compatible =3D "mobileye,eyeq7h-acc0-olb", .data =3D &eqr_eyeq7h_acc_d= ata }, + { .compatible =3D "mobileye,eyeq7h-acc1-olb", .data =3D &eqr_eyeq7h_acc_d= ata }, + { .compatible =3D "mobileye,eyeq7h-xnn0-olb", .data =3D &eqr_eyeq7h_xnn_d= ata }, + { .compatible =3D "mobileye,eyeq7h-xnn1-olb", .data =3D &eqr_eyeq7h_xnn_d= ata }, {} }; MODULE_DEVICE_TABLE(of, eqr_match_table); @@ -556,6 +791,15 @@ static const struct auxiliary_device_id eqr_id_table[]= =3D { { .name =3D "clk_eyeq.reset_west" }, { .name =3D "clk_eyeq.reset_east" }, { .name =3D "clk_eyeq.reset_acc" }, + { .name =3D "clk_eyeq.reset_south" }, + { .name =3D "clk_eyeq.reset_periph_east" }, + { .name =3D "clk_eyeq.reset_periph_west" }, + { .name =3D "clk_eyeq.reset_ddr0" }, + { .name =3D "clk_eyeq.reset_ddr1" }, + { .name =3D "clk_eyeq.reset_acc0" }, + { .name =3D "clk_eyeq.reset_acc1" }, + { .name =3D "clk_eyeq.reset_xnn0" }, + { .name =3D "clk_eyeq.reset_xnn1" }, {} }; MODULE_DEVICE_TABLE(auxiliary, eqr_id_table); --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EE96303CA0; Wed, 3 Sep 2025 12:47:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903672; cv=none; b=dLkA2sc7iYV/CPj+M6NDR+KGHSNTNC0rpvDw6qEWbiAwXhuGxUs2KQHDCNyhS1TO+jsa/gyRC07kvl3ZXRmpulFYVG91xmuAwAx68Ivo4BXxd0fTgh/Otiv8gv1MYyq82BRgaorrxMlxNXr4zrTXZKTKenUf1Nh95wF4mipRmgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903672; c=relaxed/simple; bh=xi/o5kWUDoeVTEz8CVGVlsZgn5M7wM6SPz+7rGGvINI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GCbIn+vTgR9W9qzZF7fUMQKZmi61dKsJy8MrQNASqVzZhU0INJWC+kh9CbTTuAAVeCTpqBoe2P/AG0EOpYqbKR4xenNdFjoSVTQlPWZfK/wEdTNJ01+cVIH5LFiPGXZYwFNdh14+g6UMaAsukPRFB5k21oBBF3JI0dbu4iapo5k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=VaKRUXVN; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="VaKRUXVN" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id E6FE64E40C0A; Wed, 3 Sep 2025 12:47:48 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id BE967606C3; Wed, 3 Sep 2025 12:47:48 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 632151C22A4EA; Wed, 3 Sep 2025 14:47:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903667; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=PLsxsB1U7iOyjFs0v18bA/rl5OjxWvCZDmHawmPZZz0=; b=VaKRUXVNW1hH2ngZ83GKCpeYB71UlbdWGaAnVXDR6khs42dk+ZPVba9/Y+r3fgSRKxbBYr V1KZEsQkM9iULoJifNqozKspb9vrDKKuKwf/3Rf51tKzGcWRD0hU98KDekM5CsAnxpXE95 0Kez+MQ4EhbINEUu8XDeNi96rVwghLEoBSgQSzpeCW3+/yuQPpeidT5E+zJry4aHRVXffY AkQu/7JsyotXaA4LwPsaXXy8znrBfwVg7F/yLWNyS3evOQDPqymZRijzPVPR9SRFU88ztP RIWqVXpJwZRoHl5ECISm+ikzziNt51naM8pYgPyChfOfQlclXjamCQw7gZgLmw== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:14 +0200 Subject: [PATCH 07/19] clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-7-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add a variant of clk_hw_register_fixed_factor allowing to set the accuracy of the fixed factor clock. This function allows declaring a fixed factor with a known accuracy and a parent clock by name. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-fixed-factor.c | 12 ++++++++++++ include/linux/clk-provider.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index e62ae8794d445f685156276d5135448f340fca3f..7c76658a725f9b268da24857699= 79e5ba213d25b 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -217,6 +217,18 @@ struct clk_hw *clk_hw_register_fixed_factor(struct dev= ice *dev, } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); =20 +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy(struct device *d= ev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div, unsigned long acc) +{ + const struct clk_parent_data pdata =3D { .index =3D -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, acc, + CLK_FIXED_FACTOR_FIXED_ACCURACY, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy); + struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, struct device_node *np, const char *name, const char *fw_name, unsigned long flags, unsigned int mult, unsigned int div) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 630705a47129453c241f1b1755f2c2f2a7ed8f77..6b3e426f5754bfae4af89765bf5= abd2954ca49dc 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1153,6 +1153,9 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy(struct device *d= ev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div, unsigned long acc); struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, struct device_node *np, const char *name, const char *fw_name, unsigned long flags, unsigned int mult, unsigned int div); --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C457430274F; Wed, 3 Sep 2025 12:47:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903675; cv=none; b=NGqNAiFBnlU+XzHkx4AAh1hGd+I5Upaevif43Ph53uXEjrH/2Fglb8rrTYKmOz2sSLj75Sb2DShCFc5kTCx6GXDE74OGGevSzfuYxg6u8SZWCm635sTVEJd8JVNy1U6UauQfYxuwcVF5jb/0eSR18Na6Sh8rAyt8i0174BLsOuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903675; c=relaxed/simple; bh=DrpsGRl2lWVxg8jgfjmuky3LsdH9Ow5e5tUE+I/Ksys=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rJ0C4gIgMsP6Bs4BLs1elCXeHu2hyHoYsh8Pd4NMTTJs+j08rLGLsfdIF5yi7KylCfNhO5zWhhbrXPukQEvMBi1kSP/fjR6lw1S7ozYS6AckcP7t+Fr2M4ML5UY5O9z3TmbBGcs8zW+ozOKaDIMwJOF++tAFs3gtOoal9rzKrcE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=vUQbL9qa; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="vUQbL9qa" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 2C8E44E40C12; Wed, 3 Sep 2025 12:47:51 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0617D606C3; Wed, 3 Sep 2025 12:47:51 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 211331C22C3F8; Wed, 3 Sep 2025 14:47:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903669; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=C+XaOZ1nGya7Ny+Ft3/Ooh9qVsU2Acl6gHch2FC2Uvc=; b=vUQbL9qadf+K5EOnSVLM4F2NxWru936xLq7zTMYAAxatsuc39EeLWE7eX5Lvq49R2IoFyn +kL+tT1B7Xvf/4YdVRKCGUmBdaiXQwaDzsXbj4nTV9XbYvFXLqUGfWPa8HH0bZiBzR5wQQ GXLe1xhVumhVUvMhdgkEOm07hL9M2f8JAq5Rnd5IbjmYVyqDft5S5JXcN7x0G37XCvBPKS XcnLYcDPWZkyxhifUR7cYrDbh3BG1xeMSsv/D6WFGlixRBtxTUSCOnqGl8cOg8cWsED29v HovHa0+AlQYhzEW2lJ5kJ9I7vcWKSK1y8q2tVtqFE0Who3wwdD/+jKPFE/L3nQ== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:15 +0200 Subject: [PATCH 08/19] clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-8-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Ensure that the divider is even when the flag CLK_DIVIDER_EVEN_INTEGERS is set, similar to the power of two check for CLK_DIVIDER_POWER_OF_TWO. Signed-off-by: Vladimir Kondratiev Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-divider.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index c1f426b8a5043cb5a1de08e1da385928ec54a2ed..8e8f87024e76625f348f1d66c15= a7a938fa0c4db 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -181,6 +181,8 @@ static bool _is_valid_div(const struct clk_div_table *t= able, unsigned int div, { if (flags & CLK_DIVIDER_POWER_OF_TWO) return is_power_of_2(div); + if (flags & CLK_DIVIDER_EVEN_INTEGERS) + return (div % 2) =3D=3D 0; if (table) return _is_valid_table_div(table, div); return true; --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DDDF302770 for ; Wed, 3 Sep 2025 12:47:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903678; cv=none; b=sB7ZrFb5czKkarJZTEQvLoFMDDAnQBBwN8gJDlpUugCNTwpsdvzZJNW3e65FphDHZg3pFfwhL74pYZEZVeS+WyEBn8kz/PIp6skBXTrTDpOCY5OBiTRVi7SY/LHTI91+9oO5VTqomtUz+pXnX3IfhArzNp2LugOb69/raxVPyUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903678; c=relaxed/simple; bh=tkW5x3xXgltuqbCsN7rkr+c/J/FoTke8ujqu3am9bUk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CHpmjpXi4XQbWpc3/S4jQcXFKjpnPGFlgdcYMdFmarJgn9cJajMvzOXWrtC4eJxtNHnA5/AvNm+DMANAVOY82vGTamRVsHVS4+nG2x9VSMrd2nTyiEMiCUIWtz6zQ+7856b0JXJXDM14iOd1LAGjnBR+CWR7nJy+SaC/6ZG0dhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=MMsVVr8/; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="MMsVVr8/" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id EA4A3C8EC51; Wed, 3 Sep 2025 12:47:37 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 06F94606C3; Wed, 3 Sep 2025 12:47:53 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 482C51C22DBAD; Wed, 3 Sep 2025 14:47:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903672; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Zu15Dv3rwzhMYuygTnnYcdnEv58fMlFkI0F/4ADcw+s=; b=MMsVVr8/kQM8Ys1kXWXlOx653qiHZ/L2OR9Wi2bumgdoXhP2WwfnCYrBAUuNhng+jo5eWe ZkE2ud/tcvf8gxGe4ajMSMSYyKdzZFdNl72MhiWAjF6lEsJ8SkkrdisuMNElHhcnMsj0vx McOLrjh2paiPyLrkXztMd/dAGFF1NGlJ+iF+dzfeAX8nraGxvP+4tGrz74Dzb8EinVs7z5 /aHi/w6FK4G8zaYXKNAot0GTFaPi6rdUcVZ1Kp2JUF10RzY02d194RT3APjhhLfVKmU/Ar 7MKB3K4aWpNRuJXp0YjZmxNIdli92A2bY/hJ+RGs8VaKcb6YZoQV7OLY0Jf/bw== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:16 +0200 Subject: [PATCH 09/19] clk: divider: check validity of flags when a table is provided Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-9-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 If any of the flag CLK_DIVIDER_ONE_BASED, CLK_DIVIDER_POWER_OF_TWO, CLK_DIVIDER_MAX_AT_ZERO or CLK_DIVIDER_EVEN_INTEGERS is set, the divider table will be ignored in _get_div and _get_val. This can lead to subtle bug when a clock is registered with some flags and an optional table, with the clock rate and register value being computed with the wrong type of conversion. Prevent this by refusing to register a divider with both the flag and the table set. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-divider.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 8e8f87024e76625f348f1d66c15a7a938fa0c4db..b4861d519bac2121dd015d094c9= 4a5fee2480148 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -561,6 +561,13 @@ struct clk_hw *__clk_hw_register_divider(struct device= *dev, return ERR_PTR(-EINVAL); } } + if (table && (clk_divider_flags & (CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_POWER_OF_TWO | + CLK_DIVIDER_MAX_AT_ZERO | + CLK_DIVIDER_EVEN_INTEGERS))) { + pr_warn("divider table and flags incompatible\n"); + return ERR_PTR(-EINVAL); + } =20 /* allocate the divider */ div =3D kzalloc(sizeof(*div), GFP_KERNEL); --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60F712FB63C for ; Wed, 3 Sep 2025 12:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903681; cv=none; b=OipLAzGjwVTIjEigvCSr7im71RpMGJ95n17R6VfRcQpqZL7GmgmMsC2Ph3quY8PtHDPTPAJGfgu8EBNfYHZYWytL1XQnUh8weHqodGvFwroe+vlwxcFBWtlhYpjTNCg8GoCCWrhlYg4l4iR8FJJM9i6Kc7NHi7XgH7J3bPZ2Rts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903681; c=relaxed/simple; bh=8rmzqvfR/jLcrU3Ww14o338baqPR0EMUTSwyH3c+BkM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QhDO3tRULAaIhZR6ACTmRtTqDdhfRl/+BYV3nIkqWjymt0igfWOM/8644L0gY7w6qJM7o9yPCXkt7kVqR60MX9/RUbHKa/PNYEm1mk/K3v1emI//ESE+2w61YlP3YCt+R2gN27MZryMV+DdBff+ZynAnvjVRBTZYsJf6KwIxyAM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=PKdUv+R8; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="PKdUv+R8" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id D66F94E40C0A; Wed, 3 Sep 2025 12:47:54 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id AFE56606C3; Wed, 3 Sep 2025 12:47:54 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4EE471C22A4EA; Wed, 3 Sep 2025 14:47:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903673; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=12E/BElr5gCYI8YsYwHlrC7l4pZjCd49Xorz7J+azFg=; b=PKdUv+R8aFTvVO0OQ3WlDQproDTLqPa1so9i7de2hVOQC3W7lsrpqdcJWFoIn4pxE0O4C3 Qi8O8smdxUARN2ZFzHRVheGxed4P/uUchwEKSfs+9he9GbvKErT2jVlQy69+mnmr7sCTu2 oRLzHv85R6ADboqYZKwd8Tg4EqpRXf/kcN34FJ3uqPVzpQbtNflMyxoCxpA0W1ld7O2qon aRy/IXjcaJy+9TkWBImuYAiMqVE7rHX4pfBLSUDd67+X6D4KlZVEJ8HZVRKCESOQsYckgR FyCYdtDq/2mxmNmh3JuHSiOHARGLAm0WyHQYEvM5cM1QxY989n4I756iOkyl0g== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:17 +0200 Subject: [PATCH 10/19] clk: eyeq: skip post-divisor when computing pll divisor Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-10-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The output of the pll is routed before the post-divisor so ignore it when computing the frequency of the pll, functional change is implemented to reflect how the clock signal is wired internally. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 8fbc8eb31185a9e82216a38a81dfbdaa1a700858..cbba4a21cca47efb8ab554ecf73= 22e47437c9c6a 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -177,8 +177,6 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsi= gned long *mult, =20 *mult =3D FIELD_GET(PCSR0_INTIN, r0); *div =3D FIELD_GET(PCSR0_REF_DIV, r0); - if (r0 & PCSR0_FOUTPOSTDIV_EN) - *div *=3D FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0= ); =20 /* Fractional mode, in 2^20 (0x100000) parts. */ if (r0 & PCSR0_DSM_EN) { --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B962E3009FE; Wed, 3 Sep 2025 12:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903682; cv=none; b=EBGChezN8dGNQHeeSIAL7DGzQr+QuOzz7P4idpvTe/EMzgipaIUEPRqXceQo8NfIAl0Vh1hbHq8T8iE6yKsheVpLcxCAfrahpbkOPKfpsmC7dXJ8OkevMvdAsIvUNRaIl0l1vDADNHu8X0qB3nVrd9AF3O9/MCnV+5hZ9PTf4GA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903682; c=relaxed/simple; bh=t9Cj2vsk9A2IypF0ZbhgnScvYQTKAJSuu1sLgL93Sw0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TrtN6P4htfyHBIGYzVXquymiYBDEdXkMcNfuti0SmSY7PDULztwGl8s4n0eZ5VWFoi2td7lPHWAD2iVHSrXobDFKFnF+ESMDyRV/Obc/tcYNERhDLISN9tL2reMbCz7dOwcns7GPWoKSBXwgHMW89HRK4rAQT3WGK/U+D2TX/dU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=MDKetlJE; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="MDKetlJE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 99B581A08CE; Wed, 3 Sep 2025 12:47:57 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 72788606C3; Wed, 3 Sep 2025 12:47:57 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 100511C228A5D; Wed, 3 Sep 2025 14:47:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903675; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=cG4E+ChNi7Pq9aaCdZ3+CMHo9z6hvO9a8YfEiX5GW9w=; b=MDKetlJEgtj5kCgTTIDxg7bUP//0qIPgaS2Y99jXiJ4vb9v0pATsiERS2r8tFnY4Ifxnry gQV58rNFDRbX9gxdlPbOzhvdYV3NyoV5oCbRAfyaoYbbDc7MtrXjnEn4Xqrdt/NThvfLvf Q/XNBsp3z5m4PCrtPo54D315K+lmO4zjzaDY57JR8ObJ9ujozEUo74UjEyTtL/A0v8C6JS ixFPTehfn7wlegKeOtmTc78AcIGLHGkrvAZOKDCnTfhLZAEKStzdcuZ8pruJBnIyEnPmCM pJnKCpbxiLEy5SK0Nvgia3I8Xcr28Xe88lonYnKtmXvK3017XH4And8R5UjiwA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:18 +0200 Subject: [PATCH 11/19] clk: eyeq: rename the parent field to parent_idx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-11-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Make some room for introducing a new field to refer to the parent clock by its name for divisors and fixed factors. No functional code change in this patch, this is a rename only. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index cbba4a21cca47efb8ab554ecf7322e47437c9c6a..89e0782b5cbe16a7c2010d9d441= ace139fd0deb5 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -83,7 +83,7 @@ struct eqc_pll { struct eqc_div { unsigned int index; const char *name; - unsigned int parent; + unsigned int parent_idx; unsigned int reg; u8 shift; u8 width; @@ -94,7 +94,7 @@ struct eqc_fixed_factor { const char *name; unsigned int mult; unsigned int div; - unsigned int parent; + unsigned int parent_idx; }; =20 struct eqc_match_data { @@ -269,11 +269,11 @@ static void eqc_probe_init_divs(struct device *dev, c= onst struct eqc_match_data for (i =3D 0; i < data->div_count; i++) { div =3D &data->divs[i]; reg =3D base + div->reg; - parent =3D cells->hws[div->parent]; + parent =3D cells->hws[div->parent_idx]; =20 if (IS_ERR(parent)) { /* Parent is in early clk provider. */ - parent_data.index =3D div->parent; + parent_data.index =3D div->parent_idx; parent_data.hw =3D NULL; } else { /* Avoid clock lookup when we already have the hw reference. */ @@ -301,12 +301,12 @@ static void eqc_probe_init_fixed_factors(struct devic= e *dev, =20 for (i =3D 0; i < data->fixed_factor_count; i++) { ff =3D &data->fixed_factors[i]; - parent_hw =3D cells->hws[ff->parent]; + parent_hw =3D cells->hws[ff->parent_idx]; =20 if (IS_ERR(parent_hw)) { /* Parent is in early clk provider. */ hw =3D clk_hw_register_fixed_factor_index(dev, ff->name, - ff->parent, 0, ff->mult, ff->div); + ff->parent_idx, 0, ff->mult, ff->div); } else { /* Avoid clock lookup when we already have the hw reference. */ hw =3D clk_hw_register_fixed_factor_parent_hw(dev, ff->name, @@ -522,7 +522,7 @@ static const struct eqc_div eqc_eyeq5_divs[] =3D { { .index =3D EQ5C_DIV_OSPI, .name =3D "div-ospi", - .parent =3D EQ5C_PLL_PER, + .parent_idx =3D EQ5C_PLL_PER, .reg =3D 0x11C, .shift =3D 0, .width =3D 4, @@ -597,7 +597,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_EMMC, .name =3D "div-emmc", - .parent =3D EQ6HC_SOUTH_PLL_PER, + .parent_idx =3D EQ6HC_SOUTH_PLL_PER, .reg =3D 0x070, .shift =3D 4, .width =3D 4, @@ -605,7 +605,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_OSPI_REF, .name =3D "div-ospi-ref", - .parent =3D EQ6HC_SOUTH_PLL_PER, + .parent_idx =3D EQ6HC_SOUTH_PLL_PER, .reg =3D 0x090, .shift =3D 4, .width =3D 4, @@ -613,7 +613,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_OSPI_SYS, .name =3D "div-ospi-sys", - .parent =3D EQ6HC_SOUTH_PLL_PER, + .parent_idx =3D EQ6HC_SOUTH_PLL_PER, .reg =3D 0x090, .shift =3D 8, .width =3D 1, @@ -621,7 +621,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] =3D= { { .index =3D EQ6HC_SOUTH_DIV_TSU, .name =3D "div-tsu", - .parent =3D EQ6HC_SOUTH_PLL_PCIE, + .parent_idx =3D EQ6HC_SOUTH_PLL_PCIE, .reg =3D 0x098, .shift =3D 4, .width =3D 8, @@ -790,7 +790,7 @@ static void __init eqc_early_init(struct device_node *n= p, =20 for (i =3D 0; i < early_data->early_fixed_factor_count; i++) { const struct eqc_fixed_factor *ff =3D &early_data->early_fixed_factors[i= ]; - struct clk_hw *parent_hw =3D cells->hws[ff->parent]; + struct clk_hw *parent_hw =3D cells->hws[ff->parent_idx]; struct clk_hw *hw; =20 hw =3D clk_hw_register_fixed_factor_parent_hw(NULL, ff->name, --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C9953009DE for ; Wed, 3 Sep 2025 12:48:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903684; cv=none; b=NFNs0S17YKTkkuBv7O3e0WfAqV9ev3mElV4M4u5N0WwhQqHwpGttIKwTWvU9ZYVNZechSek7S+W3a7IcPLPPSfNaWW74Huw1qaoWdHmmQXpUCTLJA6QCpMYIuXmjDek5vX5WUsvV93Z1S6pb4YSPWtklb1nnuUn8PQMmQ5nbuZo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903684; c=relaxed/simple; bh=RkW5y4rZ49JdAHh0nxP4TIpnjzpp214s3igwWvMZVFE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PDkr6oWO8MYk0wzR6Ort/Iwu7drSv8kAYBqxhfUXmDtJ8C9bx2EENDYPM6YQphnD1h/eXBYzQncU6ZakrODjZQtyLJQ2aBufXi+lrhh/Sc5RRCDWvZ+AhFF2uDoLeFB73LRN41g7r8/DeI/snWO/1cqaQMkZH0HusIiu7d8+7UM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LqP0HypL; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LqP0HypL" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 7833EC8EC51; Wed, 3 Sep 2025 12:47:44 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 89D2C606C3; Wed, 3 Sep 2025 12:47:59 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A4A8A1C22C3F8; Wed, 3 Sep 2025 14:47:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903678; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=/VSLyI+Ovanq4kgxvJjgjN4r0Yaa6e1OA7Uan/Os3TY=; b=LqP0HypLLhdL+74Ib7TF+9WC3yi5nvcCu1q0lhfqVCfNNA3oifrSourQlUhDKzQ1pBcE2U wqyF5VH0EESeOxh6hBctpY5THV2/eJaG+8tZCffnD/AoQgGgdud/42lT5kmgTBQuRFXlC4 7tVUcJR3d8Lhw6AuVARir4lelSdGoXPLdFVLeAlqKFhwGG1miYdIizRjDM6NRCwlUHym9I OLDAN40w9cIfk6aXn6gQJ8MDiSMiuwnUMD9qjkXYdgaplNbtCSKyHcpdNKdwk4NTwUcgJZ pp6GY9GMnteBf5o4dfnJzq7rnbLHXsFVDgoToswlhBd4hDYgWU1o+QqaYFC2Xg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:19 +0200 Subject: [PATCH 12/19] clk: eyeq: lookup parent clock by name Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-12-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 When registering a divider or a fixed factor during probe, lookup its parent by name if the parent clock was registered early. Looking up the parent clock by index in this case leads to orphaned clocks or clocks with the wrong parent, since the index refers to clocks from the device tree. This is applicable to the eyeQ5 where some probed dividers and fixed factors refer to PLL and fixed factors registered in early init. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 48 ++++++++++++++++++++++++++--------------------= -- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 89e0782b5cbe16a7c2010d9d441ace139fd0deb5..a0581016100c7367efb373a3fb3= b7c6d51b49912 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -84,6 +84,7 @@ struct eqc_div { unsigned int index; const char *name; unsigned int parent_idx; + const char *parent_name; unsigned int reg; u8 shift; u8 width; @@ -95,6 +96,7 @@ struct eqc_fixed_factor { unsigned int mult; unsigned int div; unsigned int parent_idx; + const char *parent_name; }; =20 struct eqc_match_data { @@ -273,7 +275,8 @@ static void eqc_probe_init_divs(struct device *dev, con= st struct eqc_match_data =20 if (IS_ERR(parent)) { /* Parent is in early clk provider. */ - parent_data.index =3D div->parent_idx; + parent_data.index =3D -1; + parent_data.name =3D div->parent_name; parent_data.hw =3D NULL; } else { /* Avoid clock lookup when we already have the hw reference. */ @@ -305,8 +308,8 @@ static void eqc_probe_init_fixed_factors(struct device = *dev, =20 if (IS_ERR(parent_hw)) { /* Parent is in early clk provider. */ - hw =3D clk_hw_register_fixed_factor_index(dev, ff->name, - ff->parent_idx, 0, ff->mult, ff->div); + hw =3D clk_hw_register_fixed_factor(dev, ff->name, + ff->parent_name, 0, ff->mult, ff->div); } else { /* Avoid clock lookup when we already have the hw reference. */ hw =3D clk_hw_register_fixed_factor_parent_hw(dev, ff->name, @@ -487,35 +490,35 @@ static const struct eqc_fixed_factor eqc_eyeq5_early_= fixed_factors[] =3D { =20 static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] =3D { /* EQ5C_PLL_CPU children */ - { EQ5C_CPU_CPC, "cpc", 1, 1, EQ5C_CPU_SI_CSS0 }, - { EQ5C_CPU_CM, "cm", 1, 1, EQ5C_CPU_SI_CSS0 }, - { EQ5C_CPU_MEM, "mem", 1, 1, EQ5C_CPU_SI_CSS0 }, - { EQ5C_CPU_OCC_ISRAM, "occ-isram", 1, 2, EQ5C_PLL_CPU }, + { EQ5C_CPU_CPC, "cpc", 1, 1, EQ5C_CPU_SI_CSS0, "si-css0" }, + { EQ5C_CPU_CM, "cm", 1, 1, EQ5C_CPU_SI_CSS0, "si-css0" }, + { EQ5C_CPU_MEM, "mem", 1, 1, EQ5C_CPU_SI_CSS0, "si-css0" }, + { EQ5C_CPU_OCC_ISRAM, "occ-isram", 1, 2, EQ5C_PLL_CPU, "pll-cpu" }, { EQ5C_CPU_ISRAM, "isram", 1, 1, EQ5C_CPU_OCC_ISRAM }, - { EQ5C_CPU_OCC_DBU, "occ-dbu", 1, 10, EQ5C_PLL_CPU }, + { EQ5C_CPU_OCC_DBU, "occ-dbu", 1, 10, EQ5C_PLL_CPU, "pll-cpu" }, { EQ5C_CPU_SI_DBU_TP, "si-dbu-tp", 1, 1, EQ5C_CPU_OCC_DBU }, =20 /* EQ5C_PLL_VDI children */ - { EQ5C_VDI_OCC_VDI, "occ-vdi", 1, 2, EQ5C_PLL_VDI }, + { EQ5C_VDI_OCC_VDI, "occ-vdi", 1, 2, EQ5C_PLL_VDI, "pll-vdi" }, { EQ5C_VDI_VDI, "vdi", 1, 1, EQ5C_VDI_OCC_VDI }, - { EQ5C_VDI_OCC_CAN_SER, "occ-can-ser", 1, 16, EQ5C_PLL_VDI }, + { EQ5C_VDI_OCC_CAN_SER, "occ-can-ser", 1, 16, EQ5C_PLL_VDI, "pll-vdi" }, { EQ5C_VDI_CAN_SER, "can-ser", 1, 1, EQ5C_VDI_OCC_CAN_SER }, - { EQ5C_VDI_I2C_SER, "i2c-ser", 1, 20, EQ5C_PLL_VDI }, + { EQ5C_VDI_I2C_SER, "i2c-ser", 1, 20, EQ5C_PLL_VDI, "pll-vdi" }, =20 /* EQ5C_PLL_PER children */ - { EQ5C_PER_PERIPH, "periph", 1, 1, EQ5C_PER_OCC }, - { EQ5C_PER_CAN, "can", 1, 1, EQ5C_PER_OCC }, - { EQ5C_PER_SPI, "spi", 1, 1, EQ5C_PER_OCC }, - { EQ5C_PER_I2C, "i2c", 1, 1, EQ5C_PER_OCC }, - { EQ5C_PER_TIMER, "timer", 1, 1, EQ5C_PER_OCC }, - { EQ5C_PER_GPIO, "gpio", 1, 1, EQ5C_PER_OCC }, - { EQ5C_PER_EMMC, "emmc-sys", 1, 10, EQ5C_PLL_PER }, - { EQ5C_PER_CCF, "ccf-ctrl", 1, 4, EQ5C_PLL_PER }, - { EQ5C_PER_OCC_MJPEG, "occ-mjpeg", 1, 2, EQ5C_PLL_PER }, + { EQ5C_PER_PERIPH, "periph", 1, 1, EQ5C_PER_OCC, "occ-periph" }, + { EQ5C_PER_CAN, "can", 1, 1, EQ5C_PER_OCC, "occ-periph" }, + { EQ5C_PER_SPI, "spi", 1, 1, EQ5C_PER_OCC, "occ-periph" }, + { EQ5C_PER_I2C, "i2c", 1, 1, EQ5C_PER_OCC, "occ-periph" }, + { EQ5C_PER_TIMER, "timer", 1, 1, EQ5C_PER_OCC, "occ-periph" }, + { EQ5C_PER_GPIO, "gpio", 1, 1, EQ5C_PER_OCC, "occ-periph" }, + { EQ5C_PER_EMMC, "emmc-sys", 1, 10, EQ5C_PLL_PER, "pll-per" }, + { EQ5C_PER_CCF, "ccf-ctrl", 1, 4, EQ5C_PLL_PER, "pll-per" }, + { EQ5C_PER_OCC_MJPEG, "occ-mjpeg", 1, 2, EQ5C_PLL_PER, "pll-per" }, { EQ5C_PER_HSM, "hsm", 1, 1, EQ5C_PER_OCC_MJPEG }, { EQ5C_PER_MJPEG, "mjpeg", 1, 1, EQ5C_PER_OCC_MJPEG }, - { EQ5C_PER_FCMU_A, "fcmu-a", 1, 20, EQ5C_PLL_PER }, - { EQ5C_PER_OCC_PCI, "occ-pci-sys", 1, 8, EQ5C_PLL_PER }, + { EQ5C_PER_FCMU_A, "fcmu-a", 1, 20, EQ5C_PLL_PER, "pll-per" }, + { EQ5C_PER_OCC_PCI, "occ-pci-sys", 1, 8, EQ5C_PLL_PER, "pll-per" }, }; =20 static const struct eqc_div eqc_eyeq5_divs[] =3D { @@ -523,6 +526,7 @@ static const struct eqc_div eqc_eyeq5_divs[] =3D { .index =3D EQ5C_DIV_OSPI, .name =3D "div-ospi", .parent_idx =3D EQ5C_PLL_PER, + .parent_name =3D "pll-per", .reg =3D 0x11C, .shift =3D 0, .width =3D 4, --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57857307482 for ; Wed, 3 Sep 2025 12:48:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903685; cv=none; b=rCa5kOXhZHTAjv7DsJpiXukQKnua8bMlsGMI0dJPLApiopB/4IuXUwWZ2LG49SopoNBqSjUc4J/D0qCnMO1n2jS+Ya57BhURT6PC5OkFupCOAqQYXNfjCnHuO0XgB2wxB9ltaRNuFvtQfpw6c5653Kk4i8m0IcEbCm8BnYlp3wo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903685; c=relaxed/simple; bh=YbkzBj87bNiH9dr8n9qI7MSjJOTkbr6y/UMdoSkgchc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b8Bp8q1uUlBZinPabhgHjG2NK/g1BeAZgFg6+m4F9G7E7vWHd/HXL6Wu32hCwP07WSuEHE3RckWUosvEcPKlrY7RYXc5SgVSgOGZwnIP57sBTPskQ1jtkytaQW+8ncD7Hzbycx0oZsZA8BiBABKTTXRssxh3H0rLUgvi2HP2Nb4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BF3nfutE; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BF3nfutE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 852F04E40C0A; Wed, 3 Sep 2025 12:48:01 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5930B606C3; Wed, 3 Sep 2025 12:48:01 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C837B1C22CCD6; Wed, 3 Sep 2025 14:47:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903680; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=x+dTceR5i9aJItNSeVUHs9v1PElS49Iavdx8taEX/wI=; b=BF3nfutEUj+Fd2eM2kLx0t4H3wEUBM82BpCgKh436gGxGMfLnym2wsqciJbmMfYIAEbHrr yRNNri9FM7sez2d1k2H55hDZwSRPAoW/dD34v7NTLYl6cvbsKLnS1TOsGuEe8vvxGKNPwM hnxVspArgSKsbjWzm0LZ0sPXNr6vS3NNN4CQnWGerlk0TVyVsiBg+/cvove0nay7H37YM0 BC+E4ixLABpsAyk/IBw7pCfg85CqnU9xvWZ9YF5E8IGHy+pGZ7fGlAqDpkGXe5x7iDJYKD UL4jjl8ePyvH7tbHXnXWeTJ35HVsKnEsLjD6yXzNcZ20FD57QRhyhDNltgBdrw== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:20 +0200 Subject: [PATCH 13/19] clk: eyeq: prefix the PLL registers with the PLL type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-13-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Rename the PLL registers to make room for other PLL types that are present in the eyeQ7H. We only prefix the register with the PLL type (FRACG), no other change. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 50 +++++++++++++++++++++++++---------------------= ---- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index a0581016100c7367efb373a3fb3b7c6d51b49912..63093a3099261e6798a6752651d= 25efa1b3e7592 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -47,28 +47,28 @@ #include =20 /* In frac mode, it enables fractional noise canceling DAC. Else, no funct= ion. */ -#define PCSR0_DAC_EN BIT(0) +#define FRACG_PCSR0_DAC_EN BIT(0) /* Fractional or integer mode */ -#define PCSR0_DSM_EN BIT(1) -#define PCSR0_PLL_EN BIT(2) +#define FRACG_PCSR0_DSM_EN BIT(1) +#define FRACG_PCSR0_PLL_EN BIT(2) /* All clocks output held at 0 */ -#define PCSR0_FOUTPOSTDIV_EN BIT(3) -#define PCSR0_POST_DIV1 GENMASK(6, 4) -#define PCSR0_POST_DIV2 GENMASK(9, 7) -#define PCSR0_REF_DIV GENMASK(15, 10) -#define PCSR0_INTIN GENMASK(27, 16) -#define PCSR0_BYPASS BIT(28) +#define FRACG_PCSR0_FOUTPOSTDIV_EN BIT(3) +#define FRACG_PCSR0_POST_DIV1 GENMASK(6, 4) +#define FRACG_PCSR0_POST_DIV2 GENMASK(9, 7) +#define FRACG_PCSR0_REF_DIV GENMASK(15, 10) +#define FRACG_PCSR0_INTIN GENMASK(27, 16) +#define FRACG_PCSR0_BYPASS BIT(28) /* Bits 30..29 are reserved */ -#define PCSR0_PLL_LOCKED BIT(31) +#define FRACG_PCSR0_PLL_LOCKED BIT(31) =20 -#define PCSR1_RESET BIT(0) -#define PCSR1_SSGC_DIV GENMASK(4, 1) +#define FRACG_PCSR1_RESET BIT(0) +#define FRACG_PCSR1_SSGC_DIV GENMASK(4, 1) /* Spread amplitude (% =3D 0.1 * SPREAD[4:0]) */ -#define PCSR1_SPREAD GENMASK(9, 5) -#define PCSR1_DIS_SSCG BIT(10) +#define FRACG_PCSR1_SPREAD GENMASK(9, 5) +#define FRACG_PCSR1_DIS_SSCG BIT(10) /* Down-spread or center-spread */ -#define PCSR1_DOWN_SPREAD BIT(11) -#define PCSR1_FRAC_IN GENMASK(31, 12) +#define FRACG_PCSR1_DOWN_SPREAD BIT(11) +#define FRACG_PCSR1_FRAC_IN GENMASK(31, 12) =20 struct eqc_pll { unsigned int index; @@ -167,29 +167,29 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, un= signed long *mult, { u32 spread; =20 - if (r0 & PCSR0_BYPASS) { + if (r0 & FRACG_PCSR0_BYPASS) { *mult =3D 1; *div =3D 1; *acc =3D 0; return 0; } =20 - if (!(r0 & PCSR0_PLL_LOCKED)) + if (!(r0 & FRACG_PCSR0_PLL_LOCKED)) return -EINVAL; =20 - *mult =3D FIELD_GET(PCSR0_INTIN, r0); - *div =3D FIELD_GET(PCSR0_REF_DIV, r0); + *mult =3D FIELD_GET(FRACG_PCSR0_INTIN, r0); + *div =3D FIELD_GET(FRACG_PCSR0_REF_DIV, r0); =20 /* Fractional mode, in 2^20 (0x100000) parts. */ - if (r0 & PCSR0_DSM_EN) { + if (r0 & FRACG_PCSR0_DSM_EN) { *div *=3D (1ULL << 20); - *mult =3D *mult * (1ULL << 20) + FIELD_GET(PCSR1_FRAC_IN, r1); + *mult =3D *mult * (1ULL << 20) + FIELD_GET(FRACG_PCSR1_FRAC_IN, r1); } =20 if (!*mult || !*div) return -EINVAL; =20 - if (r1 & (PCSR1_RESET | PCSR1_DIS_SSCG)) { + if (r1 & (FRACG_PCSR1_RESET | FRACG_PCSR1_DIS_SSCG)) { *acc =3D 0; return 0; } @@ -204,10 +204,10 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, un= signed long *mult, * with acc in parts per billion and, * spread in parts per thousand. */ - spread =3D FIELD_GET(PCSR1_SPREAD, r1); + spread =3D FIELD_GET(FRACG_PCSR1_SPREAD, r1); *acc =3D spread * 500000; =20 - if (r1 & PCSR1_DOWN_SPREAD) { + if (r1 & FRACG_PCSR1_DOWN_SPREAD) { /* * Downspreading: the central frequency is half a * spread lower. --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D4B7302770; Wed, 3 Sep 2025 12:48:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903687; cv=none; b=MWyEyzSpIgV9rUnz2+DfR5KOhbb1z/bXaKAeJ883TCwzyGQLf/S2G/JeBNHHCei/AFxS2NQWY+86XvOdjOOrqimoqhSTsDoQP6jF7Cg4nvSrQbFWhslhGMva3l02Mw7VCSudMKrPZLg4UvSjGGJw+1Lchlw3nUALdM6X06Fbetc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903687; c=relaxed/simple; bh=EPqmwwZ0f90bOzU8V5eQYfHIX7JI0YJEm0PuKVv+4Pw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J/jQeqUq+ozOqU2FBrjzbaWriK1HOvyvW5xKlOaJL9S6Jhmpiuj9DKaCmLsluwwhQ72QYV34ldeUGP5kPV4yqOuil8qsmnbs0ps/JpKC0dSMgEmwppm9lTVUxZ/BnfuLg1omUNgSwtq++XAebIuIiR+CyWx/SEnT1qSekZBxW8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=N2H2I/zY; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="N2H2I/zY" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 835421A08CE; Wed, 3 Sep 2025 12:48:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5BF2E606C3; Wed, 3 Sep 2025 12:48:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A17131C22DDD0; Wed, 3 Sep 2025 14:48:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903682; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=DJ1DuDyv3KQPQ4Ddd0dIiiyvMJY53s+wrB6U+LwgtA0=; b=N2H2I/zY0L63M0PS1CHma/SUEbnQBdKalT5Xw4uZ/8DnzisuylKoi9gOsKNRvzHQWKY2eV CKjHzHvxDZaBQGVYs6/U9l37n57gVW5Jk/RAhlneqrPt3MqAt4RowKsYxpzSPfuiq6gUPm iKp9KBpE8f4JuUZVJ6wn3IsgoZitYYAUD3NnkBpT4kKofn5wB2/ELKGaWynEWcZS9Z2x23 q64bdsR9Ao8ztNK7k0ZZe6teZvX/XaOEqKN0eMLvUlJHqQJHsoUAyDAHV+3V8Qrt6hBNWI E9Ks6dWzmEuFKsyplISPhHLD4xKK+u1th0w5l3gmonF8zAln9/xDOKKs4wat/g== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:21 +0200 Subject: [PATCH 14/19] clk: eyeq: rename the reg64 field of eqc_pll Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-14-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Not all PLL types need a 64 bits access, make the field name more generic by renaming it to reg. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 64 +++++++++++++++++++++++++---------------------= ---- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 63093a3099261e6798a6752651d25efa1b3e7592..0379fe7593453e72dd8983c7435= 61caa385a3fbd 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -73,7 +73,7 @@ struct eqc_pll { unsigned int index; const char *name; - unsigned int reg64; + unsigned int reg; }; =20 /* @@ -239,7 +239,7 @@ static void eqc_probe_init_plls(struct device *dev, con= st struct eqc_match_data for (i =3D 0; i < data->pll_count; i++) { pll =3D &data->plls[i]; =20 - val =3D readq(base + pll->reg64); + val =3D readq(base + pll->reg); r0 =3D val; r1 =3D val >> 32; =20 @@ -422,19 +422,19 @@ static int eqc_probe(struct platform_device *pdev) =20 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */ static const struct eqc_pll eqc_eyeq5_early_plls[] =3D { - { .index =3D EQ5C_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x02C }, - { .index =3D EQ5C_PLL_PER, .name =3D "pll-per", .reg64 =3D 0x05C }, + { .index =3D EQ5C_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C }, + { .index =3D EQ5C_PLL_PER, .name =3D "pll-per", .reg =3D 0x05C }, }; =20 static const struct eqc_pll eqc_eyeq5_plls[] =3D { - { .index =3D EQ5C_PLL_VMP, .name =3D "pll-vmp", .reg64 =3D 0x034 }, - { .index =3D EQ5C_PLL_PMA, .name =3D "pll-pma", .reg64 =3D 0x03C }, - { .index =3D EQ5C_PLL_VDI, .name =3D "pll-vdi", .reg64 =3D 0x044 }, - { .index =3D EQ5C_PLL_DDR0, .name =3D "pll-ddr0", .reg64 =3D 0x04C }, - { .index =3D EQ5C_PLL_PCI, .name =3D "pll-pci", .reg64 =3D 0x054 }, - { .index =3D EQ5C_PLL_PMAC, .name =3D "pll-pmac", .reg64 =3D 0x064 }, - { .index =3D EQ5C_PLL_MPC, .name =3D "pll-mpc", .reg64 =3D 0x06C }, - { .index =3D EQ5C_PLL_DDR1, .name =3D "pll-ddr1", .reg64 =3D 0x074 }, + { .index =3D EQ5C_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x034 }, + { .index =3D EQ5C_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x03C }, + { .index =3D EQ5C_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044 }, + { .index =3D EQ5C_PLL_DDR0, .name =3D "pll-ddr0", .reg =3D 0x04C }, + { .index =3D EQ5C_PLL_PCI, .name =3D "pll-pci", .reg =3D 0x054 }, + { .index =3D EQ5C_PLL_PMAC, .name =3D "pll-pmac", .reg =3D 0x064 }, + { .index =3D EQ5C_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x06C }, + { .index =3D EQ5C_PLL_DDR1, .name =3D "pll-ddr1", .reg =3D 0x074 }, }; =20 enum { @@ -562,10 +562,10 @@ static const struct eqc_match_data eqc_eyeq5_match_da= ta =3D { }; =20 static const struct eqc_pll eqc_eyeq6l_plls[] =3D { - { .index =3D EQ6LC_PLL_DDR, .name =3D "pll-ddr", .reg64 =3D 0x02C }, - { .index =3D EQ6LC_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x034 }, /* a= lso acc */ - { .index =3D EQ6LC_PLL_PER, .name =3D "pll-per", .reg64 =3D 0x03C }, - { .index =3D EQ6LC_PLL_VDI, .name =3D "pll-vdi", .reg64 =3D 0x044 }, + { .index =3D EQ6LC_PLL_DDR, .name =3D "pll-ddr", .reg =3D 0x02C }, + { .index =3D EQ6LC_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x034 }, /* als= o acc */ + { .index =3D EQ6LC_PLL_PER, .name =3D "pll-per", .reg =3D 0x03C }, + { .index =3D EQ6LC_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044 }, }; =20 static const struct eqc_match_data eqc_eyeq6l_match_data =3D { @@ -580,7 +580,7 @@ static const struct eqc_match_data eqc_eyeq6h_west_matc= h_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_east_plls[] =3D { - { .index =3D 0, .name =3D "pll-east", .reg64 =3D 0x074 }, + { .index =3D 0, .name =3D "pll-east", .reg =3D 0x074 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_east_match_data =3D { @@ -591,10 +591,10 @@ static const struct eqc_match_data eqc_eyeq6h_east_ma= tch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_south_plls[] =3D { - { .index =3D EQ6HC_SOUTH_PLL_VDI, .name =3D "pll-vdi", .reg64 =3D 0x000= }, - { .index =3D EQ6HC_SOUTH_PLL_PCIE, .name =3D "pll-pcie", .reg64 =3D 0x008= }, - { .index =3D EQ6HC_SOUTH_PLL_PER, .name =3D "pll-per", .reg64 =3D 0x010= }, - { .index =3D EQ6HC_SOUTH_PLL_ISP, .name =3D "pll-isp", .reg64 =3D 0x018= }, + { .index =3D EQ6HC_SOUTH_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x000 }, + { .index =3D EQ6HC_SOUTH_PLL_PCIE, .name =3D "pll-pcie", .reg =3D 0x008 }, + { .index =3D EQ6HC_SOUTH_PLL_PER, .name =3D "pll-per", .reg =3D 0x010 }, + { .index =3D EQ6HC_SOUTH_PLL_ISP, .name =3D "pll-isp", .reg =3D 0x018 }, }; =20 static const struct eqc_div eqc_eyeq6h_south_divs[] =3D { @@ -641,7 +641,7 @@ static const struct eqc_match_data eqc_eyeq6h_south_mat= ch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] =3D { - { .index =3D 0, .name =3D "pll-ddr0", .reg64 =3D 0x074 }, + { .index =3D 0, .name =3D "pll-ddr0", .reg =3D 0x074 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data =3D { @@ -650,7 +650,7 @@ static const struct eqc_match_data eqc_eyeq6h_ddr0_matc= h_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] =3D { - { .index =3D 0, .name =3D "pll-ddr1", .reg64 =3D 0x074 }, + { .index =3D 0, .name =3D "pll-ddr1", .reg =3D 0x074 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data =3D { @@ -659,11 +659,11 @@ static const struct eqc_match_data eqc_eyeq6h_ddr1_ma= tch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_acc_plls[] =3D { - { .index =3D EQ6HC_ACC_PLL_XNN, .name =3D "pll-xnn", .reg64 =3D 0x040 }, - { .index =3D EQ6HC_ACC_PLL_VMP, .name =3D "pll-vmp", .reg64 =3D 0x050 }, - { .index =3D EQ6HC_ACC_PLL_PMA, .name =3D "pll-pma", .reg64 =3D 0x05C }, - { .index =3D EQ6HC_ACC_PLL_MPC, .name =3D "pll-mpc", .reg64 =3D 0x068 }, - { .index =3D EQ6HC_ACC_PLL_NOC, .name =3D "pll-noc", .reg64 =3D 0x070 }, + { .index =3D EQ6HC_ACC_PLL_XNN, .name =3D "pll-xnn", .reg =3D 0x040 }, + { .index =3D EQ6HC_ACC_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x050 }, + { .index =3D EQ6HC_ACC_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x05C }, + { .index =3D EQ6HC_ACC_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x068 }, + { .index =3D EQ6HC_ACC_PLL_NOC, .name =3D "pll-noc", .reg =3D 0x070 }, }; =20 static const struct eqc_match_data eqc_eyeq6h_acc_match_data =3D { @@ -697,7 +697,7 @@ builtin_platform_driver(eqc_driver); =20 /* Required early for GIC timer. */ static const struct eqc_pll eqc_eyeq6h_central_early_plls[] =3D { - { .index =3D EQ6HC_CENTRAL_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x02C= }, + { .index =3D EQ6HC_CENTRAL_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C }, }; =20 static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factor= s[] =3D { @@ -714,7 +714,7 @@ static const struct eqc_early_match_data eqc_eyeq6h_cen= tral_early_match_data __i =20 /* Required early for UART. */ static const struct eqc_pll eqc_eyeq6h_west_early_plls[] =3D { - { .index =3D EQ6HC_WEST_PLL_PER, .name =3D "pll-west", .reg64 =3D 0x074 }, + { .index =3D EQ6HC_WEST_PLL_PER, .name =3D "pll-west", .reg =3D 0x074 }, }; =20 static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[]= =3D { @@ -758,7 +758,7 @@ static void __init eqc_early_init(struct device_node *n= p, for (i =3D 0; i < clk_count; i++) cells->hws[i] =3D ERR_PTR(-EPROBE_DEFER); =20 - /* Offsets (reg64) of early PLLs are relative to OLB block. */ + /* Offsets (reg) of early PLLs are relative to OLB block. */ base =3D of_iomap(np, 0); if (!base) { ret =3D -ENODEV; @@ -772,7 +772,7 @@ static void __init eqc_early_init(struct device_node *n= p, u32 r0, r1; u64 val; =20 - val =3D readq(base + pll->reg64); + val =3D readq(base + pll->reg); r0 =3D val; r1 =3D val >> 32; =20 --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B16933093CE for ; Wed, 3 Sep 2025 12:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903690; cv=none; b=MqB6cdUFfSysoaBMbUwOHYIMf9FnJ6Dff7C4KN6aYNOvwPP0kqXqdZ/D40teG8fG4x+cka9qQQLHh+eQfgWMKAYXUIsPdUy3HSKz4eMjj5qN1fZwxDMJ+MT5obBfyW02oMS0WHnr1f5yxn1djQLOvPKLaQ6JuzhuhdZC+TwHI0E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903690; c=relaxed/simple; bh=ibQJG3yzlt3LNvhxoq6oseOsLckktboWe/oUHYYLRC4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gWPNU2OG12jgQiMI9oNrwfsn5UCrFdRrf6LgWjaMamydyGFdKhUmXYN62WLiPr2f2+xNmt0u+WYZn93ekOr6ZpEx1cfCIiyASfWBMt+aaBx75SkE1+FDORw8YQ7d7IFVu1CwWbFzXj16efcs4Dkwdp4sKp1c86iloZWKmmCXXvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=n9RWs/Gw; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="n9RWs/Gw" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 49F831A08EC; Wed, 3 Sep 2025 12:48:06 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 21230606C3; Wed, 3 Sep 2025 12:48:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 872C51C22DE01; Wed, 3 Sep 2025 14:48:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903684; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=dpAK/zu2XKNS6eGJFjWeRaO0v0/Xw6/7WiQfH/TyBKE=; b=n9RWs/Gw3UqUf9CzzaUIPw9BtWQXHpRb/KcL+6kma7/nl5pqldrhECAmqnjb4rvkGimvep exeKImtlfteD7cmtuMWOkuCzH7UFVxtWx77aVnu1rQU+CJ4f6oJjtPA/USXgSrJvEcHMFN wGm3wA4a2fMBNIHcR8dbehHaWuLNJIy8TrVoDKcCDjrz/rVGKzIBKc1/0KaWZ8RokZ0U0E ldDmWIz7b75JqSwlKDBO7EPL0l6lU3X72tdgRX7fYFPjrxyK30ARML5OqkaXJJGiCMFHKB T/1siUjymnRX3UFpDTT9wKm66oS+wd6Ow1NjGp3DU0pNerYXUWJjeYVxYD9vOg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:22 +0200 Subject: [PATCH 15/19] clk: eyeq: add a type for the PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-15-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add a type field to the eqc_pll structure and parse the registers of the PLL depending on its type. This makes room for adding new PLL types found in the eyeQ7H OLB. Each PLL type now comes with its own registers parsing function that is called based on the type. For now, only the FRACG type is implemented. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 104 +++++++++++++++++++++++++++------------------= ---- 1 file changed, 57 insertions(+), 47 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 0379fe7593453e72dd8983c743561caa385a3fbd..07a205fefd93eed8f9c2c6b88fb= f5b8b6a39a92c 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -70,10 +70,15 @@ #define FRACG_PCSR1_DOWN_SPREAD BIT(11) #define FRACG_PCSR1_FRAC_IN GENMASK(31, 12) =20 +enum eqc_pll_type { + EQC_PLL_FRACG, +}; + struct eqc_pll { - unsigned int index; - const char *name; - unsigned int reg; + unsigned int index; + const char *name; + unsigned int reg; + enum eqc_pll_type type; }; =20 /* @@ -162,11 +167,17 @@ static void eqc_pll_downshift_factors(unsigned long *= mult, unsigned long *div) *div >>=3D shift; } =20 -static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, - unsigned long *div, unsigned long *acc) +static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult, + unsigned long *div, unsigned long *acc) { + u64 val; + u32 r0, r1; u32 spread; =20 + val =3D readq(base); + r0 =3D val; + r1 =3D val >> 32; + if (r0 & FRACG_PCSR0_BYPASS) { *mult =3D 1; *div =3D 1; @@ -225,6 +236,16 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, uns= igned long *mult, return 0; } =20 +static int eqc_parse_one_pll(void __iomem *base, enum eqc_pll_type type, u= nsigned long *mult, + unsigned long *div, unsigned long *acc) +{ + switch (type) { + case EQC_PLL_FRACG: + return eqc_pll_parse_fracg(base, mult, div, acc); + } + return -EINVAL; +} + static void eqc_probe_init_plls(struct device *dev, const struct eqc_match= _data *data, void __iomem *base, struct clk_hw_onecell_data *cells) { @@ -232,18 +253,12 @@ static void eqc_probe_init_plls(struct device *dev, c= onst struct eqc_match_data const struct eqc_pll *pll; struct clk_hw *hw; unsigned int i; - u32 r0, r1; - u64 val; int ret; =20 for (i =3D 0; i < data->pll_count; i++) { pll =3D &data->plls[i]; =20 - val =3D readq(base + pll->reg); - r0 =3D val; - r1 =3D val >> 32; - - ret =3D eqc_pll_parse_registers(r0, r1, &mult, &div, &acc); + ret =3D eqc_parse_one_pll(base + pll->reg, pll->type, &mult, &div, &acc); if (ret) { dev_warn(dev, "failed parsing state of %s\n", pll->name); cells->hws[pll->index] =3D ERR_PTR(ret); @@ -422,19 +437,19 @@ static int eqc_probe(struct platform_device *pdev) =20 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */ static const struct eqc_pll eqc_eyeq5_early_plls[] =3D { - { .index =3D EQ5C_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C }, - { .index =3D EQ5C_PLL_PER, .name =3D "pll-per", .reg =3D 0x05C }, + { .index =3D EQ5C_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_PER, .name =3D "pll-per", .reg =3D 0x05C, .type = =3D EQC_PLL_FRACG }, }; =20 static const struct eqc_pll eqc_eyeq5_plls[] =3D { - { .index =3D EQ5C_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x034 }, - { .index =3D EQ5C_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x03C }, - { .index =3D EQ5C_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044 }, - { .index =3D EQ5C_PLL_DDR0, .name =3D "pll-ddr0", .reg =3D 0x04C }, - { .index =3D EQ5C_PLL_PCI, .name =3D "pll-pci", .reg =3D 0x054 }, - { .index =3D EQ5C_PLL_PMAC, .name =3D "pll-pmac", .reg =3D 0x064 }, - { .index =3D EQ5C_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x06C }, - { .index =3D EQ5C_PLL_DDR1, .name =3D "pll-ddr1", .reg =3D 0x074 }, + { .index =3D EQ5C_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x034, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x03C, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_DDR0, .name =3D "pll-ddr0", .reg =3D 0x04C, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_PCI, .name =3D "pll-pci", .reg =3D 0x054, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_PMAC, .name =3D "pll-pmac", .reg =3D 0x064, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x06C, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ5C_PLL_DDR1, .name =3D "pll-ddr1", .reg =3D 0x074, .type = =3D EQC_PLL_FRACG }, }; =20 enum { @@ -562,10 +577,11 @@ static const struct eqc_match_data eqc_eyeq5_match_da= ta =3D { }; =20 static const struct eqc_pll eqc_eyeq6l_plls[] =3D { - { .index =3D EQ6LC_PLL_DDR, .name =3D "pll-ddr", .reg =3D 0x02C }, - { .index =3D EQ6LC_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x034 }, /* als= o acc */ - { .index =3D EQ6LC_PLL_PER, .name =3D "pll-per", .reg =3D 0x03C }, - { .index =3D EQ6LC_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044 }, + { .index =3D EQ6LC_PLL_DDR, .name =3D "pll-ddr", .reg =3D 0x02C, .type = =3D EQC_PLL_FRACG }, + /* pll-cpu also for acc */ + { .index =3D EQ6LC_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x034, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ6LC_PLL_PER, .name =3D "pll-per", .reg =3D 0x03C, .type = =3D EQC_PLL_FRACG }, + { .index =3D EQ6LC_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x044, .type = =3D EQC_PLL_FRACG }, }; =20 static const struct eqc_match_data eqc_eyeq6l_match_data =3D { @@ -580,7 +596,7 @@ static const struct eqc_match_data eqc_eyeq6h_west_matc= h_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_east_plls[] =3D { - { .index =3D 0, .name =3D "pll-east", .reg =3D 0x074 }, + { .index =3D 0, .name =3D "pll-east", .reg =3D 0x074, .type =3D EQC_PLL_F= RACG }, }; =20 static const struct eqc_match_data eqc_eyeq6h_east_match_data =3D { @@ -591,10 +607,10 @@ static const struct eqc_match_data eqc_eyeq6h_east_ma= tch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_south_plls[] =3D { - { .index =3D EQ6HC_SOUTH_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x000 }, - { .index =3D EQ6HC_SOUTH_PLL_PCIE, .name =3D "pll-pcie", .reg =3D 0x008 }, - { .index =3D EQ6HC_SOUTH_PLL_PER, .name =3D "pll-per", .reg =3D 0x010 }, - { .index =3D EQ6HC_SOUTH_PLL_ISP, .name =3D "pll-isp", .reg =3D 0x018 }, + { .index =3D EQ6HC_SOUTH_PLL_VDI, .name =3D "pll-vdi", .reg =3D 0x000, = .type =3D EQC_PLL_FRACG }, + { .index =3D EQ6HC_SOUTH_PLL_PCIE, .name =3D "pll-pcie", .reg =3D 0x008, = .type =3D EQC_PLL_FRACG }, + { .index =3D EQ6HC_SOUTH_PLL_PER, .name =3D "pll-per", .reg =3D 0x010, = .type =3D EQC_PLL_FRACG }, + { .index =3D EQ6HC_SOUTH_PLL_ISP, .name =3D "pll-isp", .reg =3D 0x018, = .type =3D EQC_PLL_FRACG }, }; =20 static const struct eqc_div eqc_eyeq6h_south_divs[] =3D { @@ -641,7 +657,7 @@ static const struct eqc_match_data eqc_eyeq6h_south_mat= ch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] =3D { - { .index =3D 0, .name =3D "pll-ddr0", .reg =3D 0x074 }, + { .index =3D 0, .name =3D "pll-ddr0", .reg =3D 0x074, .type =3D EQC_PLL_F= RACG }, }; =20 static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data =3D { @@ -650,7 +666,7 @@ static const struct eqc_match_data eqc_eyeq6h_ddr0_matc= h_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] =3D { - { .index =3D 0, .name =3D "pll-ddr1", .reg =3D 0x074 }, + { .index =3D 0, .name =3D "pll-ddr1", .reg =3D 0x074, .type =3D EQC_PLL_F= RACG }, }; =20 static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data =3D { @@ -659,11 +675,11 @@ static const struct eqc_match_data eqc_eyeq6h_ddr1_ma= tch_data =3D { }; =20 static const struct eqc_pll eqc_eyeq6h_acc_plls[] =3D { - { .index =3D EQ6HC_ACC_PLL_XNN, .name =3D "pll-xnn", .reg =3D 0x040 }, - { .index =3D EQ6HC_ACC_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x050 }, - { .index =3D EQ6HC_ACC_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x05C }, - { .index =3D EQ6HC_ACC_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x068 }, - { .index =3D EQ6HC_ACC_PLL_NOC, .name =3D "pll-noc", .reg =3D 0x070 }, + { .index =3D EQ6HC_ACC_PLL_XNN, .name =3D "pll-xnn", .reg =3D 0x040, .typ= e =3D EQC_PLL_FRACG }, + { .index =3D EQ6HC_ACC_PLL_VMP, .name =3D "pll-vmp", .reg =3D 0x050, .typ= e =3D EQC_PLL_FRACG }, + { .index =3D EQ6HC_ACC_PLL_PMA, .name =3D "pll-pma", .reg =3D 0x05C, .typ= e =3D EQC_PLL_FRACG }, + { .index =3D EQ6HC_ACC_PLL_MPC, .name =3D "pll-mpc", .reg =3D 0x068, .typ= e =3D EQC_PLL_FRACG }, + { .index =3D EQ6HC_ACC_PLL_NOC, .name =3D "pll-noc", .reg =3D 0x070, .typ= e =3D EQC_PLL_FRACG }, }; =20 static const struct eqc_match_data eqc_eyeq6h_acc_match_data =3D { @@ -697,7 +713,7 @@ builtin_platform_driver(eqc_driver); =20 /* Required early for GIC timer. */ static const struct eqc_pll eqc_eyeq6h_central_early_plls[] =3D { - { .index =3D EQ6HC_CENTRAL_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C }, + { .index =3D EQ6HC_CENTRAL_PLL_CPU, .name =3D "pll-cpu", .reg =3D 0x02C, = .type =3D EQC_PLL_FRACG }, }; =20 static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factor= s[] =3D { @@ -714,7 +730,7 @@ static const struct eqc_early_match_data eqc_eyeq6h_cen= tral_early_match_data __i =20 /* Required early for UART. */ static const struct eqc_pll eqc_eyeq6h_west_early_plls[] =3D { - { .index =3D EQ6HC_WEST_PLL_PER, .name =3D "pll-west", .reg =3D 0x074 }, + { .index =3D EQ6HC_WEST_PLL_PER, .name =3D "pll-west", .reg =3D 0x074, .t= ype =3D EQC_PLL_FRACG }, }; =20 static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[]= =3D { @@ -769,14 +785,8 @@ static void __init eqc_early_init(struct device_node *= np, const struct eqc_pll *pll =3D &early_data->early_plls[i]; unsigned long mult, div, acc; struct clk_hw *hw; - u32 r0, r1; - u64 val; =20 - val =3D readq(base + pll->reg); - r0 =3D val; - r1 =3D val >> 32; - - ret =3D eqc_pll_parse_registers(r0, r1, &mult, &div, &acc); + ret =3D eqc_parse_one_pll(base + pll->reg, pll->type, &mult, &div, &acc); if (ret) { pr_err("failed parsing state of %s\n", pll->name); goto err; --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DA95309DDF; Wed, 3 Sep 2025 12:48:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903691; cv=none; b=ZYsKaU83XbQDTpMh4TgGfKQ7WPkqQd+xs2OyeAifCtkfwj0mw1dBD0y5DqIPMzdoqKlXW3WDcp1w/wJwfb+w3PzyN7ZawAkKfY/ot1aUfnJ5sETN1ythq2izyVfyFhJSe7nBXKEZp/CHP5J8pZxTykh0N8TttDmY2oGgJRGdEsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903691; c=relaxed/simple; bh=W4Ta+ycjb4QCLgW02FiMWVfiz5MCgzdDYWA7YCly94w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PF0DdVJPwsgH9rd1mJULpSwfVuTRcKtegvlVd3DnTa0GtOH61S0Bcd/Ci6rj3tua4uPIsKjIkT7N0BQyXhOy+empOu9X4BEq6K70p7wUSoR/j4Vh+XsyjRHSkjSVuu0hmhy3+buBBa/mdOMO76QvI1ynRi5i7GaIKgPqCMeuAgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=oEn+P8eU; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="oEn+P8eU" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 458FF4E40C0A; Wed, 3 Sep 2025 12:48:08 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1E6ED606C3; Wed, 3 Sep 2025 12:48:08 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 031EA1C22C3F8; Wed, 3 Sep 2025 14:48:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903686; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=0wxZt/suAs12evWL3lnT9+Z1yeWU0cypzlWRzlgafgY=; b=oEn+P8eUGsBESsg/56v4rbCZsIviEdBIhoCdgmr/qkSZR8gDDQZvm6aGdAc0GG7pGB2Pjt +Rddl84zplPWl4wzW6JGryHtbreCd71fc1GVQhuyvem0I0BjCjkBML9JogBIfJQbRsMm9j 9L8w3ukRyRFzaatPkECaheWuRWzY1H75jHCaIoTVyJ5fp41cnGlEbpNWZPxo/Jqzzr7oNU uMYjjOMMopj9P4Yu9d0cdjs+RrSrw3HO54dvtxriRZLm5QwsdwuvGYQaq9NX+kSTRTdhFe tudDhOIA1uqO90sE7l1CFJKu5NvIXlu7AP9ctpPOyXO0nOavH39ZXRG2C58v/A== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:23 +0200 Subject: [PATCH 16/19] clk: eyeq: add two PLL types Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-16-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add the handling of the two types of PLL found in the eyeQ7H OLB. The JFRACR PLL have similar properties as the FRACG PLL, but its configuration is spread on three registers instead of two. The AINTP PLL does not support spread spectrum and uses a single register. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 117 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 117 insertions(+) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 07a205fefd93eed8f9c2c6b88fbf5b8b6a39a92c..cf745671d86a5fc770ec3599561= eb3468e13bd58 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -70,8 +70,44 @@ #define FRACG_PCSR1_DOWN_SPREAD BIT(11) #define FRACG_PCSR1_FRAC_IN GENMASK(31, 12) =20 +#define JFRACR_PCSR0_BYPASS BIT(0) +#define JFRACR_PCSR0_PLL_EN BIT(1) +#define JFRACR_PCSR0_FOUTVCO_EN BIT(2) +#define JFRACR_PCSR0_FOUTPOSTDIV_EN BIT(3) +#define JFRACR_PCSR0_POST_DIV1 GENMASK(6, 4) +#define JFRACR_PCSR0_POST_DIV2 GENMASK(9, 7) +#define JFRACR_PCSR0_REF_DIV GENMASK(15, 10) +#define JFRACR_PCSR0_FB_DIV GENMASK(27, 16) +#define JFRACR_PCSR0_VCO_SEL GENMASK(29, 28) +#define JFRACR_PCSR0_PLL_LOCKED GENMASK(31, 30) + +#define JFRACR_PCSR1_FRAC_IN GENMASK(23, 0) +#define JFRACR_PCSR1_FOUT4PHASE_EN BIT(24) +#define JFRACR_PCSR1_DAC_EN BIT(25) +#define JFRACR_PCSR1_DSM_EN BIT(26) +/* Bits 31..27 are reserved */ +#define JFRACR_PCSR2_RESET BIT(0) +#define JFRACR_PCSR2_DIS_SSCG BIT(1) +#define JFRACR_PCSR2_DOWN_SPREAD BIT(2) +#define JFRACR_PCSR2_SSGC_DIV GENMASK(7, 4) +#define JFRACR_PCSR2_SPREAD GENMASK(12, 8) +/* Bits 31..13 are reserved */ + +#define AINTP_PCSR_BYPASS BIT(0) +#define AINTP_PCSR_PLL_EN BIT(1) +#define AINTP_PCSR_FOUTVCO_EN BIT(2) +#define AINTP_PCSR_FOUTPOSTDIV_EN BIT(3) +#define AINTP_PCSR_POST_DIV1 GENMASK(6, 4) +#define AINTP_PCSR_POST_DIV2 GENMASK(9, 7) +#define AINTP_PCSR_REF_DIV GENMASK(15, 10) +#define AINTP_PCSR_FB_DIV GENMASK(27, 16) +#define AINTP_PCSR_VCO_SEL GENMASK(29, 28) +#define AINTP_PCSR_PLL_LOCKED GENMASK(31, 30) + enum eqc_pll_type { EQC_PLL_FRACG, + EQC_PLL_JFRACR, + EQC_PLL_AINTP, }; =20 struct eqc_pll { @@ -236,12 +272,93 @@ static int eqc_pll_parse_fracg(void __iomem *base, un= signed long *mult, return 0; } =20 +static int eqc_pll_parse_jfracr(void __iomem *base, unsigned long *mult, + unsigned long *div, unsigned long *acc) +{ + u64 val; + u32 r0, r1, r2; + u32 spread; + + val =3D readq(base); + r0 =3D val; + r1 =3D val >> 32; + r2 =3D readl(base + 8); + + if (r0 & JFRACR_PCSR0_BYPASS) { + *mult =3D 1; + *div =3D 1; + *acc =3D 0; + return 0; + } + + if (!(r0 & JFRACR_PCSR0_PLL_LOCKED)) + return -EINVAL; + + *mult =3D FIELD_GET(JFRACR_PCSR0_FB_DIV, r0); + *div =3D FIELD_GET(JFRACR_PCSR0_REF_DIV, r0); + + if (r1 & JFRACR_PCSR1_DSM_EN) { + *div *=3D (1ULL << 20); + *mult =3D *mult * (1ULL << 20) + FIELD_GET(JFRACR_PCSR1_FRAC_IN, r1); + } + + if (!*mult || !*div) + return -EINVAL; + + if (r2 & (JFRACR_PCSR2_RESET | JFRACR_PCSR2_DIS_SSCG)) { + *acc =3D 0; + return 0; + } + + spread =3D FIELD_GET(JFRACR_PCSR2_SPREAD, r2); + *acc =3D spread * 500000; + + if (r2 & JFRACR_PCSR2_DOWN_SPREAD) { + *mult *=3D 2000 - spread; + *div *=3D 2000; + eqc_pll_downshift_factors(mult, div); + } + + return 0; +} + +static int eqc_pll_parse_aintp(void __iomem *base, unsigned long *mult, + unsigned long *div, unsigned long *acc) +{ + u32 r0; + + /* no spread spectrum */ + *acc =3D 0; + + r0 =3D readl(base); + if (r0 & AINTP_PCSR_BYPASS) { + *mult =3D 1; + *div =3D 1; + return 0; + } + + if (!(r0 & AINTP_PCSR_PLL_LOCKED)) + return -EINVAL; + + *mult =3D FIELD_GET(AINTP_PCSR_FB_DIV, r0); + *div =3D FIELD_GET(AINTP_PCSR_REF_DIV, r0); + + if (!*mult || !*div) + return -EINVAL; + + return 0; +} + static int eqc_parse_one_pll(void __iomem *base, enum eqc_pll_type type, u= nsigned long *mult, unsigned long *div, unsigned long *acc) { switch (type) { case EQC_PLL_FRACG: return eqc_pll_parse_fracg(base, mult, div, acc); + case EQC_PLL_JFRACR: + return eqc_pll_parse_jfracr(base, mult, div, acc); + case EQC_PLL_AINTP: + return eqc_pll_parse_aintp(base, mult, div, acc); } return -EINVAL; } --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85A8D30AAC0; Wed, 3 Sep 2025 12:48:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903693; cv=none; b=SfIO3TWFsTahIMeaZ4WZhzyipted9Vta5+Y4qM3SwXKFglcnW1C9omiFkERLd/FnnbqWsJZmgbLr/pov4NttcH9XPNuoJm2neavXhJpMOkUXEnijRRoRR5kOeZPKKgSN5P3mwAd9tE/Afx9Mb+3R3dQg5B5TeapPzBsoqjgXKk4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903693; c=relaxed/simple; bh=4bNNkHVC2aJNVXLs/K85UFMmabtxOabApbEO1pdUgyQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rkLAFwAjHnjN8Y1fFl0yvF6VVR5vVosPiASQrswloSZZZitUxZn0LBnpRfBY+FS3GaG/6vsqhbcs66xq1rHE/gEZcx3faCBk7pJdCrFpnhxjTR50FZosgIR/q596uWP3kQ4PW8lXT9drLbV2WCJPJ7GqZa6G1KihsgWV35jZq10= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=1AqA+bm6; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="1AqA+bm6" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 052E31A08CE; Wed, 3 Sep 2025 12:48:10 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id D2335606C3; Wed, 3 Sep 2025 12:48:09 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 318081C22A4EA; Wed, 3 Sep 2025 14:48:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903688; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=OAZYQK1WvsUmQL4WZLsOwmlchJWna6XIMMIb+V5JjQ8=; b=1AqA+bm6fjtkmWg6FVcdHY6BVRtDDm2azATuHi2QE4Ad76X4ABZ4JIi4eiNtIfvLEuX4bZ i5imFE2FAJMyeUR6nAm8VK3ckz3Opg7HtjHv+CLTTMcykWNvLCi6Xso/1Z42BLDG2E3bFJ mNK0OcS9Wc9OXZZyz5LVorDC3I9MkSUgbCLmFng2SwZFEZ+OQSz9/zz82r4sXWPq2L8sOJ wd8UscwQ1Rm+yiop55x+GdzhSjHnjDhdsLHYGeCq/U3k3xA8/Lsze56rUf+9iVoJ9D3y09 M6V11Vm3zj2FEETL2zVjrTbdfRgmmb5bgk7wA9ugJfxwua0s1aZLFbHG1dmpbg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:24 +0200 Subject: [PATCH 17/19] clk: eyeq: add a parent field to the pll Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-17-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Allow setting the parent of a pll. If NULL, use the same "ref" clock as before. If non-NULL, the name is looked up in the "clock-names" passed in the device tree and if found it is used as the fw_name, similar to how "ref" was used previously. If not found, the name is used as the parent_name when registering the clock with clk_hw_register_fixed_factor_with_accuracy. This last case is used to refer to a clock registered in early init and used by the same OLB during probe while avoiding a dependency cycle. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index cf745671d86a5fc770ec3599561eb3468e13bd58..a6260c38393776afab60e994c99= 008cfeecf6bc3 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -115,6 +115,7 @@ struct eqc_pll { const char *name; unsigned int reg; enum eqc_pll_type type; + const char *parent_name; }; =20 /* @@ -366,8 +367,10 @@ static int eqc_parse_one_pll(void __iomem *base, enum = eqc_pll_type type, unsigne static void eqc_probe_init_plls(struct device *dev, const struct eqc_match= _data *data, void __iomem *base, struct clk_hw_onecell_data *cells) { + struct device_node *np =3D dev->of_node; unsigned long mult, div, acc; const struct eqc_pll *pll; + const char *fw_name; struct clk_hw *hw; unsigned int i; int ret; @@ -382,8 +385,20 @@ static void eqc_probe_init_plls(struct device *dev, co= nst struct eqc_match_data continue; } =20 - hw =3D clk_hw_register_fixed_factor_with_accuracy_fwname(dev, - dev->of_node, pll->name, "ref", 0, mult, div, acc); + if (!pll->parent_name) + fw_name =3D "ref"; + else if (of_property_match_string(np, "clock-names", pll->parent_name) >= =3D 0) + fw_name =3D pll->parent_name; + else + fw_name =3D NULL; + + if (fw_name) + hw =3D clk_hw_register_fixed_factor_with_accuracy_fwname(dev, + np, pll->name, fw_name, 0, mult, div, acc); + else + hw =3D clk_hw_register_fixed_factor_with_accuracy(dev, + pll->name, pll->parent_name, 0, mult, div, acc); + cells->hws[pll->index] =3D hw; if (IS_ERR(hw)) dev_warn(dev, "failed registering %s: %pe\n", pll->name, hw); --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D8513009DE; Wed, 3 Sep 2025 12:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903695; cv=none; b=SiMMfxDeStYdAXELNU/NUBYfdeDIN5mP0P7MrAhWFYO9PwWLu6qT770pKRiAchNnNG/WiRErf1bQkIH4eCusvaCvFPkDEpjT7Bo4Xq35SJRczjO/jbVwlDAZBADwe9JosdeZ16WI9K8dmmOg2YXPScKgaQD1897SuvSYxg9Bl7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903695; c=relaxed/simple; bh=R0IpjP48mGbApyiDHDBOompW3i7L72XuTjLgRVkraEE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZFuEMu9Hr2tbuoR/wLEXzJp2JsnTbXO+e1uTvpcBkuzEsygIF4Ag4nvIwFG9RsGh2OlAcbeBrtMnJdZTb2ASv26f/YAlC5iNWpLyO/eIXzetDxPmas/3Q05lIxWkllCCaK0qOzhVFDZbPopbUuXEvi7bF4R+/QgK7IS+msRVqIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mXE9+74b; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mXE9+74b" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id F20AA4E40C09; Wed, 3 Sep 2025 12:48:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C5735606C3; Wed, 3 Sep 2025 12:48:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E9A0D1C22CF52; Wed, 3 Sep 2025 14:48:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903690; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ik7BcMqE7IJwAhNylRviJShBX6EjkWH4eM1xXqILmgs=; b=mXE9+74bgFgeFgGidMG2360hnt7QuME+h4vj0zDzRYIogZDDC/g0wKX/VyLYZ7DBviBbwi EAfQnsqF3epghJJTx21bcmvv8pC9MJbfy1qKcTyF7zucMZx5dbJAEIXmgfiwqW0N/j7gwG r1lOPDsMNUkC/hvRTOln45fKyCesongZf7mtd19XL/BdoDLitefj9K6VcF9AWg5YBmtCC6 U8ZeBQBHR9zeWmnXw7OuHNtkSBuwL6HSdkYIH/40QsT+ZMcvMZ5A3lfiPNP6eD/Bq2WjIn S/ztB04o11JxsiFR6PdGI6Xo1CT4sP3GazObaEoH8XwMvszO/4c0uRiUSR6pVw== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:25 +0200 Subject: [PATCH 18/19] clk: eyeq: add an optional clk_div_table to divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-18-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The new type of divider in eyeQ7H OLB are table-based, use it if present. Make sure we don't pass CLK_DIVIDER_EVEN_INTEGERS in the flags when registerting a table based divider as it has priority over the table. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index a6260c38393776afab60e994c99008cfeecf6bc3..8d5e194215e9d3d13b334a5ebf0= 04499050e84b9 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -119,17 +119,20 @@ struct eqc_pll { }; =20 /* - * Divider clock. Divider is 2*(v+1), with v the register value. + * Divider clock. + * If the table is NULL, divider is 2*(v+1), with v the register value. * Min divider is 2, max is 2*(2^width). + * Otherwise the divider values are looked up in the table. */ struct eqc_div { - unsigned int index; - const char *name; - unsigned int parent_idx; - const char *parent_name; - unsigned int reg; - u8 shift; - u8 width; + unsigned int index; + const char *name; + unsigned int parent_idx; + const char *parent_name; + unsigned int reg; + u8 shift; + u8 width; + const struct clk_div_table *table; }; =20 struct eqc_fixed_factor { @@ -433,7 +436,7 @@ static void eqc_probe_init_divs(struct device *dev, con= st struct eqc_match_data =20 hw =3D clk_hw_register_divider_table_parent_data(dev, div->name, &parent_data, 0, reg, div->shift, div->width, - CLK_DIVIDER_EVEN_INTEGERS, NULL, NULL); + div->table ? 0 : CLK_DIVIDER_EVEN_INTEGERS, div->table, NULL); cells->hws[div->index] =3D hw; if (IS_ERR(hw)) dev_warn(dev, "failed registering %s: %pe\n", --=20 2.51.0 From nobody Fri Oct 3 07:40:42 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D66AD30DD34; Wed, 3 Sep 2025 12:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903698; cv=none; b=P8RkXi0lX4D/qDSWRC3VT8mp5HLeIiph8ezzEQ4blu6GV9UAtbf3F0AgBIZXJOolpNRMkczJk2g7eTptLBruTcudz/bAj0nPzTZRfTsMGxWnl2PXrO6bfP5qh3+UirsOLbin+3TC0x+j4Egxx6j1zj9Ig7CoJMtKlJnKzSnzJCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756903698; c=relaxed/simple; bh=cqH0VxNb5n7kxL+3crRI7+cRuPrafE9H8Exy5gWNGZI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q9bO97k0y1mYbP48O4H0icusEvemG0R4T2zK7zthYbQI8px9qMIZD2euiNZIge+LmvWuiqVzEDZq3qyFdH6Hfn6YpN/DL28MaMboiZscAekERvJ1zH1UeXuGfSrMD1wHdF+nRFHaGivbbh2e/qAlkkMNe1Apc7P2agK6vGvRf/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=KDCHjsqz; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="KDCHjsqz" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 37A474E40C0A; Wed, 3 Sep 2025 12:48:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 10C8F606C3; Wed, 3 Sep 2025 12:48:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E61C01C22D6E3; Wed, 3 Sep 2025 14:48:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756903693; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=9DyI7fqJU5vfPrO1NrCHiyZ+Zl33oMOjd4I66nyHHWA=; b=KDCHjsqzqlPsp8N0CZmjWjfBpxCLf8bVRqKDtAYxdKIClcvSyoe/mcLiuAT7o/608D4KCi DxW/ukwX+Rc7ULCN4dtltj67anmHkFeAh9SzXJ7f/FhfyEqQBgozrAIHJoWwsDKYHIL2ma wE4e/TdR+nBOtXuIAXgPj3qzr5D6Hxdv+6hKqzMCZPW7Ch8Qs5Ke96Hz+oQ8jVNoz3LqVA Esc7UOCryEXzYT8owFvIYslIRRh0pTiErPgFW73N8TnnHN0irtX+yt3XEszWel15spGZ3Y NoBsZFkxI9GG6SotXNiD/P4g8Ba8ILWcgrtuYT/d7c0ikYlFmXYWK/acuSnMRg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Wed, 03 Sep 2025 14:47:26 +0200 Subject: [PATCH 19/19] clk: eyeq: add eyeQ7H compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-clk-eyeq7-v1-19-3f5024b5d6e2@bootlin.com> References: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> In-Reply-To: <20250903-clk-eyeq7-v1-0-3f5024b5d6e2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tawfik Bayouk , Sari Khoury , =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Add the entries for the 14 Other Logic Blocks found in the eyeQ7H SoC. The clock tree is more complex than the previous generation of SoC, as some OLB depend on the clock output of other OLB instead of all referring to the main oscillator. The OLB south, east and west generate those reference clocks used by other blocks. They also use the reference clock internally. To avoid creating a reference loop, we register those reference clocks early then refer to them at probe time. This is the same approach that is used for the clocks of the eyeQ5 OLB. The reference clock provided by OLB south is named "ref_100p0", "ref_106p6_e" by OLB east and "ref_106p6_w" by OLB west. For the OLB with a single parent clock, We use the same logic as the blocks found in previous SoC and refer to it with the implied name "ref". The OLB with two parent clocks use the reference clock names provided by the OLB south, east and west and the main oscillator as "ref". The reset controllers found is 11 of the OLB are declared as auxiliary device attached to the clock device. Signed-off-by: Beno=C3=AEt Monin --- drivers/clk/clk-eyeq.c | 495 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 495 insertions(+) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 8d5e194215e9d3d13b334a5ebf004499050e84b9..b9437003024fd0766fb1bd5d3e4= 916263f9cc854 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -824,6 +824,464 @@ static const struct eqc_match_data eqc_eyeq6h_acc_mat= ch_data =3D { .reset_auxdev_name =3D "reset_acc", }; =20 +/* Required early as reference for other PLL in OLB south */ +static const struct eqc_pll eqc_eyeq7h_south_early_plls[] =3D { + { EQ7HC_SOUTH_PLL_100P0, "pll-100p0", 0x40, EQC_PLL_JFRACR }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_south_early_fixed_factors[= ] =3D { + { EQ7HC_SOUTH_DIV_REF_100P0, "ref_100p0", 1, 48, EQ7HC_SOUTH_PLL_100P0 }, +}; + +static const struct eqc_pll eqc_eyeq7h_south_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_SOUTH_PLL_XSPI, "pll-xspi", 0x10, EQC_PLL_AINTP, "ref_100p0" }, + { EQ7HC_SOUTH_PLL_VDIO, "pll-vdio", 0x18, EQC_PLL_AINTP, "ref_100p0" }, + { EQ7HC_SOUTH_PLL_PER, "pll-per-s", 0x20, EQC_PLL_AINTP, "ref_100p0" }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_south_fixed_factors[] =3D { + { EQ7HC_SOUTH_DIV_VDO_DSI_SYS, "vdo_dsi_sys", 1, 9, EQ7HC_SOUTH= _PLL_100P0, + "pll-100p0" }, + { EQ7HC_SOUTH_DIV_PMA_CMN_REF, "pma_cmn_ref", 1, 48, EQ7HC_SOUTH= _PLL_100P0, + "pll-100p0" }, + { EQ7HC_SOUTH_DIV_REF_UFS, "ref_ufs", 1, 250, EQ7HC_SOUTH= _PLL_100P0, + "pll-100p0" }, + { EQ7HC_SOUTH_DIV_XSPI_SYS, "xspi_sys", 1, 8, EQ7HC_SOUTH= _PLL_XSPI }, + { EQ7HC_SOUTH_DIV_XSPI_MBITS, "xspi_mbits", 1, 8, EQ7HC_SOUTH= _PLL_XSPI }, + { EQ7HC_SOUTH_DIV_NOC_S, "noc_s", 1, 2, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_PCIE_SYS, "pcie_sys", 1, 4, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_PCIE_SYS_MBITS, "pcie_sys_mbits", 1, 4, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_PCIE_GBE_PHY, "pcie_gbe_phy_apb", 1, 16, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_UFS_CORE, "ufs_core", 1, 8, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_UFS_SMS, "ufs_sms", 1, 5, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_UFS_ROM_SMS, "ufs_rom_sms", 1, 5, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_ETH_SYS, "eth_sys", 1, 8, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_ETH_MBITS, "eth_mbits", 1, 8, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_CFG_S, "cfg_s", 1, 8, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_TSU, "tsu", 1, 64, EQ7HC_SOUTH= _PLL_PER }, + { EQ7HC_SOUTH_DIV_VDIO, "vdio", 1, 4, EQ7HC_SOUTH= _PLL_VDIO }, + { EQ7HC_SOUTH_DIV_VDIO_CORE, "vdio_core", 1, 4, EQ7HC_SOUTH= _PLL_VDIO }, + { EQ7HC_SOUTH_DIV_VDIO_CORE_MBIT, "vdio_core_mbit", 1, 4, EQ7HC_SOUTH= _PLL_VDIO }, + { EQ7HC_SOUTH_DIV_VDO_CORE_MBITS, "vdo_core_mbits", 1, 4, EQ7HC_SOUTH= _PLL_VDIO }, + { EQ7HC_SOUTH_DIV_VDO_P, "vdo_p", 1, 40, EQ7HC_SOUTH= _PLL_VDIO }, + { EQ7HC_SOUTH_DIV_VDIO_CFG, "vdio_cfg", 1, 150, EQ7HC_SOUTH= _PLL_VDIO }, + { EQ7HC_SOUTH_DIV_VDIO_TXCLKESC, "vdio_txclkesc", 1, 8, EQ7HC_SOUTH= _PLL_VDIO }, +}; + +static const struct eqc_early_match_data eqc_eyeq7h_south_early_match_data= __initconst =3D { + .early_pll_count =3D ARRAY_SIZE(eqc_eyeq7h_south_early_plls), + .early_plls =3D eqc_eyeq7h_south_early_plls, + + .early_fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_south_early_fixed_fac= tors), + .early_fixed_factors =3D eqc_eyeq7h_south_early_fixed_factors, + + .late_clk_count =3D ARRAY_SIZE(eqc_eyeq7h_south_plls) + + ARRAY_SIZE(eqc_eyeq7h_south_fixed_factors), +}; + +static const struct eqc_match_data eqc_eyeq7h_south_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_south_plls), + .plls =3D eqc_eyeq7h_south_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_south_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_south_fixed_factors, + + .reset_auxdev_name =3D "reset_south", + + .early_clk_count =3D ARRAY_SIZE(eqc_eyeq7h_south_early_plls) + + ARRAY_SIZE(eqc_eyeq7h_south_early_fixed_factors), +}; + +/* Required early as reference for other PLL in OLB east */ +static const struct eqc_pll eqc_eyeq7h_east_early_plls[] =3D { + { EQ7HC_EAST_PLL_106P6, "pll-106p6-e", 0x0, EQC_PLL_JFRACR }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_east_early_fixed_factors[]= =3D { + { EQ7HC_EAST_DIV_REF_106P6, "ref_106p6_e", 1, 40, EQ7HC_EAST_PLL_106P6 }, +}; + +static const struct eqc_pll eqc_eyeq7h_east_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_EAST_PLL_NOC, "pll-noc-e", 0x30, EQC_PLL_AINTP, "ref_106p6_e" }, + { EQ7HC_EAST_PLL_ISP, "pll-isp", 0x38, EQC_PLL_AINTP, "ref_100p0" }, + { EQ7HC_EAST_PLL_VEU, "pll-veu", 0x40, EQC_PLL_AINTP, "ref_100p0" }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_east_fixed_factors[] =3D { + { EQ7HC_EAST_DIV_REF_DDR_PHY, "ref_ddr_phy_e", 1, 2, EQ7HC_EAST_PLL_106P= 6, "pll-106p6-e" }, + { EQ7HC_EAST_DIV_CORE, "core_e", 1, 2, EQ7HC_EAST_PLL_NOC = }, + { EQ7HC_EAST_DIV_CORE_MBITS, "core_mbits_e", 1, 2, EQ7HC_EAST_PLL_NOC = }, + { EQ7HC_EAST_DIV_ISRAM_MBITS, "isram_mbits_e", 1, 2, EQ7HC_EAST_PLL_NOC = }, + { EQ7HC_EAST_DIV_CFG, "cfg_e", 1, 4, EQ7HC_EAST_PLL_NOC = }, + { EQ7HC_EAST_DIV_VEU_CORE, "veu_core", 1, 4, EQ7HC_EAST_PLL_VEU = }, + { EQ7HC_EAST_DIV_VEU_MBITS, "veu_mbits", 1, 4, EQ7HC_EAST_PLL_VEU = }, + { EQ7HC_EAST_DIV_VEU_OCP, "veu_ocp", 1, 16, EQ7HC_EAST_PLL_VEU = }, + { EQ7HC_EAST_DIV_LBITS, "lbits_e", 1, 48, EQ7HC_EAST_PLL_ISP = }, + { EQ7HC_EAST_DIV_ISP0_CORE, "isp0_core", 1, 2, EQ7HC_EAST_PLL_ISP = }, +}; + +static const struct eqc_early_match_data eqc_eyeq7h_east_early_match_data = __initconst =3D { + .early_pll_count =3D ARRAY_SIZE(eqc_eyeq7h_east_early_plls), + .early_plls =3D eqc_eyeq7h_east_early_plls, + + .early_fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_east_early_fixed_fact= ors), + .early_fixed_factors =3D eqc_eyeq7h_east_early_fixed_factors, + + .late_clk_count =3D ARRAY_SIZE(eqc_eyeq7h_east_plls) + + ARRAY_SIZE(eqc_eyeq7h_east_fixed_factors), +}; + +static const struct eqc_match_data eqc_eyeq7h_east_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_east_plls), + .plls =3D eqc_eyeq7h_east_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_east_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_east_fixed_factors, + + .reset_auxdev_name =3D "reset_east", + + .early_clk_count =3D ARRAY_SIZE(eqc_eyeq7h_east_early_plls) + + ARRAY_SIZE(eqc_eyeq7h_east_early_fixed_factors), +}; + +/* Required early as reference for other PLL in OLB west */ +static const struct eqc_pll eqc_eyeq7h_west_early_plls[] =3D { + { EQ7HC_WEST_PLL_106P6, "pll-106p6-w", 0x0, EQC_PLL_JFRACR }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_west_early_fixed_factors[]= =3D { + { EQ7HC_WEST_DIV_REF_106P6, "ref_106p6_w", 1, 40, EQ7HC_WEST_PLL_106P6 }, +}; + +static const struct eqc_pll eqc_eyeq7h_west_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_WEST_PLL_NOC, "pll-noc-w", 0x30, EQC_PLL_AINTP, "ref_106p6_w" }, + { EQ7HC_WEST_PLL_GPU, "pll-gpu", 0x38, EQC_PLL_AINTP, "ref_100p0" }, + { EQ7HC_WEST_PLL_SSI, "pll-ssi", 0x40, EQC_PLL_AINTP, "ref_100p0" }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_west_fixed_factors[] =3D { + { EQ7HC_WEST_DIV_GPU, "gpu", 1, 2, EQ7HC_WEST_PLL_= GPU }, + { EQ7HC_WEST_DIV_GPU_MBITS, "gpu_mbits", 1, 2, EQ7HC_WEST_PLL_= GPU }, + { EQ7HC_WEST_DIV_LBITS, "lbits_w", 1, 40, EQ7HC_WEST_PLL_= GPU }, + { EQ7HC_WEST_DIV_MIPS_TIMER, "mips_timer", 1, 24, EQ7HC_WEST_PLL_= SSI }, + { EQ7HC_WEST_DIV_SSI_CORE, "ssi_core", 1, 2, EQ7HC_WEST_PLL_= SSI }, + { EQ7HC_WEST_DIV_SSI_CORE_MBITS, "ssi_core_mbits", 1, 2, EQ7HC_WEST_PLL_= SSI }, + { EQ7HC_WEST_DIV_SSI_ROM, "ssi_rom", 1, 8, EQ7HC_WEST_PLL_= SSI }, + { EQ7HC_WEST_DIV_SSI_ROM_MBITS, "ssi_rom_mbits", 1, 8, EQ7HC_WEST_PLL_= SSI }, + { EQ7HC_WEST_DIV_REF_DDR_PHY, "ref_ddr_phy_w", 1, 2, EQ7HC_WEST_PLL_= 106P6, + "pll-106p6-w" }, + { EQ7HC_WEST_DIV_CORE, "core_w", 1, 2, EQ7HC_WEST_PLL_= NOC }, + { EQ7HC_WEST_DIV_CORE_MBIT, "core_mbit_w", 1, 2, EQ7HC_WEST_PLL_= NOC }, + { EQ7HC_WEST_DIV_CFG, "cfg_w", 1, 4, EQ7HC_WEST_PLL_= NOC }, + { EQ7HC_WEST_DIV_CAU, "cau_w", 1, 8, EQ7HC_WEST_PLL_= NOC }, + { EQ7HC_WEST_DIV_CAU_MBITS, "cau_mbits_w", 1, 8, EQ7HC_WEST_PLL_= NOC }, +}; + +static const struct eqc_early_match_data eqc_eyeq7h_west_early_match_data = __initconst =3D { + .early_pll_count =3D ARRAY_SIZE(eqc_eyeq7h_west_early_plls), + .early_plls =3D eqc_eyeq7h_west_early_plls, + + .early_fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_west_early_fixed_fact= ors), + .early_fixed_factors =3D eqc_eyeq7h_west_early_fixed_factors, + + .late_clk_count =3D ARRAY_SIZE(eqc_eyeq7h_west_plls) + + ARRAY_SIZE(eqc_eyeq7h_west_fixed_factors), +}; + +static const struct eqc_match_data eqc_eyeq7h_west_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_west_plls), + .plls =3D eqc_eyeq7h_west_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_west_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_west_fixed_factors, + + .reset_auxdev_name =3D "reset_west", + + .early_clk_count =3D ARRAY_SIZE(eqc_eyeq7h_west_early_plls) + + ARRAY_SIZE(eqc_eyeq7h_west_early_fixed_factors), +}; + +static const struct eqc_pll eqc_eyeq7h_periph_east_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_PERIPH_EAST_PLL_PER, "pll-periph_east_per", 0x0, EQC_PLL_AINTP }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_periph_east_fixed_factors[= ] =3D { + { EQ7HC_PERIPH_EAST_DIV_PER, "periph_e", 1, 10, EQ7HC_PERIPH_EAST_PLL_PER= }, +}; + +static const struct eqc_match_data eqc_eyeq7h_periph_east_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_periph_east_plls), + .plls =3D eqc_eyeq7h_periph_east_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_periph_east_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_periph_east_fixed_factors, + + .reset_auxdev_name =3D "reset_periph_east", +}; + +static const struct eqc_pll eqc_eyeq7h_periph_west_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_PERIPH_WEST_PLL_PER, "pll-periph_west_per", 0x0, EQC_PLL_AINTP, "= ref_100p0" }, + { EQ7HC_PERIPH_WEST_PLL_I2S, "pll-periph_west_i2s", 0x4, EQC_PLL_AINTP, "= ref_106p6_w" }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_periph_west_fixed_factors[= ] =3D { + { EQ7HC_PERIPH_WEST_DIV_PER, "periph_w", 1, 10, EQ7HC_PERIPH_WEST= _PLL_PER }, + { EQ7HC_PERIPH_WEST_DIV_I2S, "periph_i2s_ser_w", 1, 100, EQ7HC_PERIPH_WES= T_PLL_I2S }, +}; + +static const struct eqc_match_data eqc_eyeq7h_periph_west_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_periph_west_plls), + .plls =3D eqc_eyeq7h_periph_west_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_periph_west_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_periph_west_fixed_factors, + + .reset_auxdev_name =3D "reset_periph_west", +}; + +static const struct clk_div_table eqc_eyeq7h_ddr_apb_div_table[] =3D { + { .val =3D 0, .div =3D 8 }, + { .val =3D 1, .div =3D 128 }, + { .val =3D 0, .div =3D 0 }, +}; + +static const struct clk_div_table eqc_eyeq7h_ddr_ref_div_table[] =3D { + { .val =3D 0, .div =3D 2 }, + { .val =3D 1, .div =3D 8 }, + { .val =3D 0, .div =3D 0 }, +}; + +static const struct clk_div_table eqc_eyeq7h_ddr_dfi_div_table[] =3D { + { .val =3D 0, .div =3D 2 }, + { .val =3D 1, .div =3D 32 }, + { .val =3D 0, .div =3D 0 }, +}; + +static const struct eqc_div eqc_eyeq7h_ddr0_divs[] =3D { + { + .index =3D EQ7HC_DDR_DIV_APB, + .name =3D "div-ddr0_apb", + .parent_idx =3D EQ7HC_DDR_PLL, + .reg =3D 0x08, + .shift =3D 10, + .width =3D 1, + .table =3D eqc_eyeq7h_ddr_apb_div_table, + }, + { + .index =3D EQ7HC_DDR_DIV_PLLREF, + .name =3D "div-ddr0_pllref", + .parent_idx =3D EQ7HC_DDR_PLL, + .reg =3D 0x08, + .shift =3D 10, + .width =3D 1, + .table =3D eqc_eyeq7h_ddr_ref_div_table, + }, + { + .index =3D EQ7HC_DDR_DIV_DFI, + .name =3D "div-ddr0-dfi", + .parent_idx =3D EQ7HC_DDR_PLL, + .reg =3D 0x08, + .shift =3D 10, + .width =3D 1, + .table =3D eqc_eyeq7h_ddr_dfi_div_table, + }, +}; + +static const struct eqc_pll eqc_eyeq7h_ddr0_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_DDR_PLL, "pll-ddr0", 0x0, EQC_PLL_AINTP }, +}; + +static const struct eqc_match_data eqc_eyeq7h_ddr0_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_ddr0_plls), + .plls =3D eqc_eyeq7h_ddr0_plls, + + .div_count =3D ARRAY_SIZE(eqc_eyeq7h_ddr0_divs), + .divs =3D eqc_eyeq7h_ddr0_divs, + + .reset_auxdev_name =3D "reset_ddr0", +}; + +static const struct eqc_div eqc_eyeq7h_ddr1_divs[] =3D { + { + .index =3D EQ7HC_DDR_DIV_APB, + .name =3D "div-ddr1_apb", + .parent_idx =3D EQ7HC_DDR_PLL, + .reg =3D 0x08, + .shift =3D 10, + .width =3D 1, + .table =3D eqc_eyeq7h_ddr_apb_div_table, + }, + { + .index =3D EQ7HC_DDR_DIV_PLLREF, + .name =3D "div-ddr1_pllref", + .parent_idx =3D EQ7HC_DDR_PLL, + .reg =3D 0x08, + .shift =3D 10, + .width =3D 1, + .table =3D eqc_eyeq7h_ddr_ref_div_table, + }, + { + .index =3D EQ7HC_DDR_DIV_DFI, + .name =3D "div-ddr1-dfi", + .parent_idx =3D EQ7HC_DDR_PLL, + .reg =3D 0x08, + .shift =3D 10, + .width =3D 1, + .table =3D eqc_eyeq7h_ddr_dfi_div_table, + }, +}; + +static const struct eqc_pll eqc_eyeq7h_ddr1_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_DDR_PLL, "pll-ddr1", 0x0, EQC_PLL_AINTP }, +}; + +static const struct eqc_match_data eqc_eyeq7h_ddr1_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_ddr1_plls), + .plls =3D eqc_eyeq7h_ddr1_plls, + + .div_count =3D ARRAY_SIZE(eqc_eyeq7h_ddr1_divs), + .divs =3D eqc_eyeq7h_ddr1_divs, + + .reset_auxdev_name =3D "reset_ddr1", +}; + +static const struct eqc_pll eqc_eyeq7h_mips0_plls[] =3D { + { EQ7HC_MIPS_PLL_CPU, "pll-cpu0", 0x0, EQC_PLL_AINTP }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_mips0_fixed_factors[] =3D { + { EQ7HC_MIPS_DIV_CM, "mips0_cm", 1, 2, EQ7HC_MIPS_PLL_CPU }, +}; + +static const struct eqc_match_data eqc_eyeq7h_mips0_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_mips0_plls), + .plls =3D eqc_eyeq7h_mips0_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_mips0_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_mips0_fixed_factors, +}; + +static const struct eqc_pll eqc_eyeq7h_mips1_plls[] =3D { + { EQ7HC_MIPS_PLL_CPU, "pll-cpu1", 0x0, EQC_PLL_AINTP }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_mips1_fixed_factors[] =3D { + { EQ7HC_MIPS_DIV_CM, "mips1_cm", 1, 2, EQ7HC_MIPS_PLL_CPU }, +}; + +static const struct eqc_match_data eqc_eyeq7h_mips1_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_mips1_plls), + .plls =3D eqc_eyeq7h_mips1_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_mips1_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_mips1_fixed_factors, +}; + +static const struct eqc_pll eqc_eyeq7h_mips2_plls[] =3D { + { EQ7HC_MIPS_PLL_CPU, "pll-cpu2", 0x0, EQC_PLL_AINTP }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_mips2_fixed_factors[] =3D { + { EQ7HC_MIPS_DIV_CM, "mips2_cm", 1, 2, EQ7HC_MIPS_PLL_CPU }, +}; + +static const struct eqc_match_data eqc_eyeq7h_mips2_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_mips2_plls), + .plls =3D eqc_eyeq7h_mips2_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_mips2_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_mips2_fixed_factors, +}; + +static const struct eqc_pll eqc_eyeq7h_acc0_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_ACC_PLL_VMP, "pll-acc0-vmp", 0x400, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_ACC_PLL_MPC, "pll-acc0-mpc", 0x404, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_ACC_PLL_PMA, "pll-acc0-pma", 0x408, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_ACC_PLL_NOC, "pll-acc0-noc-acc", 0x40c, EQC_PLL_AINTP, "ref_106p6= _e" }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_acc0_fixed_factors[] =3D { + { EQ7HC_ACC_DIV_PMA, "acc0_pma", 1, 2, EQ7HC_ACC_PLL_PMA }, + { EQ7HC_ACC_DIV_NCORE, "acc0_ncore", 1, 2, EQ7HC_ACC_PLL_NOC }, + { EQ7HC_ACC_DIV_CFG, "acc0_cfg", 1, 8, EQ7HC_ACC_PLL_NOC }, +}; + +static const struct eqc_match_data eqc_eyeq7h_acc0_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_acc0_plls), + .plls =3D eqc_eyeq7h_acc0_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_acc0_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_acc0_fixed_factors, + + .reset_auxdev_name =3D "reset_acc0", +}; + +static const struct eqc_pll eqc_eyeq7h_acc1_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_ACC_PLL_VMP, "pll-acc1-vmp", 0x400, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_ACC_PLL_MPC, "pll-acc1-mpc", 0x404, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_ACC_PLL_PMA, "pll-acc1-pma", 0x408, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_ACC_PLL_NOC, "pll-acc1-noc-acc", 0x40c, EQC_PLL_AINTP, "ref_106p6= _e" }, +}; + +static const struct eqc_match_data eqc_eyeq7h_acc1_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_acc1_plls), + .plls =3D eqc_eyeq7h_acc1_plls, + + .reset_auxdev_name =3D "reset_acc1", +}; + +static const struct eqc_pll eqc_eyeq7h_xnn0_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_XNN_PLL_XNN0, "pll-xnn0-0", 0x400, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_XNN_PLL_XNN1, "pll-xnn0-1", 0x404, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_XNN_PLL_XNN2, "pll-xnn0-2", 0x408, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_XNN_PLL_CLSTR, "pll-xnn0-clstr", 0x410, EQC_PLL_AINTP, "ref_106p6= _e" }, +}; + +static const struct eqc_fixed_factor eqc_eyeq7h_xnn0_fixed_factors[] =3D { + { EQ7HC_XNN_DIV_XNN0, "xnn0", 1, 2, EQ7HC_XNN_PLL_XNN0 }, + { EQ7HC_XNN_DIV_XNN1, "xnn1", 1, 2, EQ7HC_XNN_PLL_XNN1 }, + { EQ7HC_XNN_DIV_XNN2, "xnn2", 1, 2, EQ7HC_XNN_PLL_XNN2 }, + { EQ7HC_XNN_DIV_CLSTR, "xnn0_clstr", 1, 2, EQ7HC_XNN_PLL_CLSTR }, + { EQ7HC_XNN_DIV_I2, "xnn0_i2", 1, 4, EQ7HC_XNN_PLL_CLSTR }, + { EQ7HC_XNN_DIV_I2_SMS, "xnn0_i2_sms", 1, 4, EQ7HC_XNN_PLL_CLSTR }, + { EQ7HC_XNN_DIV_CFG, "xnn0_cfg", 1, 8, EQ7HC_XNN_PLL_CLSTR }, +}; + +static const struct eqc_match_data eqc_eyeq7h_xnn0_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_xnn0_plls), + .plls =3D eqc_eyeq7h_xnn0_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq7h_xnn0_fixed_factors), + .fixed_factors =3D eqc_eyeq7h_xnn0_fixed_factors, + + .reset_auxdev_name =3D "reset_xnn0", +}; + +static const struct eqc_pll eqc_eyeq7h_xnn1_plls[] =3D { + //{index, name, reg, type, parent} + { EQ7HC_XNN_PLL_XNN0, "pll-xnn1-0", 0x400, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_XNN_PLL_XNN1, "pll-xnn1-1", 0x404, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_XNN_PLL_XNN2, "pll-xnn1-2", 0x408, EQC_PLL_AINTP, "ref_100p0= " }, + { EQ7HC_XNN_PLL_CLSTR, "pll-xnn1-clstr", 0x410, EQC_PLL_AINTP, "ref_106p6= _e" }, +}; + +static const struct eqc_match_data eqc_eyeq7h_xnn1_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq7h_xnn1_plls), + .plls =3D eqc_eyeq7h_xnn1_plls, + + .reset_auxdev_name =3D "reset_xnn1", +}; + static const struct of_device_id eqc_match_table[] =3D { { .compatible =3D "mobileye,eyeq5-olb", .data =3D &eqc_eyeq5_match_data }, { .compatible =3D "mobileye,eyeq6l-olb", .data =3D &eqc_eyeq6l_match_data= }, @@ -833,6 +1291,22 @@ static const struct of_device_id eqc_match_table[] = =3D { { .compatible =3D "mobileye,eyeq6h-ddr0-olb", .data =3D &eqc_eyeq6h_ddr0_= match_data }, { .compatible =3D "mobileye,eyeq6h-ddr1-olb", .data =3D &eqc_eyeq6h_ddr1_= match_data }, { .compatible =3D "mobileye,eyeq6h-acc-olb", .data =3D &eqc_eyeq6h_acc_ma= tch_data }, + { .compatible =3D "mobileye,eyeq7h-periph-west-olb", + .data =3D &eqc_eyeq7h_periph_west_match_data }, + { .compatible =3D "mobileye,eyeq7h-periph-east-olb", + .data =3D &eqc_eyeq7h_periph_east_match_data }, + { .compatible =3D "mobileye,eyeq7h-west-olb", .data =3D &eqc_eyeq7h_west_= match_data }, + { .compatible =3D "mobileye,eyeq7h-east-olb", .data =3D &eqc_eyeq7h_east_= match_data }, + { .compatible =3D "mobileye,eyeq7h-south-olb", .data =3D &eqc_eyeq7h_sout= h_match_data }, + { .compatible =3D "mobileye,eyeq7h-mips0-olb", .data =3D &eqc_eyeq7h_mips= 0_match_data }, + { .compatible =3D "mobileye,eyeq7h-mips1-olb", .data =3D &eqc_eyeq7h_mips= 1_match_data }, + { .compatible =3D "mobileye,eyeq7h-mips2-olb", .data =3D &eqc_eyeq7h_mips= 2_match_data }, + { .compatible =3D "mobileye,eyeq7h-ddr0-olb", .data =3D &eqc_eyeq7h_ddr0_= match_data }, + { .compatible =3D "mobileye,eyeq7h-ddr1-olb", .data =3D &eqc_eyeq7h_ddr1_= match_data }, + { .compatible =3D "mobileye,eyeq7h-acc0-olb", .data =3D &eqc_eyeq7h_acc0_= match_data }, + { .compatible =3D "mobileye,eyeq7h-acc1-olb", .data =3D &eqc_eyeq7h_acc1_= match_data }, + { .compatible =3D "mobileye,eyeq7h-xnn0-olb", .data =3D &eqc_eyeq7h_xnn0_= match_data }, + { .compatible =3D "mobileye,eyeq7h-xnn1-olb", .data =3D &eqc_eyeq7h_xnn1_= match_data }, {} }; =20 @@ -1004,3 +1478,24 @@ static void __init eqc_eyeq6h_west_early_init(struct= device_node *np) } CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_west, "mobileye,eyeq6h-west-olb", eqc_eyeq6h_west_early_init); + +static void __init eqc_eyeq7h_south_early_init(struct device_node *np) +{ + eqc_early_init(np, &eqc_eyeq7h_south_early_match_data); +} +CLK_OF_DECLARE_DRIVER(eqc_eyeq7h_south, "mobileye,eyeq7h-south-olb", + eqc_eyeq7h_south_early_init); + +static void __init eqc_eyeq7h_east_early_init(struct device_node *np) +{ + eqc_early_init(np, &eqc_eyeq7h_east_early_match_data); +} +CLK_OF_DECLARE_DRIVER(eqc_eyeq7h_east, "mobileye,eyeq7h-east-olb", + eqc_eyeq7h_east_early_init); + +static void __init eqc_eyeq7h_west_early_init(struct device_node *np) +{ + eqc_early_init(np, &eqc_eyeq7h_west_early_match_data); +} +CLK_OF_DECLARE_DRIVER(eqc_eyeq7h_west, "mobileye,eyeq7h-west-olb", + eqc_eyeq7h_west_early_init); --=20 2.51.0