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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-329e3a6720asm4856888a91.11.2025.09.03.03.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 03:52:01 -0700 (PDT) From: Fange Zhang Date: Wed, 03 Sep 2025 18:49:28 +0800 Subject: [PATCH v8 1/2] arm64: dts: qcom: Add display support for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-add-display-support-for-qcs615-platform-v8-1-7971c05d1262@oss.qualcomm.com> References: <20250903-add-display-support-for-qcs615-platform-v8-0-7971c05d1262@oss.qualcomm.com> In-Reply-To: <20250903-add-display-support-for-qcs615-platform-v8-0-7971c05d1262@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , xiangxu.yin@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Li Liu , Fange Zhang , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756896714; l=5827; i=fange.zhang@oss.qualcomm.com; s=20250714; h=from:subject:message-id; bh=uXlwezLY7U3gqs8X4zeTpdCd9Lux78E+OqnciVI8/Jk=; b=nJMMlMxwmLRBPOm8DOtATHaZV3jr336k5oN3dKsp8USIFCY8D7t9Q2Bg+o/o8b1NgUhZCNBc0 ThYkwUazfukDErkAalcbvZZb8ctAO1ZbyLXAF4qHodyLLWc2GJkgHVP X-Developer-Key: i=fange.zhang@oss.qualcomm.com; a=ed25519; pk=tn190A7bjF3/EyH7AYy/eNzPoS9lwXGznYamlMv6TE0= X-Authority-Analysis: v=2.4 cv=Ycq95xRf c=1 sm=1 tr=0 ts=68b81dd4 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=Roi-LC9FDB9nNxv02foA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: IVLx_gafQnrv-YOs0C4SKxk7Mg7ofi6f X-Proofpoint-ORIG-GUID: IVLx_gafQnrv-YOs0C4SKxk7Mg7ofi6f X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTAxMDEwMSBTYWx0ZWRfXyc5qg8vuN5OT +lZbuB3b+z+p48oUC+MP/cl3EIimtlE6JiXJdqUZH4sBJ77Ynea/VbXal/yE691aijqemQQGpLw RG5WiEsc+XL9VHWqmBUDOacxsy3posO/m1IU3qB8RhVurIdCqmpvMegwfmanhFqjCpx6lWFPACS PP2lE/TAkChHLpVyJQY8E9kr/96Gs7yiiJ57zJ1ri2Wt9Z8MD7sdm+7VqU6Xyc0qdSlbIVzcX0d RnjT0+TQ2NSc2rUJMWBhwb8AzWOlkh4TYVw1ETqyOzK6hpdPZr4M8Ll112UzItsq7Kp9c9IrxxC lYQcDWm54dKKRK4Iq6oJPpx2wDIsD46peEpBXcN+ouMC2NtnEcI7JRZ71ccg+o7Hfjnro4SVtO7 TB12wZg3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509010101 From: Li Liu Add display MDSS and DSI configuration for QCS615 platform. QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 182 +++++++++++++++++++++++++++++++= +++- 1 file changed, 180 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 53496241479a05fec7bffa893b96b2d12b2d7614..c0e6485c148a059f6c0b2d221a9= ee34b0220ea06 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include #include #include #include @@ -3579,14 +3580,191 @@ camcc: clock-controller@ad00000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm6150-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_CORE_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm6150-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", + "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + interrupts-extended =3D <&mdss 0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-164000000 { + opp-hz =3D /bits/ 64 <164000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sm6150-dsi-phy-14nm"; + reg =3D <0x0 0x0ae94400 0x0 0x100>, + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x124>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,qcs615-dispcc"; reg =3D <0 0x0af00000 0 0x20000>; =20 clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>, <0>; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-329e3a6720asm4856888a91.11.2025.09.03.03.52.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 03:52:05 -0700 (PDT) From: Fange Zhang Date: Wed, 03 Sep 2025 18:49:29 +0800 Subject: [PATCH v8 2/2] arm64: dts: qcom: Add display support for QCS615 RIDE board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-add-display-support-for-qcs615-platform-v8-2-7971c05d1262@oss.qualcomm.com> References: <20250903-add-display-support-for-qcs615-platform-v8-0-7971c05d1262@oss.qualcomm.com> In-Reply-To: <20250903-add-display-support-for-qcs615-platform-v8-0-7971c05d1262@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , xiangxu.yin@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Li Liu , Fange Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756896714; l=4362; i=fange.zhang@oss.qualcomm.com; s=20250714; h=from:subject:message-id; bh=iioqO7Yy62GZNJa0hLNm5uNqstxqzn757DeXBVJ7XU4=; b=UYL982xrh2KbMh0Uyj5T1eMaCvghDY9q0URqUzRenLwApB4Hhk4i16F1DE/0fdr9BkUbzC8ag HHmLio/93f3ANtqCBNi8SgIvsqQbxF/LVO2FjnNl/kzxla/q71SvoVR X-Developer-Key: i=fange.zhang@oss.qualcomm.com; a=ed25519; pk=tn190A7bjF3/EyH7AYy/eNzPoS9lwXGznYamlMv6TE0= X-Authority-Analysis: v=2.4 cv=Ycq95xRf c=1 sm=1 tr=0 ts=68b81dd7 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=M5YQ4GC9HTMohWAA_GoA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: NTggXlBrhyXhG8kYJgkzsi1lbyNVWKHS X-Proofpoint-ORIG-GUID: NTggXlBrhyXhG8kYJgkzsi1lbyNVWKHS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTAxMDEwMSBTYWx0ZWRfX1blo5DuCUjOx TUJk8Teq2WAjKGT4jIpFayMzaVOOxKjw7yb7VkjsnAXRXBC36qu2HqpNfYK0+JNcQhjALh73KyM P9iNAqBqQ8BD+lritgFCg6MEKv4o0xs89NEtCCvjz8AL2cM8fHu3jx50s/1EA9pUWDfNmLDmfgP 3xmM3RgflqHAPK/UmI1iqC3byxgR7IOVSo8Y08o5WDeyd+fCp9/d9trDt/cW4JwPv5774D77rPj xw0WaVBK7PE6hiWrELxd9Qywm3PAeMIzRBTqsixxROUHa4FK/uw42buiAu4zcnpAkhIxYewBYAe fWKhh2GZjhuc57AtZC1+9FGvRsYN7tvkfqwMciVtKRClgkhMCse12BmM9r9+ly/89BXTi4rFp8g YHlsVcG/ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_06,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509010101 From: Li Liu Add display MDSS and DSI configuration for QCS615 RIDE board. QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 150 +++++++++++++++++++++++++++= ++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index e663343df75d59481786192cde647017a83c4191..00f85e58c941f59335a4e53fcac= d6779eaaf00c1 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -39,6 +39,18 @@ xo_board_clk: xo-board-clk { }; }; =20 + dp-dsi0-connector { + compatible =3D "dp-connector"; + label =3D "DSI0"; + type =3D "mini"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint =3D <&dsi2dp_bridge_out>; + }; + }; + }; + vreg_conn_1p8: regulator-conn-1p8 { compatible =3D "regulator-fixed"; regulator-name =3D "vreg_conn_1p8"; @@ -65,6 +77,64 @@ regulator-usb2-vbus { regulator-always-on; }; =20 + vreg_12p0: regulator-vreg-12p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_12P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vreg_1p0: regulator-vreg-1p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + + vin-supply =3D <&vreg_1p8>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + vin-supply =3D <&vreg_5p0>; + }; + + vreg_3p0: regulator-vreg-3p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_3P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + + vin-supply =3D <&vreg_12p0>; + }; + + vreg_5p0: regulator-vreg-5p0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_5P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + vin-supply =3D <&vreg_12p0>; + }; + wcn6855-pmu { compatible =3D "qcom,wcn6855-pmu"; =20 @@ -288,6 +358,86 @@ vreg_l17a: ldo17 { }; }; =20 +&i2c2 { + clock-frequency =3D <400000>; + status =3D "okay"; + + io_expander: pinctrl@3e { + compatible =3D "semtech,sx1509q"; + reg =3D <0x3e>; + interrupts-extended =3D <&tlmm 58 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + semtech,probe-reset; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9542"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + bridge@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupts-extended =3D <&io_expander 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; + vdd10-supply =3D <&vreg_1p0>; + vdd18-supply =3D <&vreg_1p8>; + vdd33-supply =3D <&vreg_3p0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dsi2dp_bridge_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi2dp_bridge_out: endpoint { + remote-endpoint =3D <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&dsi2dp_bridge_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vcca-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + &pcie { perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; --=20 2.34.1