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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3dc1cd4a7d2sm3996035f8f.33.2025.09.03.07.24.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 07:24:39 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 14:24:35 +0000 Subject: [PATCH v3 1/3] arm64: dts: exynos: gs101: add #clock-cells to the ACPM protocol node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-dvfs-dt-v3-1-f24059e5cd95@linaro.org> References: <20250903-acpm-dvfs-dt-v3-0-f24059e5cd95@linaro.org> In-Reply-To: <20250903-acpm-dvfs-dt-v3-0-f24059e5cd95@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756909477; l=858; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=O0ZaIGzNEXwrghncj9YNIJwIZXgEV0h6GP+O9Ob9bCc=; b=Vo6WkR/E//OV0DsTSlpds8sKzQhNQBSu+HqfP4AtDKHJiLDyc7STDizBG48Nhd4baH1I3LEcE 1EAmsYRXET3B43eHFQZqaTcqLTcXr2LlCFSs8nmManOhkxRVzbBznF4 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Make the ACPM node a clock provider by adding the mandatory "#clock-cells" property, which allows devices to reference its clock outputs. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin Tested-by: Peter Griffin # on gs101-oriole --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index c0f8c25861a9ddb5bbd256b62c66a645922ca74e..f00754692bbac39fd828ebd4ef7= c269f746f2522 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -202,6 +202,7 @@ ext_200m: clock-2 { firmware { acpm_ipc: power-management { compatible =3D "google,gs101-acpm-ipc"; + #clock-cells =3D <1>; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; }; --=20 2.51.0.338.gd7d06c2dae-goog From nobody Fri Oct 3 07:40:25 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CE6430DD04 for ; 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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3dc1cd4a7d2sm3996035f8f.33.2025.09.03.07.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 07:24:39 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 14:24:36 +0000 Subject: [PATCH v3 2/3] arm64: dts: exynos: gs101: add CPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-dvfs-dt-v3-2-f24059e5cd95@linaro.org> References: <20250903-acpm-dvfs-dt-v3-0-f24059e5cd95@linaro.org> In-Reply-To: <20250903-acpm-dvfs-dt-v3-0-f24059e5cd95@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756909477; l=3055; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=DvCybsMaaovaYrXT+kGukCydj98f0jObaOksmSKLE7g=; b=pVxjq+o735XuRTrAp24zmkgSEQyM98WPeI5CRx0F32McSQr5++j2fb9E7h3fx6kzQhtnAPJ9Z MQlithbin71DJfR1JpELcCBTH3/EWVBxgk3BV+R9iKiPVX/zygYfDLi X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the GS101 CPU clocks exposed through the ACPM protocol. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin Tested-by: Peter Griffin # on gs101-oriole --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index f00754692bbac39fd828ebd4ef7c269f746f2522..e355fafe2276fdfbcb573600474= cbdd26a654e7c 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -72,6 +73,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -82,6 +84,7 @@ cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -92,6 +95,7 @@ cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -102,6 +106,7 @@ cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -112,6 +117,7 @@ cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -122,6 +128,7 @@ cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; 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[35.233.43.219]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3dc1cd4a7d2sm3996035f8f.33.2025.09.03.07.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 07:24:40 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 14:24:37 +0000 Subject: [PATCH v3 3/3] arm64: dts: exynos: gs101: add OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-dvfs-dt-v3-3-f24059e5cd95@linaro.org> References: <20250903-acpm-dvfs-dt-v3-0-f24059e5cd95@linaro.org> In-Reply-To: <20250903-acpm-dvfs-dt-v3-0-f24059e5cd95@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756909477; l=8499; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=RvVu8WG3URT0piw1f9aHSn6PXTY0B6dQgb9rqghC/4w=; b=zx9QGLCrHs6y/TeSxlErivRRhCI+pDqOMKBKPWbNo08SjuusXP7t1+67s6yCJm2woRrpVz8em HzBsC0MKCTEAlz19WRgfqpdtOP9n0i7djOGv2l0IIjmShxk7eX3hRbl X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add operating performance points (OPPs). Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin Tested-by: Peter Griffin # on gs101-oriole --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 275 +++++++++++++++++++++++= ++++ 1 file changed, 275 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index e355fafe2276fdfbcb573600474cbdd26a654e7c..e810aea40b36e4e8bdbaf77513a= b1d4f058307f7 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -78,6 +78,7 @@ cpu0: cpu@0 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu1: cpu@100 { @@ -89,6 +90,7 @@ cpu1: cpu@100 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu2: cpu@200 { @@ -100,6 +102,7 @@ cpu2: cpu@200 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu3: cpu@300 { @@ -111,6 +114,7 @@ cpu3: cpu@300 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu4: cpu@400 { @@ -122,6 +126,7 @@ cpu4: cpu@400 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu5: cpu@500 { @@ -133,6 +138,7 @@ cpu5: cpu@500 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu6: cpu@600 { @@ -144,6 +150,7 @@ cpu6: cpu@600 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 cpu7: cpu@700 { @@ -155,6 +162,7 @@ cpu7: cpu@700 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 idle-states { @@ -192,6 +200,273 @@ hera_cpu_sleep: cpu-hera-sleep { }; }; =20 + cpucl0_opp_table: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <5000000>; + }; + + opp-574000000 { + opp-hz =3D /bits/ 64 <574000000>; + opp-microvolt =3D <600000>; + clock-latency-ns =3D <5000000>; + }; + + opp-738000000 { + opp-hz =3D /bits/ 64 <738000000>; + opp-microvolt =3D <618750>; + clock-latency-ns =3D <5000000>; + }; + + opp-930000000 { + opp-hz =3D /bits/ 64 <930000000>; + opp-microvolt =3D <668750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1098000000 { + opp-hz =3D /bits/ 64 <1098000000>; + opp-microvolt =3D <712500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <762500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1401000000 { + opp-hz =3D /bits/ 64 <1401000000>; + opp-microvolt =3D <781250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1598000000 { + opp-hz =3D /bits/ 64 <1598000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1704000000 { + opp-hz =3D /bits/ 64 <1704000000>; + opp-microvolt =3D <862500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1803000000 { + opp-hz =3D /bits/ 64 <1803000000>; + opp-microvolt =3D <906250>; + clock-latency-ns =3D <5000000>; + }; + }; + + cpucl1_opp_table: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <506250>; + clock-latency-ns =3D <5000000>; + }; + + opp-553000000 { + opp-hz =3D /bits/ 64 <553000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <5000000>; + }; + + opp-696000000 { + opp-hz =3D /bits/ 64 <696000000>; + opp-microvolt =3D <562500>; + clock-latency-ns =3D <5000000>; + }; + + opp-799000000 { + opp-hz =3D /bits/ 64 <799000000>; + opp-microvolt =3D <581250>; + clock-latency-ns =3D <5000000>; + }; + + opp-910000000 { + opp-hz =3D /bits/ 64 <910000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1024000000 { + opp-hz =3D /bits/ 64 <1024000000>; + opp-microvolt =3D <625000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <687500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1491000000 { + opp-hz =3D /bits/ 64 <1491000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1663000000 { + opp-hz =3D /bits/ 64 <1663000000>; + opp-microvolt =3D <775000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1836000000 { + opp-hz =3D /bits/ 64 <1836000000>; + opp-microvolt =3D <818750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1999000000 { + opp-hz =3D /bits/ 64 <1999000000>; + opp-microvolt =3D <868750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2130000000 { + opp-hz =3D /bits/ 64 <2130000000>; + opp-microvolt =3D <918750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2253000000 { + opp-hz =3D /bits/ 64 <2253000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <5000000>; + }; + }; + + cpucl2_opp_table: opp-table-2 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <500000>; + clock-latency-ns =3D <5000000>; + }; + + opp-851000000 { + opp-hz =3D /bits/ 64 <851000000>; + opp-microvolt =3D <556250>; + clock-latency-ns =3D <5000000>; + }; + + opp-984000000 { + opp-hz =3D /bits/ 64 <984000000>; + opp-microvolt =3D <575000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1106000000 { + opp-hz =3D /bits/ 64 <1106000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1277000000 { + opp-hz =3D /bits/ 64 <1277000000>; + opp-microvolt =3D <631250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1426000000 { + opp-hz =3D /bits/ 64 <1426000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1582000000 { + opp-hz =3D /bits/ 64 <1582000000>; + opp-microvolt =3D <693750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1745000000 { + opp-hz =3D /bits/ 64 <1745000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1826000000 { + opp-hz =3D /bits/ 64 <1826000000>; + opp-microvolt =3D <750000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2048000000 { + opp-hz =3D /bits/ 64 <2048000000>; + opp-microvolt =3D <793750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2188000000 { + opp-hz =3D /bits/ 64 <2188000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <5000000>; + }; + + opp-2252000000 { + opp-hz =3D /bits/ 64 <2252000000>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2401000000 { + opp-hz =3D /bits/ 64 <2401000000>; + opp-microvolt =3D <887500>; + clock-latency-ns =3D <5000000>; + }; + + opp-2507000000 { + opp-hz =3D /bits/ 64 <2507000000>; + opp-microvolt =3D <925000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2630000000 { + opp-hz =3D /bits/ 64 <2630000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2704000000 { + opp-hz =3D /bits/ 64 <2704000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2802000000 { + opp-hz =3D /bits/ 64 <2802000000>; + opp-microvolt =3D <1056250>; + clock-latency-ns =3D <5000000>; + }; + }; + /* ect node is required to be present by bootloader */ ect { }; --=20 2.51.0.338.gd7d06c2dae-goog