From nobody Fri Oct 3 07:49:45 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDCEC30E0E7 for ; Wed, 3 Sep 2025 13:56:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907807; cv=none; b=KyaHUuHh6Y9Bly/jqM86Koc6aJF7/bx2Q8s5KYXWfji/0nBYA5yWOWSPjokR4LhtDX8GqaemZpMobQBS07z/AQEpZxxiNDR4bQeONkZdqLfIj3MF4VSkXqcmr1bmRxVX9QZG3BHC4n/RiXh7f4CjBZGXZMlFk+B1yBOU5G9qW1s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907807; c=relaxed/simple; bh=ZAh+jVEjk+p7IOugFLPfvW1C8t+Wsd6E695/908UhEY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pBF3WxlMdWZmFXQS9W+OtB7CtdVCsHXJpAst2SjMSd05F3YO88ByCztI9cX4EIITOR2/W2KIR+bgT3c9dt6V7sKoVR2un5j7oUcXmvWfecMhNPU1xhjDX7zutRzHMroKbGtyTMPwlf2mssXu1qNUALgzjzzS6j6BzRIKTkhiQng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PG7Zix3X; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PG7Zix3X" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-45b9c35bc0aso13059415e9.2 for ; Wed, 03 Sep 2025 06:56:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756907804; x=1757512604; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bdN66op9i3NFpyozSjSkCRDl8+TcoAJ7grYzdeqCoIA=; b=PG7Zix3XLWyWOeBLSpOiXd6QypdNYxG3Eu4uskAN7Qo/HgNGGTVMjPSN9rMKtXsbMs aemI6LkC2vRE2vPkLlo3r4YZWX8d9DumxUEJD9RLgDtLEBNhdonigswYr4fSWHXPGWwf 0f74ZnYa8cIVEKaUZiT0IPQbcMwzmFSZo/tZS9mzffqII3j0tQoXzTd55ftEiiwPTY+e G0Ph4Eyq7gspRHAljEFCBnKNWs0qIQfAc+HYZ4iKTpwBZodM6XH806GxZxiviPdzoRVm hBcSgLhUle91aDc7Atoc95Wb7aNqPcpPIU0RHpV15qp2zFEOWW3g3ESiucuQhwaxAUQD XlFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756907804; x=1757512604; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bdN66op9i3NFpyozSjSkCRDl8+TcoAJ7grYzdeqCoIA=; b=pKSEdS6jj2zPR10swwE9XQvx+C62jVyRTjX290N75+c96aEyNdn6Z9wlW3Iaa7Ckm0 OO6wY+Jso+x5igloIZLq029YEK0unso83gNQGY9AV5olXCtX4pPBIsQnFDqUodM3MxWv MD7IvNOWePR3452dwRxfT7pJieS5ErenGM5wDucKpYd0nrJEuVaA7u9TmxxRfoP0uPSn BZIkhFe+zviXdzE2AC8XI2WpU0Y1vai78dpzlFeexp8717fd3i5ASVZq/zI/OIs3G+ws 1RDdK4m2OpnpxVZZK6dbuuBuRQi+VvJguKryEDK9OYTj9/z56wDa07aDYjQLMaPD6Ec+ CV7g== X-Gm-Message-State: AOJu0Ywr+2vi5IF8ST75Rb6Z8jgUZNX9pbIx6w3+YtgSdPjs/HTxP1XW HOWqdPVVZE3ExEJUJ2ABjNiu6qvnDxoCIBs8sqWQYfOvEHAWdZ4tjaCjYEc/m631Cqk= X-Gm-Gg: ASbGncs0erM/OHSexL8HU1h9ei8O7ogJHCEwaXUF9MZNinDaG9W7qZxc0uTVWuqPhUT uxHLXGMhZFd3WU3hq+CMgVamg3uTNVKpqtqL0KqTjDXRH2zBW6W+wMBpt4DbuKY4geqgKcOsdy8 6MAmyH2V9nPR1e+pI8yLpkUeb6fci07DYyAbNuujVcgOBHYxQd/aOn+VMbUd3M6zBaP5abwNcMT JkJzau7VGroQla9/G7r1mL+467gfF55zRrKAGKRHqJGE/PcioGXMtNhJx0vG9tuL8vwKhdGYFWC XF/VN79JVEl2PCx84bharXQGtMmlkTXb0Mnm2SPQOz8k78dzrHcXkrwCidpGTINBd5Z6dMeF+A7 BIjAc6n7AoQyLB2WeMeqleVjzIuUXdgFqYCYoLYiLjIai6gIB8Pu4Ch0I1bgXt+S3Pzyr344l/i d06g== X-Google-Smtp-Source: AGHT+IECR6paJMgzBY3Zw3h8Wf7Abdm7g6RlBanKKC46/zidpsFpNnDAQ1oCeBfUT0qxZEn5rcCT3Q== X-Received: by 2002:a05:600c:a41:b0:45b:627a:60cf with SMTP id 5b1f17b1804b1-45b8559b8edmr151397345e9.24.1756907804169; Wed, 03 Sep 2025 06:56:44 -0700 (PDT) Received: from ta2.c.googlers.com (219.43.233.35.bc.googleusercontent.com. [35.233.43.219]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b87632365sm197257135e9.16.2025.09.03.06.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 06:56:43 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 13:56:38 +0000 Subject: [PATCH v3 1/5] dt-bindings: firmware: google,gs101-acpm-ipc: add ACPM clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-clk-v3-1-65ecd42d88c7@linaro.org> References: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> In-Reply-To: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756907802; l=3056; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=ZAh+jVEjk+p7IOugFLPfvW1C8t+Wsd6E695/908UhEY=; b=LdelR0stuthQLZnXmrirVmjYcak2/o60K97PRS1iSdMsSt8ME/KFQNZUxXFvFnn3X+yQ10ki7 84Cj4pTH5pdA4SKB7iyec3ofdfwJhKl3k+3XqAq5yNxcOimpT2VF11S X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The firmware exposes clocks that can be controlled via the Alive Clock and Power Manager (ACPM) interface. Make the ACPM node a clock provider by adding the mandatory "#clock-cells" property, which allows devices to reference its clock outputs. Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring (Arm) --- .../bindings/firmware/google,gs101-acpm-ipc.yaml | 11 +++++++++ include/dt-bindings/clock/google,gs101-acpm.h | 26 ++++++++++++++++++= ++++ 2 files changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index 9785aac3b5f34955bbfe2718eec48581d050954f..d3bca6088d128485618bb2b538e= d8596b4ba14f0 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -24,6 +24,15 @@ properties: compatible: const: google,gs101-acpm-ipc =20 + "#clock-cells": + const: 1 + description: + Clocks that are variable and index based. These clocks don't provide + an entire range of values between the limits but only discrete points + within the range. The firmware also manages the voltage scaling + appropriately with the clock scaling. The argument is the ID of the + clock contained by the firmware messages. + mboxes: maxItems: 1 =20 @@ -45,6 +54,7 @@ properties: =20 required: - compatible + - "#clock-cells" - mboxes - shmem =20 @@ -56,6 +66,7 @@ examples: =20 power-management { compatible =3D "google,gs101-acpm-ipc"; + #clock-cells =3D <1>; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; =20 diff --git a/include/dt-bindings/clock/google,gs101-acpm.h b/include/dt-bin= dings/clock/google,gs101-acpm.h new file mode 100644 index 0000000000000000000000000000000000000000..e2ba89e09fa6209f7c81f554dd5= 11b2619009e5b --- /dev/null +++ b/include/dt-bindings/clock/google,gs101-acpm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025 Linaro Ltd. + * + * Device Tree binding constants for Google gs101 ACPM clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H + +#define GS101_CLK_ACPM_DVFS_MIF 0 +#define GS101_CLK_ACPM_DVFS_INT 1 +#define GS101_CLK_ACPM_DVFS_CPUCL0 2 +#define GS101_CLK_ACPM_DVFS_CPUCL1 3 +#define GS101_CLK_ACPM_DVFS_CPUCL2 4 +#define GS101_CLK_ACPM_DVFS_G3D 5 +#define GS101_CLK_ACPM_DVFS_G3DL2 6 +#define GS101_CLK_ACPM_DVFS_TPU 7 +#define GS101_CLK_ACPM_DVFS_INTCAM 8 +#define GS101_CLK_ACPM_DVFS_TNR 9 +#define GS101_CLK_ACPM_DVFS_CAM 10 +#define GS101_CLK_ACPM_DVFS_MFC 11 +#define GS101_CLK_ACPM_DVFS_DISP 12 +#define GS101_CLK_ACPM_DVFS_BO 13 + +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */ --=20 2.51.0.338.gd7d06c2dae-goog From nobody Fri Oct 3 07:49:45 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9368E30DEA0 for ; Wed, 3 Sep 2025 13:56:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907809; cv=none; b=lRIgiZO2UfapX6Yv0mxFSES/bzshyiFhLPw3iT0qxKngYPtkzpuyWvYicAMIRS3hQ5+grt1nw0Owl/R7zT/Wcu9j/wkK0kd7LfRDekM8odekb1Ccz3Bl55nUfNrg0nZ4VIp8Ooo+zVUGi4XpPQ+5v9hzYxXgrU1IMXO5Vz8Gqow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907809; c=relaxed/simple; bh=xWuaKRf4eIWvRTxRFnWQ8EPPrxM66+MS5MywdI2ONhs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HJpKSVejWQ2QLI/+ZhiXoVMN/kNq5sKl+BQ2GxI8IcylQoTuFRrQ9vkHSrLWWIhFf/SJWNbpqsr52jeFXr2Q8buaf/PkUvMXdCsPxxyh4tvlgVN3+Mn0sNAHbSwJc5cm7J6wrZvkB219crJ9JTfksLUMUe/gTlRnkh0qkPzRjqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PuCVR8gd; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PuCVR8gd" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-45b84367affso38752465e9.3 for ; Wed, 03 Sep 2025 06:56:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756907805; x=1757512605; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TEKzxyIbxVr9Lt/9n3xWbOrvTFOX3szJ8lqpps0zRyg=; b=PuCVR8gdeFKcvGa2EiZem5I2NHCJXVc3fYvWRbrq7Y/4UyFhRB80WG/896Z21CnMX2 TrzpYxfX+kCp8QJW2Y6s04FL3uiPMPULz2cswIXyPSXx/FG+qleNc1WEV6vzFWWx6Htk fuBVb/5ym0i1E4y1DehmueMe9wkHmmkdV/m6Fbts8aEBDVtuFSEXIt/dlGBO1xxxZ5Hr 4z5Uv0n0OTw8zX2+zMJ8WQaF5FQ2E6f5urs9ptZ/R0XcgsvIF4Ess3IEUtj89rZzjfjR 4cA1kvqkC+1PXPxPARxaVbB/WwQv2tTnGYoi7VPXua/H+0z4BYrm7RVDJxSJscmjZLjR L1AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756907805; x=1757512605; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TEKzxyIbxVr9Lt/9n3xWbOrvTFOX3szJ8lqpps0zRyg=; b=osJ6X3xg1/Li0IlbRuZDYXG2oVOkSxpdS5RWNRCGTszcH9Ls0GzJb280zyAvseXlBQ PBG00mmYZVFKxPL/BAywMIZV2+a/lZYWG/AH1P336Y8ySDy+syTURzPXzCDrL2NVgSIW VZI5a2JtmIA1cCceU11rH57c6d92CjjxEZzt/oxsekkn5XxJAEbOaqIi321kx0AAMkbM IDTjIYu1Gf+6gsrUoAJbt0Im/mVs59H2ub+hLDmS3E3TT6J77KnYweDEyBhcsvAj6TUd hxQybzrEn3RJcPgG8f9S8+pQAFtDzVH59PWayyxwYGY6UCfM2MoBQ83apaYXLJPIOFPS oBWg== X-Gm-Message-State: AOJu0Yw0KQ63hoQQGJoQRFhU5QbjHWmfGX45evvKGkwr1VMom6EHKwc3 BVqRVgTLaVzvS4HYLCKC+M2Sv92ZRiQBZQpyMjYEPgZzHjy1zLEVvJ+vhK1amtT8KW4= X-Gm-Gg: ASbGncuCQGDYpD+6Gyskd9vtbv2ztWKLqWTd5ly+KRb1EoZgs791FcY+Y+GuQhC37T7 6hFVi18PUJ6hCjqdE0LWP2Q53MvSwmLrzPkFa+XEKlDkLM/h85WWLwWvb5BUA3b6kcsPBNGn5y7 lM8b52r/Q16JsSdnCyrolTsSJbsuAw5jpXsQlqlxTVG+TkDlRTRq2Ok1+KxfVpc2SBq8FmtczB2 9esJURzHjJXJN/4IHFpX4SJy6Tjopf7nTevK5M4O5HBq5hwjXO7VOjWehmknOFVtbNPUTPnZkml oPFlKejf4L1CbGsPkOI9ICrbeMfhZP8IqWoMV7gK7ORWnU0Ig/xqGRB/NIWImF9ZKcealc+uBYv S02/0ZGY3sL31TUECQOxfpo2xVdyfxp4pLbSUcG0KQ6qk1UUaj9l5T2Ojj+suMWha1dInOJbOwY ghnA== X-Google-Smtp-Source: AGHT+IFO9nSz52fxYxdGQzsxxZrKol2dhW6Nm0GN+wyaiDcf/gy+3eG/jsgUY3sa/n/UJDN2fGk2Yg== X-Received: by 2002:a05:600c:314d:b0:45b:8a92:6b14 with SMTP id 5b1f17b1804b1-45b8a926f9amr119385275e9.37.1756907804887; Wed, 03 Sep 2025 06:56:44 -0700 (PDT) Received: from ta2.c.googlers.com (219.43.233.35.bc.googleusercontent.com. [35.233.43.219]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b87632365sm197257135e9.16.2025.09.03.06.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 06:56:44 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 13:56:39 +0000 Subject: [PATCH v3 2/5] firmware: exynos-acpm: add DVFS protocol Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-clk-v3-2-65ecd42d88c7@linaro.org> References: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> In-Reply-To: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756907802; l=6599; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=xWuaKRf4eIWvRTxRFnWQ8EPPrxM66+MS5MywdI2ONhs=; b=zZvkeZso8tYtXpk7gaP3vDCYLhLaul5NmQqMEO16vYvJoyZ8W6fwGy2vldN1Gw4xAEkO2psgp XUgD8F3Pm0BAhQKfgwliJv1BF+CyfbFX/P5Es0/fUxOb+Dk9urK388V X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add ACPM DVFS protocol handler. It constructs DVFS messages that the APM firmware can understand. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/Makefile | 4 +- drivers/firmware/samsung/exynos-acpm-dvfs.c | 83 ++++++++++++++++++= ++++ drivers/firmware/samsung/exynos-acpm-dvfs.h | 21 ++++++ drivers/firmware/samsung/exynos-acpm.c | 5 ++ .../linux/firmware/samsung/exynos-acpm-protocol.h | 10 +++ 5 files changed, 122 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/samsung/Makefile b/drivers/firmware/samsung/M= akefile index 7b4c9f6f34f54fd731886d97a615fe1aa97ba9a0..80d4f89b33a9558b68c9083da67= 5c70ec3d05f19 100644 --- a/drivers/firmware/samsung/Makefile +++ b/drivers/firmware/samsung/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -acpm-protocol-objs :=3D exynos-acpm.o exynos-acpm-pmic.o +acpm-protocol-objs :=3D exynos-acpm.o +acpm-protocol-objs +=3D exynos-acpm-pmic.o +acpm-protocol-objs +=3D exynos-acpm-dvfs.o obj-$(CONFIG_EXYNOS_ACPM_PROTOCOL) +=3D acpm-protocol.o diff --git a/drivers/firmware/samsung/exynos-acpm-dvfs.c b/drivers/firmware= /samsung/exynos-acpm-dvfs.c new file mode 100644 index 0000000000000000000000000000000000000000..a8763bf9374d41952a8d26124cc= 77baae0f1c723 --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-dvfs.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2025 Linaro Ltd. + */ + +#include +#include +#include +#include +#include + +#include "exynos-acpm.h" +#include "exynos-acpm-dvfs.h" + +#define ACPM_DVFS_ID GENMASK(11, 0) +#define ACPM_DVFS_REQ_TYPE GENMASK(15, 0) + +#define ACPM_DVFS_FREQ_REQ 0 +#define ACPM_DVFS_FREQ_GET 1 + +static void acpm_dvfs_set_xfer(struct acpm_xfer *xfer, u32 *cmd, size_t cm= dlen, + unsigned int acpm_chan_id, bool response) +{ + xfer->acpm_chan_id =3D acpm_chan_id; + xfer->txd =3D cmd; + xfer->txlen =3D cmdlen; + + if (response) { + xfer->rxd =3D cmd; + xfer->rxlen =3D cmdlen; + } +} + +static void acpm_dvfs_init_set_rate_cmd(u32 cmd[4], unsigned int clk_id, + unsigned long rate) +{ + cmd[0] =3D FIELD_PREP(ACPM_DVFS_ID, clk_id); + cmd[1] =3D rate / HZ_PER_KHZ; + cmd[2] =3D FIELD_PREP(ACPM_DVFS_REQ_TYPE, ACPM_DVFS_FREQ_REQ); + cmd[3] =3D ktime_to_ms(ktime_get()); +} + +int acpm_dvfs_set_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + unsigned long rate) +{ + struct acpm_xfer xfer =3D {0}; + u32 cmd[4]; + + acpm_dvfs_init_set_rate_cmd(cmd, clk_id, rate); + acpm_dvfs_set_xfer(&xfer, cmd, sizeof(cmd), acpm_chan_id, false); + + return acpm_do_xfer(handle, &xfer); +} + +static void acpm_dvfs_init_get_rate_cmd(u32 cmd[4], unsigned int clk_id, + u32 dbg_val) +{ + cmd[0] =3D FIELD_PREP(ACPM_DVFS_ID, clk_id); + cmd[1] =3D dbg_val; + cmd[2] =3D FIELD_PREP(ACPM_DVFS_REQ_TYPE, ACPM_DVFS_FREQ_GET); + cmd[3] =3D ktime_to_ms(ktime_get()); +} + +unsigned long acpm_dvfs_get_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + u32 dbg_val) +{ + struct acpm_xfer xfer; + unsigned int cmd[4]; + int ret; + + acpm_dvfs_init_get_rate_cmd(cmd, clk_id, dbg_val); + acpm_dvfs_set_xfer(&xfer, cmd, sizeof(cmd), acpm_chan_id, true); + + ret =3D acpm_do_xfer(handle, &xfer); + if (ret) + return 0; + + return xfer.rxd[1] * HZ_PER_KHZ; +} diff --git a/drivers/firmware/samsung/exynos-acpm-dvfs.h b/drivers/firmware= /samsung/exynos-acpm-dvfs.h new file mode 100644 index 0000000000000000000000000000000000000000..85a10bd535d118f2f36e9888e41= b9b705b08ea59 --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-dvfs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2025 Linaro Ltd. + */ +#ifndef __EXYNOS_ACPM_DVFS_H__ +#define __EXYNOS_ACPM_DVFS_H__ + +#include + +struct acpm_handle; + +int acpm_dvfs_set_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int id, + unsigned long rate); +unsigned long acpm_dvfs_get_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + u32 dbg_val); + +#endif /* __EXYNOS_ACPM_DVFS_H__ */ diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index 3a69fe3234c75e0b5a93cbea6bb210dc6f69d2a6..9fa0335ccf5db32892fdf09e8d4= b0a885a8f8fb5 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -29,6 +29,7 @@ #include =20 #include "exynos-acpm.h" +#include "exynos-acpm-dvfs.h" #include "exynos-acpm-pmic.h" =20 #define ACPM_PROTOCOL_SEQNUM GENMASK(21, 16) @@ -590,8 +591,12 @@ static int acpm_channels_init(struct acpm_info *acpm) */ static void acpm_setup_ops(struct acpm_info *acpm) { + struct acpm_dvfs_ops *dvfs_ops =3D &acpm->handle.ops.dvfs_ops; struct acpm_pmic_ops *pmic_ops =3D &acpm->handle.ops.pmic_ops; =20 + dvfs_ops->set_rate =3D acpm_dvfs_set_rate; + dvfs_ops->get_rate =3D acpm_dvfs_get_rate; + pmic_ops->read_reg =3D acpm_pmic_read_reg; pmic_ops->bulk_read =3D acpm_pmic_bulk_read; pmic_ops->write_reg =3D acpm_pmic_write_reg; diff --git a/include/linux/firmware/samsung/exynos-acpm-protocol.h b/includ= e/linux/firmware/samsung/exynos-acpm-protocol.h index f628bf1862c25fa018a2fe5e7e123bf05c5254b9..e41055316bb578bb8250a1b1177= f1059eeeb2611 100644 --- a/include/linux/firmware/samsung/exynos-acpm-protocol.h +++ b/include/linux/firmware/samsung/exynos-acpm-protocol.h @@ -13,6 +13,15 @@ struct acpm_handle; struct device_node; =20 +struct acpm_dvfs_ops { + int (*set_rate)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + unsigned long rate); + unsigned long (*get_rate)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, + unsigned int clk_id, u32 dbg_val); +}; + struct acpm_pmic_ops { int (*read_reg)(const struct acpm_handle *handle, unsigned int acpm_chan_id, u8 type, u8 reg, u8 chan, @@ -32,6 +41,7 @@ struct acpm_pmic_ops { }; =20 struct acpm_ops { + struct acpm_dvfs_ops dvfs_ops; struct acpm_pmic_ops pmic_ops; }; =20 --=20 2.51.0.338.gd7d06c2dae-goog From nobody Fri Oct 3 07:49:45 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BDF230E856 for ; Wed, 3 Sep 2025 13:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907810; cv=none; b=tKW9iSg+w69pUCt5YaqRD+XNwXizXBR9VB5j7cAN7w1G3vBG1q9A28Ywv8vz6mXchLXLpr+CAVG9tYurpfRbd+xxaO/GdChwh5zdTASfUFFxzIYDgOrQDQmVK7Y0LztaxDcrTKe1Z5mG31hvCkSqMQFtvYo1H31E79Pbv3+oFYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907810; c=relaxed/simple; bh=KqqXaXmMUQsdCpJZVRGT6WfJSbl5ckiI5/av635g9bs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cwylI03FRhAWi7YtUmDAr5vpiluynkngLCO1KvTZD4IjHd/ATbkiDXLz5TkcrtMA0ezV19WEFJIH8s5ebkp2fO0zi5LslMciTctbJEcsnk42ZC8hLDlB8jlZwesKJO3cm1LyoTuhrHlgYKV9Vc7XzEJJiu3Lq732CpBGucjV9UQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=I+RAaZ/c; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="I+RAaZ/c" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-45cb5e5e71eso4480805e9.2 for ; Wed, 03 Sep 2025 06:56:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756907806; x=1757512606; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2DhFOFHz0h/WoJvYuWdsxmXTZqYVyhlXjR9PRjd8hmc=; b=I+RAaZ/cGJ2RWCoNICBRenP263SZfaEyJf8gj8oPzu+iCUoAHGhM40Kl+MqfqvVFMI hRCjGBMGx+2b5Ob+a0RoqXDsb2NEaTp79mOm6Y6Qoq6t/hzhV4Mt3qxUuuAtSKnLaxP3 3n84jfB0XHmZpkj5RtdrenGJub7BLOBS5m9Mo0TPcVUhblimfpDoQs8cvoNrMJrttoIt 98ID8iK36s+yczcTrQBvkbUOihyN35tstCsHo93+myQEQvvI6kd/8B20QH1UlpWLraHA n2yAnVtdWtX4K+nZD00SvaTJGnVu6XZ+EKCUhTsDNPeweqJWxkqR5+msQyNcf7Lbx284 gXyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756907806; x=1757512606; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2DhFOFHz0h/WoJvYuWdsxmXTZqYVyhlXjR9PRjd8hmc=; b=kr9Sbj2Sk6VgvMS+sCdK3yntZmpGcO6mLhaq1Bh5riukcdZ054PuV5HTw6e2eyR2Gn 4AER+4ycFClhusj7CxbEslDgsrStlUbWjD8Kc5q8F6ZQf+u7gAFi9lJeIBnyaJiWDS5k 9gpsroAVTWjAFMaij2Kejxrynvh0bjhZKOKpuU1TqrYmko9OEqo2N49tyF01b0ES8EAe qBs4lcyI1hkScNT8KOlriEBDI07SogsNfpjmBXEePM7wRJJ8XBsrXxqCKLx8Jeh/imJy uQnvEhuxlP93hSuwmAx3ru05sS5nLRZYKGVRF0py8loBjDAf0WOGDSlSCfJrtGrqYBsj NxgA== X-Gm-Message-State: AOJu0YxTanBwohWopekexaFmQUBI/TuL7/SEKBdbsaBvgxAM15sJ/YA4 Cah3bKnBHXzgUcc0Q65bCUCxX0LP8jWd7xtXqr657O5mR+9C0taLeScY4+LXmPNLc18= X-Gm-Gg: ASbGncv4WOSmu+yHWgP8ApO0OnrHBPSVhyhPK7Jno99uVy6DIvkbdmIPJFp1F0Ulm76 hQTfr9dGE/PnqtcHLZddPXtR7yioEZgYcIdmu/zbpt3r+CcUzITfalaASMZl9sKzbqI1vVGRv3x WltNxj0kkxhCC87f8mOWbmSFUSYtNh1LtMxUNsccJmu0Scb7hbuVHrtVrtkjQtsV2LY2TPZzQb9 2ZUYEfvi+gi6yh7Nj0TSwgQlaa7y/uMfQQ3iPsMz7Ag9D9nFC1D08eDlsk2jlDvehlfk7dBP/oR TZA5ceC44WLuaEfnk/OMg8S9cxiYTh3HXiQUH8t7x/kC0WJLA4I2MrXfJ6m8ZtZHo8TP0hOy77W TLun6vg+L39d6bKhJRikICeDF/mIhd6snlCAan8QGnuMUVF5HKKTRgI01OQ5zyb4wU63maVjt1w PBHQ== X-Google-Smtp-Source: AGHT+IEyhCiL5ktj6QTvi8D22BxRnvNrT0TFR8jIAtkM1Xw+jjOyOz5Fh9eZ2GFeGHUXa5FnjJ21NQ== X-Received: by 2002:a05:600c:4f8f:b0:456:f1e:205c with SMTP id 5b1f17b1804b1-45b85550704mr128247375e9.4.1756907805637; Wed, 03 Sep 2025 06:56:45 -0700 (PDT) Received: from ta2.c.googlers.com (219.43.233.35.bc.googleusercontent.com. [35.233.43.219]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b87632365sm197257135e9.16.2025.09.03.06.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 06:56:45 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 13:56:40 +0000 Subject: [PATCH v3 3/5] clk: samsung: add Exynos ACPM clock driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-clk-v3-3-65ecd42d88c7@linaro.org> References: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> In-Reply-To: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756907802; l=7939; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=KqqXaXmMUQsdCpJZVRGT6WfJSbl5ckiI5/av635g9bs=; b=9vLkq71OeAOD3a5unJd3JpZ9FJbTx9oYJdRYUIZOTH3T3hJqpbbEK3FjNnU3NHKBBIK/QLrtM Rfj6Crt3udhCPC91VIy257mL7F5KRwj8tOrkizZRa86OzTnk2YJs4JT X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Exynos ACPM clock driver. It provides support for clocks that are controlled by firmware that implements the ACPM interface. Signed-off-by: Tudor Ambarus --- drivers/clk/samsung/Kconfig | 10 ++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-acpm.c | 203 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 214 insertions(+) diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 76a494e95027af26272e30876a87ac293bd56dfa..70a8b82a0136b4d0213d8ff95e0= 29c52436e5c7f 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -95,6 +95,16 @@ config EXYNOS_CLKOUT status of the certains clocks from SoC, but it could also be tied to other devices as an input clock. =20 +config EXYNOS_ACPM_CLK + tristate "Clock driver controlled via ACPM interface" + depends on EXYNOS_ACPM_PROTOCOL || (COMPILE_TEST && !EXYNOS_ACPM_PROTOCOL) + help + This driver provides support for clocks that are controlled by + firmware that implements the ACPM interface. + + This driver uses the ACPM interface to interact with the firmware + providing all the clock controlls. + config TESLA_FSD_COMMON_CLK bool "Tesla FSD clock controller support" if COMPILE_TEST depends on COMMON_CLK_SAMSUNG diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b77fe288e4bb484c68d1ff497acc0b83d132ea03..04b63436b12f6f5169575d74f54= b105e97bbb052 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos990.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov9.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov920.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-gs101.o +obj-$(CONFIG_EXYNOS_ACPM_CLK) +=3D clk-acpm.o obj-$(CONFIG_S3C64XX_COMMON_CLK) +=3D clk-s3c64xx.o obj-$(CONFIG_S5PV210_COMMON_CLK) +=3D clk-s5pv210.o clk-s5pv210-audss.o obj-$(CONFIG_TESLA_FSD_COMMON_CLK) +=3D clk-fsd.o diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c new file mode 100644 index 0000000000000000000000000000000000000000..fe24471c41fcaab43b62b552949= c26520b98c1e3 --- /dev/null +++ b/drivers/clk/samsung/clk-acpm.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung Exynos ACPM protocol based clock driver. + * + * Copyright 2025 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum acpm_clk_dev_type { + GS101_ACPM_CLK_ID, +}; + +struct acpm_clk { + u32 id; + struct clk_hw hw; + unsigned int mbox_chan_id; + const struct acpm_handle *handle; +}; + +struct acpm_clk_variant { + unsigned int id; + const char *name; +}; + +struct acpm_clk_driver_data { + const struct acpm_clk_variant *clks; + unsigned int nr_clks; + unsigned int mbox_chan_id; +}; + +#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw) + +#define ACPM_CLK(_id, cname) \ + { \ + .id =3D _id, \ + .name =3D cname, \ + } + +static const struct acpm_clk_variant gs101_acpm_clks[] =3D { + ACPM_CLK(GS101_CLK_ACPM_DVFS_MIF, "mif"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_INT, "int"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_CPUCL0, "cpucl0"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_CPUCL1, "cpucl1"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_CPUCL2, "cpucl2"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_G3D, "g3d"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_G3DL2, "g3dl2"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_TPU, "tpu"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_INTCAM, "intcam"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_TNR, "tnr"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_CAM, "cam"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_MFC, "mfc"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_DISP, "disp"), + ACPM_CLK(GS101_CLK_ACPM_DVFS_BO, "b0"), +}; + +static const struct acpm_clk_driver_data acpm_clk_gs101 =3D { + .clks =3D gs101_acpm_clks, + .nr_clks =3D ARRAY_SIZE(gs101_acpm_clks), + .mbox_chan_id =3D 0, +}; + +static unsigned long acpm_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct acpm_clk *clk =3D to_acpm_clk(hw); + + return clk->handle->ops.dvfs_ops.get_rate(clk->handle, + clk->mbox_chan_id, clk->id, 0); +} + +static int acpm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + /* + * We can't figure out what rate it will be, so just return the + * rate back to the caller. acpm_clk_recalc_rate() will be called + * after the rate is set and we'll know what rate the clock is + * running at then. + */ + return 0; +} + +static int acpm_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct acpm_clk *clk =3D to_acpm_clk(hw); + + return clk->handle->ops.dvfs_ops.set_rate(clk->handle, + clk->mbox_chan_id, clk->id, rate); +} + +static const struct clk_ops acpm_clk_ops =3D { + .recalc_rate =3D acpm_clk_recalc_rate, + .determine_rate =3D acpm_clk_determine_rate, + .set_rate =3D acpm_clk_set_rate, +}; + +static int acpm_clk_ops_init(struct device *dev, struct acpm_clk *aclk, + const char *name) +{ + struct clk_init_data init =3D {}; + + init.name =3D name; + init.ops =3D &acpm_clk_ops; + aclk->hw.init =3D &init; + + return devm_clk_hw_register(dev, &aclk->hw); +} + +static int acpm_clk_probe(struct platform_device *pdev) +{ + enum acpm_clk_dev_type type =3D platform_get_device_id(pdev)->driver_data; + const struct acpm_clk_driver_data *drv_data; + const struct acpm_handle *acpm_handle; + struct clk_hw_onecell_data *clk_data; + struct clk_hw **hws; + struct device *dev =3D &pdev->dev; + struct acpm_clk *aclks; + unsigned int mbox_chan_id; + int i, err, count; + + switch (type) { + case GS101_ACPM_CLK_ID: + drv_data =3D &acpm_clk_gs101; + break; + default: + return dev_err_probe(dev, -EINVAL, "Invalid device type\n"); + } + + acpm_handle =3D devm_acpm_get_by_node(dev, dev->parent->of_node); + if (IS_ERR(acpm_handle)) + return dev_err_probe(dev, PTR_ERR(acpm_handle), + "Failed to get acpm handle.\n"); + + count =3D drv_data->nr_clks; + mbox_chan_id =3D drv_data->mbox_chan_id; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, count), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num =3D count; + hws =3D clk_data->hws; + + aclks =3D devm_kcalloc(dev, count, sizeof(*aclks), GFP_KERNEL); + if (!aclks) + return -ENOMEM; + + for (i =3D 0; i < count; i++) { + const struct acpm_clk_variant *variant =3D &drv_data->clks[i]; + unsigned int id =3D variant->id; + struct acpm_clk *aclk; + + if (id >=3D count) + return dev_err_probe(dev, -EINVAL, + "Invalid ACPM clock ID.\n"); + + aclk =3D &aclks[id]; + aclk->id =3D id; + aclk->handle =3D acpm_handle; + aclk->mbox_chan_id =3D mbox_chan_id; + + hws[id] =3D &aclk->hw; + + err =3D acpm_clk_ops_init(dev, aclk, variant->name); + if (err) + return dev_err_probe(dev, err, + "Failed to register clock.\n"); + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data); +} + +static const struct platform_device_id acpm_clk_id[] =3D { + { "gs101-acpm-clk", GS101_ACPM_CLK_ID }, + {}, +}; +MODULE_DEVICE_TABLE(platform, acpm_clk_id); + +static struct platform_driver acpm_clk_driver =3D { + .driver =3D { + .name =3D "acpm-clocks", + }, + .probe =3D acpm_clk_probe, + .id_table =3D acpm_clk_id, +}; +module_platform_driver(acpm_clk_driver); + +MODULE_AUTHOR("Tudor Ambarus "); +MODULE_DESCRIPTION("Samsung Exynos ACPM clock driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0.338.gd7d06c2dae-goog From nobody Fri Oct 3 07:49:45 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6510930EF7A for ; Wed, 3 Sep 2025 13:56:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907811; cv=none; b=CsFPPrUeVyJDCJKBp0KkyCZp4UOvdDjEjI2MY3CqoKQqEXS2H0xjOclq2/1duliKC8WXkMXcyK7Rb6rx0UQMhyahWXRq18JA+1DyNjZTJHICPe2tcHsMrPBSAoOM1mzJA+D7QAgbUfNg4rRtBWaIoJ4Z2wjbc2kiCJKo7DdL3Pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907811; c=relaxed/simple; bh=dz7gQjCygFQTHCpzStxcsEQEHazG0z97bLLdbPJU1cI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ieI9Bbp6068w477uKZiEjfCFgmTpcycwV3htYIQMvXSX9YXvrsnXCsgTlrGq676QctNT1DWZrofZeY82GN4u9vNVTWlUpm0M5HZko1XuQdq1ZmCwCA57itxijhC0gNDxPZKAH2lDBhGZy6MDBxRxa04+E4Afj7sTjTCZ2BLDNbo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GbCt9QwN; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GbCt9QwN" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-45b7c56a987so23382835e9.1 for ; Wed, 03 Sep 2025 06:56:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756907806; x=1757512606; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UYuv3IrS7IPuMyikGmW/lennhceiqK2zrsQcCIyLu+Y=; b=GbCt9QwNqPh1zBRtVaheAtuNrRo8B1bIuw+9aZo28tskobvempbkFwJkVGCRPEyroz +4d2YeOut4IztKqcjFgBovxJfTm8yzEUnS7F1peemX2iFNGEzCI7vbtjUcTJncZVeW5D yKpKbcbDxf+3IYsrIxmwXM8Q2z3UxO3ycd2jSjVfHq/P0QaDTHIfkqycBxkFfv6ws1Be XDrOr0LD0El8ja5BvNH3Q1Ld24WknaLtFVuxxO0uIlSL0QKevog97dBEQpkCwAuPO8i7 HXHvM1huNXkcSpDfwLfD/EgE0vA3xsplKDheXK74XR13PjFm9Tonv9TKKQgbaAxUsduF Xazg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756907806; x=1757512606; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UYuv3IrS7IPuMyikGmW/lennhceiqK2zrsQcCIyLu+Y=; b=EGT//pJI3SCL+tPTxLrn7YSoymAWFHv1l1nexWaxUeETBYKtd6Laugfz5WRERRH7ss Zsl7gj36UfOdjPvB6rrKqfY7OwjGir0y63HoDmYWTkeGvWb4cwg2zNRrGeQCLzqDGg2i YQAsBjqcLGCAHdzu37epYy87Hn/jfqiIwfWU4yxBwAsP6RPK4XfJCnTt/fEQtlVRIs8E 7gg9P4Uri5o5k/3t7WB1yASr2boKFZZ408Z3nONUkYU3Lhk2ktZjONCvmDV3oR71E3/T oB6XkmJevmoB4THbyG0KRLRemxt6UAycV/2rz/TfVYJOJ2z7vF3ZhqIvVfKQovPdSABE 22VQ== X-Gm-Message-State: AOJu0Yzqrhqg/RtiEMAIITt8QtL//vMpCzezbrtSr7YNKAU5+6mcg2F3 vDnM15P6ES4ODyyyt3HP+BkDYl5azZ/BQ/3Cw+IoxQEn4U9bPUfed4RGkNtjiS7/Hi4= X-Gm-Gg: ASbGncubW5tBytK1V2pTuG1ryDMk0WC3kH9DRNoWvXwdarIdt0m6SSlNBcVdi/w2KbP rKlzWGJEF0WmOElQ5Lxsekx7fnn2oHvA4/+GjTOqwIEUHNZiXMyHOFdN9sfUAQ19z7WzKNlMRRn qiClZgpFf8YplY98tB95koOPgGQAQrm5zQEJebJ03Gbo4NGhD+FcC5Jf0y/t9yPcS2mW+Ndf0Nh +xsy2H/29HOKZvL3O+o/nZyWGGfePwHvw+1QXEiTwFiEFM1zPbQjDjh/dLozRbplqZT1cLBJUu9 a1vUm56mIb1SeMYt0+I5XAbDOAjC2z30rzsO1XPWD6/df/I9MqCkicU6WztJESQQEI5cZuy2qHP 0/sKSbHMGOWTGL0PfEOYWa2jhbWtyf3AxHbqH4Q5qcb/+lX9Md/XzWmUNibJ4/b+qPvE47OeWoJ rishCFyGnfHTcARpliurv+EHM= X-Google-Smtp-Source: AGHT+IHYANMgRYGXdNHs2QyGL8QnX2/Tp8baR9s93U+KQIcT5D6VPk22Vpiz9HHftpfRlLtqh7LR+Q== X-Received: by 2002:a05:600c:358c:b0:45b:9a3b:34aa with SMTP id 5b1f17b1804b1-45b9a3b36d5mr60145985e9.16.1756907806344; Wed, 03 Sep 2025 06:56:46 -0700 (PDT) Received: from ta2.c.googlers.com (219.43.233.35.bc.googleusercontent.com. [35.233.43.219]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b87632365sm197257135e9.16.2025.09.03.06.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 06:56:45 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 13:56:41 +0000 Subject: [PATCH v3 4/5] firmware: exynos-acpm: register ACPM clocks pdev Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-clk-v3-4-65ecd42d88c7@linaro.org> References: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> In-Reply-To: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756907802; l=2606; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=dz7gQjCygFQTHCpzStxcsEQEHazG0z97bLLdbPJU1cI=; b=LnTHfH04YTaRtLtGrKsu0l2tPiCHi5kfhymeOk52FGnp5MzLrMabP6gJe0V4GjgInvVmxXtUf XE+PInRBnXoA2tDMR/QaB3Bf4NEDZH1HPg1Gifx67K5mHfQZQODjRKi X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Register by hand a platform device for the ACPM clocks. The ACPM clocks are not modeled as a DT child of ACPM because: 1/ they don't have their own resources. 2/ they are not a block that can be reused. The clock identifying data is reduced (clock ID, clock name and mailbox channel ID) and may differ from a SoC to another. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/exynos-acpm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index 9fa0335ccf5db32892fdf09e8d4b0a885a8f8fb5..0cb269c7046015d4c5fe5731ba0= d61d48dcaeee1 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -177,9 +177,11 @@ struct acpm_info { /** * struct acpm_match_data - of_device_id data. * @initdata_base: offset in SRAM where the channels configuration resides. + * @acpm_clk_dev_name: base name for the ACPM clocks device that we're reg= istering. */ struct acpm_match_data { loff_t initdata_base; + const char *acpm_clk_dev_name; }; =20 #define client_to_acpm_chan(c) container_of(c, struct acpm_chan, cl) @@ -604,9 +606,15 @@ static void acpm_setup_ops(struct acpm_info *acpm) pmic_ops->update_reg =3D acpm_pmic_update_reg; } =20 +static void acpm_clk_pdev_unregister(void *data) +{ + platform_device_unregister(data); +} + static int acpm_probe(struct platform_device *pdev) { const struct acpm_match_data *match_data; + struct platform_device *acpm_clk_pdev; struct device *dev =3D &pdev->dev; struct device_node *shmem; struct acpm_info *acpm; @@ -647,6 +655,18 @@ static int acpm_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, acpm); =20 + acpm_clk_pdev =3D platform_device_register_data(dev, + match_data->acpm_clk_dev_name, + PLATFORM_DEVID_NONE, NULL, 0); + if (IS_ERR(acpm_clk_pdev)) + return dev_err_probe(dev, PTR_ERR(acpm_clk_pdev), + "Failed to register ACPM clocks device.\n"); + + ret =3D devm_add_action_or_reset(dev, acpm_clk_pdev_unregister, + acpm_clk_pdev); + if (ret) + return dev_err_probe(dev, ret, "Failed to add devm action.\n"); + return devm_of_platform_populate(dev); } =20 @@ -746,6 +766,7 @@ EXPORT_SYMBOL_GPL(devm_acpm_get_by_node); =20 static const struct acpm_match_data acpm_gs101 =3D { .initdata_base =3D ACPM_GS101_INITDATA_BASE, + .acpm_clk_dev_name =3D "gs101-acpm-clk", }; =20 static const struct of_device_id acpm_match[] =3D { --=20 2.51.0.338.gd7d06c2dae-goog From nobody Fri Oct 3 07:49:45 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3242530F557 for ; Wed, 3 Sep 2025 13:56:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907813; cv=none; b=O6qNg/nNQ60bcFhNTDm5cg1gvv7WRA3aGTmmySSmUQBY617NtvVry09aZEF9tBYy+FtEB9FxCqAMcpTblkI641s/L5OywPAoGLcICbHpIHYG36WyWYeCp+s5ZpKJHYJLz4qXVepvjHRa3uYaz8LwNCArJDXpVzWJZCWdqe3UpYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756907813; c=relaxed/simple; bh=jmSGd1LEiJi/OzRrbMT0IdOTY/EPAZZsAFW195MpqOM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jVeKbrAlKIubhCPFYAMIXl/fMQzt7aHhKaMleBis33SCoQ6K8dQbsXjHVDADQLyoAR536Ayukdpi9nGMb8w0FmuE/ORrxdW7AG6FiiJoIV4mZyuO53m50Apurz7Fu72VfXfSqIsAtMC6Qhe7XCGmgwJv2SY2aKzfO/eHaUP9IQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Gu3DBpJq; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Gu3DBpJq" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-45cb5492350so6223595e9.1 for ; Wed, 03 Sep 2025 06:56:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756907807; x=1757512607; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=knWYmZlS1tcNLIvNHwra67g63fbf9sRjO2H/UvMZ5D0=; b=Gu3DBpJqJIkDwXMJR+3BFOmT1ZwdlnBG+T5WxgqkanYALyWEifLQkMzZi6F92t4ZfN ugfWuT0KOUvLTz1emDszCCsgZcBwobQ+9OIFBBNq0H5oNHN2s+Owhv0m48HDreG3EYUb uxtoDd8djgQi6RZ3x0gCToLphTDMSwq6Hw0CxpuczLMmwpjqzJ8uO559eKufYAsSRLQK 3hows0RUQUf8chR33mbXPqyzDCkfvX6eLnMaj/oIWkFbhcoC5CxR0NUM66x85+EfRbbT zE3J0TdW48iTGmCQ22lIshOkSqy6GOOfrdbmwoHsahoctH2Vl4wDHrSt8arJnVHeJSDR HBbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756907807; x=1757512607; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=knWYmZlS1tcNLIvNHwra67g63fbf9sRjO2H/UvMZ5D0=; b=Ts8ZNk4/ON1UteI3jfiV9ruHWOlODcnN8pmQnury4YZbeyhffDlqRfgxOB8TP0fC0W UTQTnLu7nI1PhXNy7yAVpc77c8TzTdqwjz+MsC+yM14a2QKxkIK8fwGnCqM5HiPz3jmM yb1j0v4ozINMlC+kCIZbjHzigCgsCDBxwiau3nWBwf8kO+Wnp3nH7EWxEKaMW+3vV0Fh +SogJSkyYXShDUT/nQYTyjMoIxSbnvCSU/GF8pN3J2ZHcEhrSIJgLBnu6oDhNdlyg/Ti 7l/QkQGxXQTk/DGRvWHT9sEi8QcdaRKG9u/MWdoEex817ODGc2Cd0cJoujPhS8R1t3gd +3vg== X-Gm-Message-State: AOJu0YzP4rArX16bY/ZyY+65HXSBk/hCuI1CYTqu3BIlaqiBfrws3KzJ WevbDIBqbk7NoKH8tDjVZR13L7BhEbPtlYpq4fF389UC92/yp2RyVA71z84282VfsVM= X-Gm-Gg: ASbGncsu3jxQvEEqpnU9UzKIE5YlNvOT9ISH5iAtaKZFRI3bi/vdYObO6bFOOHeD8sN Kpcj+GqG72mx+HN+7nhh0iXQ8IeIYNp0pBHsd7I9Xe1Tb0aDcljdnUfR/SbyY9euTWHAwWrqI9v 5+Tr0sXWFcpEZJH673t8Opa/6YJmux7GuKI/pvbOWbx/j/F7+wA2JPhF+la53jQyCC9P4socYeS KBtZ/kwunz6orj8UECRz4kwbeT9Ewt6Ufd8AtNbJwxGqFvub7Ufjg3/HNXNkshshqW+EW88EFGL UnCtyQEtD0dB9Y2gbBrLKr/M/l5wxRwFBYWxK4o6SIx9SUH/gC9O2QosP+if69GZSUqNz3GECyi DR4G46XFEigOAKPHqYqyddfwGDdiT236Sb+Or7jYpHCTElpOKaHppuHMURWnhhpVcw2UhKidOqr py1bupcNAbA78I X-Google-Smtp-Source: AGHT+IEEbe9zmys+SdHs+R+yvKPrY3H8cKyU1UJgBhivbEglt1LnfQ35e5S95bN5Q3yU4Jw1QrwtWA== X-Received: by 2002:a05:600c:5253:b0:45d:98be:ee91 with SMTP id 5b1f17b1804b1-45d98bef030mr1077085e9.9.1756907807066; Wed, 03 Sep 2025 06:56:47 -0700 (PDT) Received: from ta2.c.googlers.com (219.43.233.35.bc.googleusercontent.com. [35.233.43.219]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b87632365sm197257135e9.16.2025.09.03.06.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Sep 2025 06:56:46 -0700 (PDT) From: Tudor Ambarus Date: Wed, 03 Sep 2025 13:56:42 +0000 Subject: [PATCH v3 5/5] arm64: defconfig: enable Exynos ACPM clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250903-acpm-clk-v3-5-65ecd42d88c7@linaro.org> References: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> In-Reply-To: <20250903-acpm-clk-v3-0-65ecd42d88c7@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756907802; l=820; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=jmSGd1LEiJi/OzRrbMT0IdOTY/EPAZZsAFW195MpqOM=; b=uHbQ7xT3bV6lIp0HqgAN0MLCg6QtXHzra5fcYf5Lk5NwyHh5UfcdGdrFyQvIdgzD6dfszLV11 AJJjST6HJPrAxYtlucE/6MSFIODMgces/93QGOxMCFOl2jtohAP2doq X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Enable the Exynos ACPM clocks driver. Samsung Exynos platforms implement ACPM to provide support for clock configuration, PMIC and temperature sensors. Signed-off-by: Tudor Ambarus --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366cd12ae212a1d107660afe8be6c5ef..4255bc885545fb3bb7e9cf02760= cac35bf2872fa 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1445,6 +1445,7 @@ CONFIG_CLK_GFM_LPASS_SM8250=3Dm CONFIG_SM_VIDEOCC_8450=3Dm CONFIG_CLK_RCAR_USB2_CLOCK_SEL=3Dy CONFIG_CLK_RENESAS_VBATTB=3Dm +CONFIG_EXYNOS_ACPM_CLK=3Dm CONFIG_CLK_SOPHGO_CV1800=3Dy CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_OMAP=3Dm --=20 2.51.0.338.gd7d06c2dae-goog