From nobody Fri Oct 3 12:26:44 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 055132E8DE7; Tue, 2 Sep 2025 07:56:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756799809; cv=none; b=J96IaouMSWeIzdyJE/XKD3sKuM8fm6Bl5vZqduFsKm8lUh6DpMV0opqdO1BF6pyN9j+LG/fCL3x+cCNrLRvu/gxrebdMB66CEyio3aalChzhds6bozZFIYtplP4zOJQUE+kMFITRqdw2r7egBrTrgGD9uuz6Bf8D0AhzQCeZvBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756799809; c=relaxed/simple; bh=gpnfdQEv0xVyAvn+ZbbbXsS8YDrJU/mvq+vj/xwMpBg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ft9GHDZoHajlzVtOmBPhIguLrPrGWUHrMWjDP+NHyCjQzi9+qPwCY085B1N+fiGl5gVrG83ZIKphCDBm7dRf4N8AMeJfaVcysyCxTKUjSrGE/vIJLABrPdbd6gHS80uTpmHXsrFgrUx9XiOt+nL0WqkXfJMmwAGn/sVLlBqtJtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PlC9HWcA; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PlC9HWcA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1756799807; x=1788335807; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gpnfdQEv0xVyAvn+ZbbbXsS8YDrJU/mvq+vj/xwMpBg=; b=PlC9HWcAEdDCDGwAxr+Ne8vxVrsh1XNt3Bg0TjDR3PfbC+eMc1DbnqOM wNkRH8mqyUPZU+gU5NxjdEpPmFJmpEh3t5//9Yh6vGyvLn+e8zcJWdgtB NmIFNokGZMoz97UlqL2xshdY/TBSKZK9mmWhAfNqHk01YygCYbGzhi0dG vTQKcN8L9ETQ5u8Ipt4grmwz5zPsiWY0qDWmOPSuNSA8TCmPzNTCczepe UuZmgBQtduep3yo4G3csPkt/eBTGoJwjPhWulxy+58AzMLZ3kZ8xK5mJG V1OciwRPweA20BoBll3RmrQnZHFqukSCROr08L9LABd04ysXIJ1CqcRwM w==; X-CSE-ConnectionGUID: I0e7JmeXSliqGe+ljgjh1Q== X-CSE-MsgGUID: 8c8O9HLSSmiAP/O4KF8OBg== X-IronPort-AV: E=Sophos;i="6.18,230,1751266800"; d="scan'208";a="45916748" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2025 00:56:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 2 Sep 2025 00:56:16 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 2 Sep 2025 00:56:14 -0700 From: Valentina Fernandez To: , , , , , , , , CC: , , Subject: [PATCH v2 3/5] riscv: dts: microchip: add icicle kit with production device Date: Tue, 2 Sep 2025 08:55:46 +0100 Message-ID: <20250902075548.1967613-4-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250902075548.1967613-1-valentina.fernandezalanis@microchip.com> References: <20250902075548.1967613-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sample (-es) variant. Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata. Add a new device tree (mpfs-icicle-kit-prod.dts) for the production board which includes the icicle kit common dtsi and enable the system controller SPI flash, which is only accessible on production silicon. Remove redundant board compatible from fabric dtsi and update board compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP cluster communication. Fix formatting by using lowecase hex everywhere and remove reduntant status properties from common dtsi. Signed-off-by: Valentina Fernandez --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-icicle-kit-common.dtsi | 10 ++++---- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 23 ++++++++++++++++--- .../dts/microchip/mpfs-icicle-kit-prod.dts | 23 +++++++++++++++++++ .../boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 5 files changed, 52 insertions(+), 8 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index f51aeeb9fd3b..1e2f4e41bf0d 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-beaglev-fire.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit-prod.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index eafea3b69cd7..e01a216e6c3a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -53,13 +53,11 @@ led-4 { ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x40000000>; - status =3D "okay"; }; =20 ddrc_cache_hi: memory@1040000000 { device_type =3D "memory"; reg =3D <0x10 0x40000000 0x0 0x40000000>; - status =3D "okay"; }; =20 reserved-memory { @@ -67,8 +65,8 @@ reserved-memory { #size-cells =3D <2>; ranges; =20 - hss_payload: region@BFC00000 { - reg =3D <0x0 0xBFC00000 0x0 0x400000>; + hss_payload: region@bfc00000 { + reg =3D <0x0 0xbfc00000 0x0 0x400000>; no-map; }; }; @@ -134,6 +132,10 @@ &i2c2 { status =3D "okay"; }; =20 +&ihc { + status =3D "okay"; +}; + &mac0 { phy-mode =3D "sgmii"; phy-handle =3D <&phy0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a6dda55a2d1d..e673b676fd1a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,9 +2,6 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { - compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", - "microchip,mpfs"; - core_pwm0: pwm@40000000 { compatible =3D "microchip,corepwm-rtl-v4"; reg =3D <0x0 0x40000000 0x0 0xF0>; @@ -26,6 +23,26 @@ i2c2: i2c@40000200 { status =3D "disabled"; }; =20 + ihc: mailbox { + compatible =3D "microchip,sbi-ipc"; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + status =3D "disabled"; + }; + + mailbox@50000000 { + compatible =3D "microchip,miv-ihc-rtl-v2"; + reg =3D <0x0 0x50000000 0x0 0x1c000>; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + microchip,ihc-chan-disabled-mask =3D /bits/ 16 <0>; + status =3D "disabled"; + }; + pcie: pcie@3000000000 { compatible =3D "microchip,pcie-host-1.0"; #address-cells =3D <0x3>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/= riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts new file mode 100644 index 000000000000..8afedece89d1 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs-icicle-kit-common.dtsi" + +/ { + model =3D "Microchip PolarFire-SoC Icicle Kit (Production Silicon)"; + compatible =3D "microchip,mpfs-icicle-prod-reference-rtl-v2507", + "microchip,mpfs-icicle-kit-prod", + "microchip,mpfs-icicle-kit", + "microchip,mpfs-prod", + "microchip,mpfs"; +}; + +&syscontroller { + microchip,bitstream-flash =3D <&sys_ctrl_flash>; +}; + +&syscontroller_qspi { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index 2cb08ed0946d..556aa9638282 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -7,6 +7,7 @@ =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; - compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", + compatible =3D "microchip,mpfs-icicle-es-reference-rtl-v2507", + "microchip,mpfs-icicle-kit", "microchip,mpfs"; }; --=20 2.34.1