From nobody Fri Oct 3 12:25:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 556102E7180; Tue, 2 Sep 2025 07:19:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797582; cv=none; b=W42n7KxqL0t0BbxdQ8CFFC/mdY/qZFziOmQDx3lW0bcLMuLj7f1IPVBvIyz+Cp3aXyLJTIyWwRT40zwrZPdqaXehlC2epvrjV9YgYc+pyY5/WzMIvsDjmFyNQrfWt7jSL9YpaPh/BibZJoZmYThMJMQkc1n+uW7JE8WE8zDp4Vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797582; c=relaxed/simple; bh=71lglGxuOWL9Yi+GIcehsj1VlOid4Gy/cvvr3555cVY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n89nDOObYoDO8uxPLvHw03P9mmLlr3+9sWfms86CpthKbtlUSLO4S/MufREmDn0UFaU9uHv5v5dJraKThFJqXy2SNWVoGrDQSGB89NudcKkyzbC3IC8sxiJ41PCTKa1PHMOH+FwzGTC8hocNzbtUARulPLnQCeVAOf6beDNUqmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=qVRBgPx1; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="qVRBgPx1" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5827Jb7D2930065; Tue, 2 Sep 2025 02:19:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756797577; bh=o+4OtCx4GxNSex+BozEe4lgeh/M/Nkp/nn2gcdmM83E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qVRBgPx1cCR6+vDE80TCsgOVaV3zUko95lJxN6dLPR6OAgs7NKKzTSEXKIZQSw0A3 2pc0UWVdorJvOWMQXuV//pRTH2bjfAhinMWdzMSpHB2/yhYJgyunfvEeDa56QrAmBt 7ag2eajALuF5kEKz1yHrSWS4HqNSXcD3+1/VadJU= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5827Jb4r2558628 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 2 Sep 2025 02:19:37 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 2 Sep 2025 02:19:36 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 2 Sep 2025 02:19:36 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5827JJgb3689199; Tue, 2 Sep 2025 02:19:32 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v3 2/3] arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS Date: Tue, 2 Sep 2025 12:49:16 +0530 Message-ID: <20250902071917.1616729-3-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250902071917.1616729-1-a-kaur@ti.com> References: <20250902071917.1616729-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. But, in order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 527f884d2d94981016e181dcbd4c4b5bf597c0ad. Signed-off-by: Akashdeep Kaur Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..d3bed23134ca 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -249,7 +249,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_= TX_CTL */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1