From nobody Fri Oct 3 12:25:35 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB06A3398A; Tue, 2 Sep 2025 07:19:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797581; cv=none; b=Y4kyyyQ5CmAbMbwUse4FYRKMIfJtojSHTYcqKLtrfik1z9Lidwwwqgc6VI8/43T6GkgzGyxGtOCX6dRbonovSIES7RhXg0hbz0twZtYg2tEOruc51rAkz1f4wJzkw03OZeECHphpwcz71qXZ0uHeMPFkmSwu1z0vteP8MOZORIU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797581; c=relaxed/simple; bh=m7TLK/OWjSqKS8h6CEhb12Sj26ZqslWc10VvzBnLzpw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kCr1oJl+BdK54I1Zb6KYULfNGKh0Fk5QuvaG4qukexILK4eQIeyoeqlHQOaE1xrMT+Q+tzMpAoy0LbsEEBOLKO82KKGP2V2W+mnXDbgeJbXfSzHzOpmKT8qjutF89r7BNKklz44jFdJG+tmvpsS6apphUtHzJiRGUSlgTPX5Kgo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=X90EOp6K; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="X90EOp6K" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5827JVYg2930057; Tue, 2 Sep 2025 02:19:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756797571; bh=RKHmaMqAlKNoVFPe+uzx7ydmqDUhBWUhyYaETomDZac=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X90EOp6Kpqu+8V72oBs2A+ZIlZPJdsXmCB3xUSXoeIotbXOvYKyTsVJ7zAPbu5+53 v05Sr44IIdFTLGl04AgnHFMKI0jiFQND455xnAeaUkUvM6XzZUkepmo9TITMdUzgVp HwX0Ot8zYJgjAjhH+gBAYPuKnf9BAowIAYBWjln0= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5827JVMY2558558 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 2 Sep 2025 02:19:31 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 2 Sep 2025 02:19:31 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 2 Sep 2025 02:19:31 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5827JJga3689199; Tue, 2 Sep 2025 02:19:27 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v3 1/3] arm64: dts: ti: k3-am62p5-sk: Remove the unused cfg in USB1_DRVVBUS Date: Tue, 2 Sep 2025 12:49:15 +0530 Message-ID: <20250902071917.1616729-2-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250902071917.1616729-1-a-kaur@ti.com> References: <20250902071917.1616729-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. But, in order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 115290c112952db27009668aa7ae2f29920704f0. Signed-off-by: Akashdeep Kaur Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 899da7896563..e8f0ac2c55e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -360,7 +360,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACL= KR.UART1_TXD */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1