From nobody Fri Oct 3 11:22:56 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB06A3398A; Tue, 2 Sep 2025 07:19:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797581; cv=none; b=Y4kyyyQ5CmAbMbwUse4FYRKMIfJtojSHTYcqKLtrfik1z9Lidwwwqgc6VI8/43T6GkgzGyxGtOCX6dRbonovSIES7RhXg0hbz0twZtYg2tEOruc51rAkz1f4wJzkw03OZeECHphpwcz71qXZ0uHeMPFkmSwu1z0vteP8MOZORIU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797581; c=relaxed/simple; bh=m7TLK/OWjSqKS8h6CEhb12Sj26ZqslWc10VvzBnLzpw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kCr1oJl+BdK54I1Zb6KYULfNGKh0Fk5QuvaG4qukexILK4eQIeyoeqlHQOaE1xrMT+Q+tzMpAoy0LbsEEBOLKO82KKGP2V2W+mnXDbgeJbXfSzHzOpmKT8qjutF89r7BNKklz44jFdJG+tmvpsS6apphUtHzJiRGUSlgTPX5Kgo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=X90EOp6K; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="X90EOp6K" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5827JVYg2930057; Tue, 2 Sep 2025 02:19:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756797571; bh=RKHmaMqAlKNoVFPe+uzx7ydmqDUhBWUhyYaETomDZac=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X90EOp6Kpqu+8V72oBs2A+ZIlZPJdsXmCB3xUSXoeIotbXOvYKyTsVJ7zAPbu5+53 v05Sr44IIdFTLGl04AgnHFMKI0jiFQND455xnAeaUkUvM6XzZUkepmo9TITMdUzgVp HwX0Ot8zYJgjAjhH+gBAYPuKnf9BAowIAYBWjln0= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5827JVMY2558558 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 2 Sep 2025 02:19:31 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 2 Sep 2025 02:19:31 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 2 Sep 2025 02:19:31 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5827JJga3689199; Tue, 2 Sep 2025 02:19:27 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v3 1/3] arm64: dts: ti: k3-am62p5-sk: Remove the unused cfg in USB1_DRVVBUS Date: Tue, 2 Sep 2025 12:49:15 +0530 Message-ID: <20250902071917.1616729-2-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250902071917.1616729-1-a-kaur@ti.com> References: <20250902071917.1616729-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. But, in order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 115290c112952db27009668aa7ae2f29920704f0. Signed-off-by: Akashdeep Kaur Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 899da7896563..e8f0ac2c55e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -360,7 +360,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACL= KR.UART1_TXD */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1 From nobody Fri Oct 3 11:22:56 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 556102E7180; Tue, 2 Sep 2025 07:19:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797582; cv=none; b=W42n7KxqL0t0BbxdQ8CFFC/mdY/qZFziOmQDx3lW0bcLMuLj7f1IPVBvIyz+Cp3aXyLJTIyWwRT40zwrZPdqaXehlC2epvrjV9YgYc+pyY5/WzMIvsDjmFyNQrfWt7jSL9YpaPh/BibZJoZmYThMJMQkc1n+uW7JE8WE8zDp4Vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797582; c=relaxed/simple; bh=71lglGxuOWL9Yi+GIcehsj1VlOid4Gy/cvvr3555cVY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n89nDOObYoDO8uxPLvHw03P9mmLlr3+9sWfms86CpthKbtlUSLO4S/MufREmDn0UFaU9uHv5v5dJraKThFJqXy2SNWVoGrDQSGB89NudcKkyzbC3IC8sxiJ41PCTKa1PHMOH+FwzGTC8hocNzbtUARulPLnQCeVAOf6beDNUqmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=qVRBgPx1; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="qVRBgPx1" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5827Jb7D2930065; Tue, 2 Sep 2025 02:19:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756797577; bh=o+4OtCx4GxNSex+BozEe4lgeh/M/Nkp/nn2gcdmM83E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qVRBgPx1cCR6+vDE80TCsgOVaV3zUko95lJxN6dLPR6OAgs7NKKzTSEXKIZQSw0A3 2pc0UWVdorJvOWMQXuV//pRTH2bjfAhinMWdzMSpHB2/yhYJgyunfvEeDa56QrAmBt 7ag2eajALuF5kEKz1yHrSWS4HqNSXcD3+1/VadJU= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5827Jb4r2558628 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 2 Sep 2025 02:19:37 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 2 Sep 2025 02:19:36 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 2 Sep 2025 02:19:36 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5827JJgb3689199; Tue, 2 Sep 2025 02:19:32 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v3 2/3] arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS Date: Tue, 2 Sep 2025 12:49:16 +0530 Message-ID: <20250902071917.1616729-3-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250902071917.1616729-1-a-kaur@ti.com> References: <20250902071917.1616729-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. But, in order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 527f884d2d94981016e181dcbd4c4b5bf597c0ad. Signed-off-by: Akashdeep Kaur Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..d3bed23134ca 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -249,7 +249,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_= TX_CTL */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1 From nobody Fri Oct 3 11:22:56 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC0FE257845; Tue, 2 Sep 2025 07:19:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797589; cv=none; b=kMt3Y+m5qLMdj1JkjN6r22b3pf82e/C+rb2bBOekBTEgO7ZJQhA4+jNWV0LiTtnp91eI16++rcWzt6Bb11q5+Um+OR0jUBOWptlJdzjRC5juR1ObRM00MMUworFmPcSqolsBlK7Rvh9NThyoPjWd3ZjfAvJOqJ8sH5LHZP4/fSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756797589; c=relaxed/simple; bh=SY0nQqXivc4wOy/GprU6dZd+jT6rz1VGOyEA24OCT7A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DdL9ydhJk3k2Dw4vZaUEC1W96ZaPlRoEwq/tpsjQcC/MRAa57hahzY9MD31o1el75Qf6VtAX7Gl8xPkjSS05SbDCuBnn0hOWZl6Fo9ULslRid4SE2bL04Y5Y/Pn8SQqDC2JuUC23tpPirMXNIWjL+EPOF7puDlFdooROS6kf5/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=a2vQx0uV; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="a2vQx0uV" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5827Jg4J2532686; Tue, 2 Sep 2025 02:19:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756797582; bh=7t+V3rIC4kUf8NGXC8DKjChwyGbywQXM1PSJFpDs4Zs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=a2vQx0uVqx1UXgu4bbYmLW+wQ/7XS5W5Tm/uxJ6kHnjHhBzzLn+GQd92QRuIMqd+b xHK4829cjcLT67sR7AR32+D10Qgbify2FdUpjUV39cbZac+xNwTSqRyni9nztARkOf jFo3IYzX8aAQUMPgE+/uKhljj/GL9aBL4SANNI2k= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5827JgoF2661415 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 2 Sep 2025 02:19:42 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 2 Sep 2025 02:19:42 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 2 Sep 2025 02:19:42 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5827JJgc3689199; Tue, 2 Sep 2025 02:19:38 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v3 3/3] arm64: dts: ti: k3-pinctrl: Add the remaining macros Date: Tue, 2 Sep 2025 12:49:17 +0530 Message-ID: <20250902071917.1616729-4-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250902071917.1616729-1-a-kaur@ti.com> References: <20250902071917.1616729-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add the drive stregth, schmitt trigger enable macros to pinctrl file. Add the missing macros for DeepSleep configuration control referenced from "Table 14-6172. Description Of The Pad Configuration Register Bits" in AM625 TRM[0]. Add some DeepSleep macros to provide combinations that can be used directly in device tree files example PIN_DS_OUTPUT_LOW that configures pin to be output and also sets its value to 0. [0] https://www.ti.com/lit/ug/spruiv7b/spruiv7b.pdf Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 55 +++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index c0f09be8d3f9..39aad59075d1 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -3,15 +3,20 @@ * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti= .com/ + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti= .com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H =20 +#define WKUP_LVL_EN_SHIFT (7) +#define WKUP_LVL_POL_SHIFT (8) #define ST_EN_SHIFT (14) #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DRV_STR_SHIFT (19) +#define DS_ISO_OVERRIDE_SHIFT (22) +#define DS_ISO_BYPASS_EN_SHIFT (23) #define DEBOUNCE_SHIFT (11) #define FORCE_DS_EN_SHIFT (15) #define DS_EN_SHIFT (24) @@ -19,6 +24,7 @@ #define DS_OUT_VAL_SHIFT (26) #define DS_PULLUD_EN_SHIFT (27) #define DS_PULLTYPE_SEL_SHIFT (28) +#define WKUP_EN_SHIFT (29) =20 /* Schmitt trigger configuration */ #define ST_DISABLE (0 << ST_EN_SHIFT) @@ -33,6 +39,26 @@ #define INPUT_EN (1 << RXACTIVE_SHIFT) #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) =20 +#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) + +#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENAB= LE) +#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENAB= LE) + +#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT) +#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT) + +#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) + +#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) +#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) +#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) +#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) +#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) + +#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) + /* Only these macros are expected be used directly in device tree files */ #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) @@ -53,18 +79,41 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) =20 +#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) + +#define PIN_SCHMITT_TRIGGER_DISABLE (0 << ST_EN_SHIFT) +#define PIN_SCHMITT_TRIGGER_ENABLE (1 << ST_EN_SHIFT) + #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) #define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) #define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT) -#define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) -#define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) +#define PIN_DS_OUT_ENABLE DS_INPUT_DISABLE +#define PIN_DS_OUT_DISABLE DS_INPUT_EN #define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) #define PIN_DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) #define PIN_DS_PULLUD_ENABLE (0 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) #define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_ISO_BYPASS (1 << DS_ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS_DISABLE (0 << DS_ISO_BYPASS_EN_SHIFT) + +#define DS_STATE_VAL (1 << DS_EN_SHIFT) +#define ACTIVE_STATE_VAL (0 << DS_EN_SHIFT) + +#define PIN_DS_OUTPUT_LOW (DS_STATE_VAL | DS_INPUT_DISABLE |= DS_OUT_VALUE_ZERO) +#define PIN_DS_OUTPUT_HIGH (DS_STATE_VAL | DS_INPUT_DISABLE |= DS_OUT_VALUE_ONE) +#define PIN_DS_INPUT (DS_STATE_VAL | DS_INPUT_EN | DS_P= ULL_DISABLE) +#define PIN_DS_INPUT_PULLUP (DS_STATE_VAL | DS_INPUT_EN | DS_P= ULL_UP) +#define PIN_DS_INPUT_PULLDOWN (DS_STATE_VAL | DS_INPUT_EN | DS_P= ULL_DOWN) + +#define PIN_WKUP_EN_EDGE (WKUP_ENABLE | WKUP_ON_EDGE) +#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKU= P_LEVEL_LOW) +#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKU= P_LEVEL_HIGH) +#define PIN_WKUP_EN WKUP_EN_EDGE =20 /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) --=20 2.34.1