From nobody Fri Oct 3 11:22:56 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 557A52BEFEB; Tue, 2 Sep 2025 00:13:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771990; cv=none; b=YQOaMMAt7tJYPT4puMI2EPJYMUKydAMOyWFGT6ud5bWadGYUlRij12IMBQpJpk1Z3CTNuAqHhIQ54TasRhkMjoUHr6iBelb0dWO9+HeXorlFaG0fkVi7aRVHkF2SwcuDlb1wxHMbUdNAhmxFoJdSgGWFZpLcB95+pa+I+zGNBRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771990; c=relaxed/simple; bh=q13jDoBacNruUmINfRn1N+CSPhkzJg45QwqqWKj7NqM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H57t7d2uwuOK12bwb0pXcvdV5kRINVS55xA4OYc26MgR62UVp5cSVQoElxOFz/hiebfwfWpDXXkzNsGnGpkiHfxqeIewCsEfx9r84ioTsw5xOy520Q3S5VuvLjARv1AQ53IgK7QwqnJ2//oW/K9WE8OW2QMRuEjZm/IZr5DXVyw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=i0fHVGVw; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i0fHVGVw" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3da4c14a5f9so45133f8f.0; Mon, 01 Sep 2025 17:13:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1756771987; x=1757376787; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9AzoOdR6sJDHEcKW2yNQOC2NaWtXxFSPPgG0odQCnsE=; b=i0fHVGVw0FkRt9FGDwr8G5wJdShwm91O6UI/6Ot/VbRSfVZNdDKPHVQDCTYFoBXrnf gNiO4+BEtyz9S6aJUtAovOSqo0u8dom2VK2WuDpny0HN8MWmEROzARHXDLzu3ETEHOC9 giPEbILN48KZbvzSaOwXZJ5YbuSlMh+wz9aNTpuAduNfM9ReQuwE5ZD5R3QJdkoKfUP1 xojkLYVplVKQIBU7V2Rj/UzMdo2ImYVUuyxLisFfqEOX7JChkDLxIJ7C7VjxSa7gmNwX 06Cpv/fD7jwhN7lsdnky0p1kxnTmSk1d7SPuhKWbRJcvv25FbfXsTLDu16JNPUjeZpvO 3Ihw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756771987; x=1757376787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9AzoOdR6sJDHEcKW2yNQOC2NaWtXxFSPPgG0odQCnsE=; b=LyOXTaHdTpKhWU7SvoXpb1fplcSTnXdJFISf8qP8VL+heaFUVnfN3SRhy/MGsHYTFX RTnIWkMCdgaE1diPMhPAKQHEe/OEKw9jSB9briAA13iSwx60mUFNXnoKD/AnuCfi0bSi h54IDgGrcGbFt7jPlT2lNcX2uaTxCrVKiG3ZJPEEmqXW+V8Ufcm6dXnpuiq/wcYBwhg/ NiJPXOLAoEomS6cl6dG9+NMmUR6V/ALyzUYccO7Ntqi2EtnSit/OjWJD0MZDgmx70wsB AWQ0FNR2bzUjdf/OqKuWwWFX+GYniPh9gfw7ouyUItQJlaI+dnMnoR+bdzsRSEh3o3bI 54VA== X-Forwarded-Encrypted: i=1; AJvYcCWhrcdMnzOsUrbdifyJCIbuQfY2J9Mq2+oN2/vdNrg//Z2OkQatmoi3K/6qcyjyUpA9i5zFDZnI@vger.kernel.org, AJvYcCXMrhbFsWCHj/9qTnozqjeUwexiAuGLl/Ig0RrgVOYQX3W7JB0BGcc0vbyND7eaedCaoqiMe/miIr3JIPSK@vger.kernel.org, AJvYcCXuzqn8YfOYOWeke1j9zMId7nYdbu2TkaldTMX4O+k6EafhSf/jQm+K/waYDBqx41bjxz2gtcKNEkw7@vger.kernel.org X-Gm-Message-State: AOJu0YyGoN+euEzAn+EpFwK4NPgqIwMjxS7Sz4MSru14sPZpZU8WIe6V TIFMcx+iutSi2GgUrcdt24L4OZh59ZO1SghbVq/O1ZVYeAx45mye42Nh X-Gm-Gg: ASbGncvOODXHNu30byeXYdMomBT7OWeBcl1Hc1o+GALrxNRfiFLNm62BDiXZY7/X9vR aeZmkd6sahQVd5dHf/0bw+O/9yDaZLyGzfc1/3rIOgz020MG3778SoJUVVHz95qLy5zRjuSwLJ6 Mg5+gll52CnqdVzVOq6fW/jkp9coRR1ocEcvblbpybejGOiNz1Ygx0qjafgc9XHvhjvQOEk9dgO bvz3gdEC/GL8w6t+ExL2scxcQpkHtgLN/Ddc7euFWeBvQzIv48QalaiNp5SFo/0nPmBCB3jg6JH oiTIUg0LfJjjRaGSCtiWBHZXW0t1+F2DWE+QI5f9onUGtBNFjVauiKGGNjHMt9keGwZhPeoFQ1w R/WIfJ4c+YuAsbpnimjDJLOGiD5HAiib6Adi6PxpfPDd8Zr4CD7A/Ix91 X-Google-Smtp-Source: AGHT+IE3uKhYEY1h+tUV59URGGBQIgTcoq1CY3L+zPFZ/Z3aqPfVSo0apPvIpocUjyJSk/XhqU4+ug== X-Received: by 2002:a05:6000:248a:b0:3d9:a7b3:1b05 with SMTP id ffacd0b85a97d-3d9a7b31bfamr745722f8f.25.1756771986610; Mon, 01 Sep 2025 17:13:06 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ca6c:86b2:c8f:84d6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d92d51982bsm2138153f8f.21.2025.09.01.17.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Sep 2025 17:13:05 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Russell King , Giuseppe Cavallaro , Jose Abreu , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 1/4] dt-bindings: net: dwmac: Increase 'maxItems' for 'interrupts' and 'interrupt-names' Date: Tue, 2 Sep 2025 01:12:59 +0100 Message-ID: <20250902001302.3823418-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Increase the `maxItems` value for the `interrupts` and `interrupt-names` properties to 19 to support additional per-channel Tx/Rx completion interrupts on the Renesas RZ/T2H SoC, which features the `snps,dwmac-5.20` IP with 8 Rx queues and 8 Tx queues. Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 4e3cbaa06229..578553840c9e 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -118,11 +118,11 @@ properties: =20 interrupts: minItems: 1 - maxItems: 11 + maxItems: 19 =20 interrupt-names: minItems: 1 - maxItems: 11 + maxItems: 19 items: oneOf: - description: Combined signal for various interrupt events @@ -134,9 +134,9 @@ properties: - description: The interrupt that occurs when HW safety error trig= gered const: sfty - description: Per channel receive completion interrupt - pattern: '^rx-queue-[0-3]$' + pattern: '^rx-queue-[0-7]$' - description: Per channel transmit completion interrupt - pattern: '^tx-queue-[0-3]$' + pattern: '^tx-queue-[0-7]$' =20 clocks: minItems: 1 --=20 2.51.0 From nobody Fri Oct 3 11:22:56 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809D92BFC60; Tue, 2 Sep 2025 00:13:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771991; cv=none; b=mNkgGQc47NiEutBHnsNGI6u86uiTPY1PvN2f9Pdw8lPED7pJCCc1ceyaT+1wT5FBh0ctIJQTAzcmoGkWYS83Vj8worPShM5EvhGouK0EIHRoKnlyKHMmtKTSXKeD939ZxGthsnkhjzXeSXUeyQi/iWaMr4PO3NHKABmzutTQkAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771991; c=relaxed/simple; bh=vwhuenc9EiopLE5Ii4+in9Gz3iF2aIzNlwPMDDwwVbY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s6XwTZkktc0q95Ssddye/pWqvz2fHsagoXH76v1sYsRUD8ntQxWhsqlvOwdkvYkFCBxzj467nobXcxzzPRp8cFq1lrrWqj9Y/wHGGP3R8xFI3fbAe+ZuwWZ6zdXf2hA6d8RvnGDHEhQEclIuuDdqqv9kX70mHoSH0mJt5S/ukJg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gVdd+89u; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gVdd+89u" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-3d1bf79d758so2120173f8f.1; Mon, 01 Sep 2025 17:13:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1756771988; x=1757376788; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=etFKt7+tWRxLPhUeF783JanGoHY0JOZ/EUy1MnL+9k4=; b=gVdd+89upfwDQXOsWJkN1iIUceqVNTDyavrt6ELzrHTNB0tZOb1rHB21GzHKNSD3Ej 4dxmWCfeHbWK86ErIJ6UAfA8SuEJNhTe/qRe1ZeyGtwoTZSk7OSDfEr0V8I3bhNhOAgs bzgbZ1g0KOomNMxNfub0BZnpDF/qguM2EIefJN33o02Qf6OtsguIj6vLvja9/4yIlUoI oGz759hndIvUbBI2OS892WVuT1fLbuagzJizYyP5uVyCEwY+yBVxirGRGD9zDMgPlOBG 6OyuPpuGMG+L4Lmaz0eLDag3pcuX6ScO9volbB1Luzf3vkKprA6v+BMTicxBfzyHyhzx RdkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756771988; x=1757376788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=etFKt7+tWRxLPhUeF783JanGoHY0JOZ/EUy1MnL+9k4=; b=qrO9CDdTcQj85NJgVbiyQjttxXiMEGI1SOpo9+0qOGqTd7qHtNro3Xk/+1+4phV9j9 LjfX4YieUbzao0RCfZGiubUgxLQr+vnHesOT0FAE3yWBJl+DxlwIZsj14Vg81OYEr2DB 7ROP7Z6205WHNtvD74KcwWxtG2j4WQEgZulL6ZGtPXEraz5rR8A+MaiJ763wcqqmcRH+ 5YVU8qaJVaYQIqlxvWNmKxm9Fu4RDwr5Kyt6eOawNBOl+TqtzKJOn0KjEyLkJ0PhqGO8 wSJt86yhGfCrWg92ZkMeugOZD8znStSNLhXm95V8kw9EwVWgCZVdJVebK6AAnQeCh7R5 Nshg== X-Forwarded-Encrypted: i=1; AJvYcCUOEYU12rBa9nFj+p4hKWhaAclc3K2sWDt7nPwNW1UqfeRop1ptyKEtVWHOIaZUTZ1EolE4Fk1jFkE/i4Uh@vger.kernel.org, AJvYcCVJVanbsb/bCMBRQ94rAHpcdJj5SvZBOYHkaeN1ue9zmLYFf1IhcZx2CcYODlDzQIkbCFcFoNATWOrD@vger.kernel.org, AJvYcCWIKli/zIIdQVLvBGAdKYPDO5n0FQNA2UNn7r9Xh34Ii2JgSvNISxQ74fGzFyjdtjUzLEOQNLx1@vger.kernel.org X-Gm-Message-State: AOJu0YyfkGeE5EcO14M9o4J/KEo5jjpsVtHKwroU8mEsj9+j6rD2Rz/e SvyUyq3Lnt4i2SPztekP3fBqdjJ/uVA5hHysjdBTuJ/jLUM37r0qVmY7 X-Gm-Gg: ASbGncs+RP4sTQNXnZG504tk79xqI8vCmk97+aH8oUoPTE7cYq69CaV9d0fYViAwGwO elxUsNfSNdmVhqS3gE/ippi1gEdKKkxutE7zyOLFart8ajdFSTT4viCxm4ZMIDqexiA9wzNNRNp Hf5JxSlFRP9i38AGRR9gKmGM6IOBP4inqwNPF8OKfwizaLM+6Xub6ws9X48UaWFqoz5qTt8ZgHl +9bENelumlv1ybSp7oUsy3M708b159LJASTuirwYYuCnIGNbF19z+A5Q8WwkPU3RJfCdZlbxjij uR80FJIQSRybSPKg0fjcxjiTER86FHWCGPlmYRPeSjd1TV4BF6nkjfrEHe+SB1Ofiq8695TbghD +m+Aq3HA6+B5BP4Rn0HCMIH0r7ym0GwSTw4oXLuSFLBedWHBIm4THUAUI X-Google-Smtp-Source: AGHT+IFPGTlk+evyu+xtq0waHE/04booU4YiDIt+L0pMGxGvKONa+Sj6VFPE3ubiKF0MVGHEbhBjNA== X-Received: by 2002:a05:6000:2387:b0:3cd:cf31:d77b with SMTP id ffacd0b85a97d-3d1dfcfb96fmr6542569f8f.37.1756771987739; Mon, 01 Sep 2025 17:13:07 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ca6c:86b2:c8f:84d6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d92d51982bsm2138153f8f.21.2025.09.01.17.13.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Sep 2025 17:13:07 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Russell King , Giuseppe Cavallaro , Jose Abreu , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 2/4] dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/T2H and RZ/N2H SoCs Date: Tue, 2 Sep 2025 01:13:00 +0100 Message-ID: <20250902001302.3823418-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document the Ethernet MAC (GMAC) IP present on the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The GMAC IP on RZ/N2H is identical to that found on the RZ/T2H SoC. While the RZ/V2H(P), RZ/T2H, and RZ/N2H SoCs all integrate the Synopsys DesignWare MAC (version 5.20), the hardware is synthesized with different options compared to the RZ/V2H(P): - RZ/T2H requires only 3 clocks instead of 7 - RZ/T2H supports 8 RX/TX queue pairs instead of 4 - RZ/T2H needs 2 reset controls with reset-names property, vs. a single unnamed reset - RZ/T2H has the split header feature enabled, while it is disabled on RZ/V2H(P) To accommodate these differences, introduce a new generic compatible string `renesas,rzt2h-gbeth`, used as a fallback for both RZ/T2H and RZ/N2H SoCs. The DT schema is updated to validate the clocks, resets, reset-names, interrupts, and interrupt-names properties accordingly. Also extend `snps,dwmac.yaml` with the new `renesas,rzt2h-gbeth` compatible. Signed-off-by: Lad Prabhakar --- .../bindings/net/renesas,rzv2h-gbeth.yaml | 177 ++++++++++++++---- .../devicetree/bindings/net/snps,dwmac.yaml | 1 + 2 files changed, 138 insertions(+), 40 deletions(-) diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml= b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index 23e39bcea96b..e01763389164 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -17,63 +17,112 @@ select: - renesas,r9a09g047-gbeth - renesas,r9a09g056-gbeth - renesas,r9a09g057-gbeth + - renesas,r9a09g077-gbeth + - renesas,r9a09g087-gbeth - renesas,rzv2h-gbeth required: - compatible =20 properties: compatible: - items: - - enum: - - renesas,r9a09g047-gbeth # RZ/G3E - - renesas,r9a09g056-gbeth # RZ/V2N - - renesas,r9a09g057-gbeth # RZ/V2H(P) - - const: renesas,rzv2h-gbeth - - const: snps,dwmac-5.20 + oneOf: + - items: + - enum: + - renesas,r9a09g047-gbeth # RZ/G3E + - renesas,r9a09g056-gbeth # RZ/V2N + - renesas,r9a09g057-gbeth # RZ/V2H(P) + - const: renesas,rzv2h-gbeth + - const: snps,dwmac-5.20 + + - items: + - enum: + - renesas,r9a09g077-gbeth # RZ/T2H + - renesas,r9a09g087-gbeth # RZ/N2H + - const: renesas,rzt2h-gbeth + - const: snps,dwmac-5.20 =20 reg: maxItems: 1 =20 clocks: - items: - - description: CSR clock - - description: AXI system clock - - description: PTP clock - - description: TX clock - - description: RX clock - - description: TX clock phase-shifted by 180 degrees - - description: RX clock phase-shifted by 180 degrees + oneOf: + - items: + - description: CSR clock + - description: AXI system clock + - description: PTP clock + - description: TX clock + - description: RX clock + - description: TX clock phase-shifted by 180 degrees + - description: RX clock phase-shifted by 180 degrees + + - items: + - description: CSR clock + - description: AXI system clock + - description: TX clock =20 clock-names: - items: - - const: stmmaceth - - const: pclk - - const: ptp_ref - - const: tx - - const: rx - - const: tx-180 - - const: rx-180 - - interrupts: - minItems: 11 + oneOf: + - items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: tx + - const: rx + - const: tx-180 + - const: rx-180 + + - items: + - const: stmmaceth + - const: pclk + - const: tx + =20 interrupt-names: - items: - - const: macirq - - const: eth_wake_irq - - const: eth_lpi - - const: rx-queue-0 - - const: rx-queue-1 - - const: rx-queue-2 - - const: rx-queue-3 - - const: tx-queue-0 - - const: tx-queue-1 - - const: tx-queue-2 - - const: tx-queue-3 + oneOf: + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 =20 resets: - items: - - description: AXI power-on system reset + oneOf: + - items: + - description: AXI power-on system reset + + - items: + - description: GMAC stmmaceth reset + - description: AHB reset + + reset-names: true =20 required: - compatible @@ -87,6 +136,54 @@ required: allOf: - $ref: snps,dwmac.yaml# =20 + - if: + properties: + compatible: + contains: + const: renesas,rzt2h-gbeth + then: + properties: + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + interrupts: + minItems: 19 + + interrupt-names: + minItems: 19 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + required: + - reset-names + else: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + + interrupts: + minItems: 11 + maxItems: 11 + + interrupt-names: + minItems: 11 + maxItems: 11 + + resets: + maxItems: 1 + + reset-names: false + unevaluatedProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 578553840c9e..14be80fe9c82 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -77,6 +77,7 @@ properties: - renesas,r9a06g032-gmac - renesas,rzn1-gmac - renesas,rzv2h-gbeth + - renesas,rzt2h-gbeth - rockchip,px30-gmac - rockchip,rk3128-gmac - rockchip,rk3228-gmac --=20 2.51.0 From nobody Fri Oct 3 11:22:56 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 138D22C028B; Tue, 2 Sep 2025 00:13:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771992; cv=none; b=EG9V3Bkx3ojv29y6MpNGWmWNugJZE01Q9dmm2+IkamF398xebbxdddQB7iyHsn5hI8dMhQWVVySmvqHLrgf+7hP/nuObUlJBH+68F3OhOCPJv/sEVF5Znyw55a2LuYnluc4ScZHl28Mlb3uu0q2wOIY65/H/Ugc1hzCOEdlIF8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771992; c=relaxed/simple; bh=zekx91f+hmWCWtRE0jqVktFYVvzjJ9zRlqXFKxYsR00=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JrETiM5Xfp7PnjTlvm4DFloPUo+g9lJTD4q1Vi3RtQ+XTLxUwabM/7URZ9OBdZJ5n3L4CFdAIeV1u1JzQrtpRbwHzMPWan5+a3jFg0rfLLCL1rRtoV37G+8ovD3PgUACfVDmDi6ZHHeJs8iOBZfeAFThI51cm8eCJfu0arXoZJE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BEKVNL3R; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BEKVNL3R" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-45a1b065d59so33048345e9.1; Mon, 01 Sep 2025 17:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1756771989; x=1757376789; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IW7wLUGlmaYQP6Tz0Pa2N3CEqKrBMcmhwzaDX5OOnZ8=; b=BEKVNL3Rd40vphF5jlsgvDjrr2GD1rc8q557k8xNWv5yWEd3d66EaIa58Wpf/pON2G Rfp0HAWr9CAimP3xVlbB7reyEZjyEVZMaUgU6V8LJw8EbImhB+hp2sBx1DgG8RW20qcM xnWYwn7dcCxAZmuZ6paaq9/MGPZb9zrVYGXJqMrEsoMbfF4ac2jMj5QcILuq+DkZQkh3 DB0PJGghCUFkqQ3WIc0R5LelAaj5gHJvwgs7GDf5qBmkF5ublBB5t3leyeOCz7b0eqDy cmar6S6qe/XoVZ5U2QZjjuitRIt3nmAQtlSNAG+6f+6L2PK70r1gbNAwEdYxHWwcaGpY cd8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756771989; x=1757376789; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IW7wLUGlmaYQP6Tz0Pa2N3CEqKrBMcmhwzaDX5OOnZ8=; b=Bbed6sh2Ecv64ekuhfF/USC9FJKmtWC4FUa9eGqxBoHFzNOXH9L1FOaeEKzMJZge1Q DOBVhihCCNkkw48suJho9yMGFvUB7ANZ91h6sDV/uwW39G3DhHGoB6vbMuIyH0g0A+Kt 7bA+UAjeLKywOVSVB03m/JReim03mkcQPh29c+TCM42wn7PjBLkn2QeH8jkNdTe4uaaD ZhwFJD62L2xRFcxap8hW7MkZdBGKLF3PFwtQaUPnotPjUMYY+zoawSNJb8gz1ywVFqUE 9lKv+lzx8R6zMlkUQSoYYP88wllhr0MUaJq0GSQqXT1jHMvsA6cdTt2E0ickM2GP3t49 aO8A== X-Forwarded-Encrypted: i=1; AJvYcCUlpKUEwiVzVzgpWFPAp+o0nk0xBz2IQD4Q40PUuOAdjNQ84nDW8Y6rNGSuC8TYQEjp7b1amyQF@vger.kernel.org, AJvYcCVuDERu0lN8dcuC4REE/o01F1X0BgdQZ+zp8u2kKqavDRatGT+puW3xR2fBo7z5aEEf04wEEoMpmJVKi1EO@vger.kernel.org, AJvYcCWyLRUAPHu5X1qjulINBewc9jf3IkYiMLKoU7iPPiu9AhFnPjRxp/Oxe5d26UCmjNYiesOjwiDERjFI@vger.kernel.org X-Gm-Message-State: AOJu0Yw4/VaO+32M5jRcFPfhSs8c2NaxQJ9Mv5D9m6NyYWxIa9Sk7wD3 o4oJnZavrVDezPop7CSiLxw4D0qTIvKyzF41VMZoDVZb9EmgdCtpFkvV X-Gm-Gg: ASbGncvtgrH5nfgQCb4gQVlb6tbbFZx4dQZ5VPQHpZoTNwErp2Rv6G9vNuR6GYTaMQC NmhbT/nvu3LKQFbyIf4gXdngII5uFh8UTfdcr2ehBp1lEfUhRJLKsxBGB1eOYuB7nLlXRVNuHrB xfTfftOWsJy0TWm6c3cDj4wMet0hmno69y7pPUbc6/lCvx0l5oeAgylNq3NsofEVv424D67lFA2 VcQZfrcEWJ+0xcQhDmyjF7ws3+bwnXj1z4iLWlCjRmcokq8y6ihiA2YrrT6iYA5CE5k9WKmaSrk sepMhUDiyCVYeVDAwMtRUE7hq7jFfi+B1C8ShqvNJygHjp3y2WgM3gOxkWw+hVvfXjiUyvAg77j jHDX2R8Pap8B+oG4LARoeKnCoILY6ghLdeUp5U5SxtFe1kr7TbdLTlrrl X-Google-Smtp-Source: AGHT+IHuS7QRUr21Kdtxu2CuDcnTrvddR0z5zY3NevQTs8JFkmoZuliR3bAbwjIkq43ebLCLnjTS7Q== X-Received: by 2002:a05:600c:a0a:b0:456:1824:4808 with SMTP id 5b1f17b1804b1-45b855aeb67mr71158435e9.32.1756771989248; Mon, 01 Sep 2025 17:13:09 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ca6c:86b2:c8f:84d6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d92d51982bsm2138153f8f.21.2025.09.01.17.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Sep 2025 17:13:08 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Russell King , Giuseppe Cavallaro , Jose Abreu , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 3/4] net: stmmac: dwmac-renesas-gbeth: Use OF data for configuration Date: Tue, 2 Sep 2025 01:13:01 +0100 Message-ID: <20250902001302.3823418-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare for adding RZ/T2H SoC support by making the driver configuration selectable via OF match data. While the RZ/V2H(P) and RZ/T2H use the same version of the Synopsys DesignWare MAC (version 5.20), the hardware is synthesized with different options. To accommodate these differences, introduce a struct holding per-SoC configuration such as clock list, number of clocks, TX clock rate control, and STMMAC flags, and retrieve it from the device tree match entry during probe. Signed-off-by: Lad Prabhakar --- .../stmicro/stmmac/dwmac-renesas-gbeth.c | 57 +++++++++++++++---- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/dr= ivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index df4ca897a60c..022e595a9e1b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -16,12 +16,34 @@ #include #include #include +#include #include #include +#include =20 #include "stmmac_platform.h" =20 +/** + * struct renesas_gbeth_of_data - OF data for Renesas GBETH + * + * @clks: Array of clock names + * @num_clks: Number of clocks + * @stmmac_flags: Flags for the stmmac driver + * @handle_reset: Flag to indicate if reset control is + * handled by the glue driver or core driver. + * @set_clk_tx_rate: Flag to indicate if Tx clock is fixed or + * set_clk_tx_rate is needed. + */ +struct renesas_gbeth_of_data { + const char * const *clks; + u8 num_clks; + u32 stmmac_flags; + bool handle_reset; + bool set_clk_tx_rate; +}; + struct renesas_gbeth { + const struct renesas_gbeth_of_data *of_data; struct plat_stmmacenet_data *plat_dat; struct reset_control *rstc; struct device *dev; @@ -70,6 +92,7 @@ static void renesas_gbeth_exit(struct platform_device *pd= ev, void *priv) =20 static int renesas_gbeth_probe(struct platform_device *pdev) { + const struct renesas_gbeth_of_data *of_data; struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct device *dev =3D &pdev->dev; @@ -91,14 +114,17 @@ static int renesas_gbeth_probe(struct platform_device = *pdev) if (!gbeth) return -ENOMEM; =20 - plat_dat->num_clks =3D ARRAY_SIZE(renesas_gbeth_clks); + of_data =3D of_device_get_match_data(&pdev->dev); + gbeth->of_data =3D of_data; + + plat_dat->num_clks =3D of_data->num_clks; plat_dat->clks =3D devm_kcalloc(dev, plat_dat->num_clks, sizeof(*plat_dat->clks), GFP_KERNEL); if (!plat_dat->clks) return -ENOMEM; =20 for (i =3D 0; i < plat_dat->num_clks; i++) - plat_dat->clks[i].id =3D renesas_gbeth_clks[i]; + plat_dat->clks[i].id =3D of_data->clks[i]; =20 err =3D devm_clk_bulk_get(dev, plat_dat->num_clks, plat_dat->clks); if (err < 0) @@ -109,25 +135,36 @@ static int renesas_gbeth_probe(struct platform_device= *pdev) return dev_err_probe(dev, -EINVAL, "error finding tx clock\n"); =20 - gbeth->rstc =3D devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(gbeth->rstc)) - return PTR_ERR(gbeth->rstc); + if (of_data->handle_reset) { + gbeth->rstc =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(gbeth->rstc)) + return PTR_ERR(gbeth->rstc); + } =20 gbeth->dev =3D dev; gbeth->plat_dat =3D plat_dat; plat_dat->bsp_priv =3D gbeth; - plat_dat->set_clk_tx_rate =3D stmmac_set_clk_tx_rate; + if (of_data->set_clk_tx_rate) + plat_dat->set_clk_tx_rate =3D stmmac_set_clk_tx_rate; plat_dat->init =3D renesas_gbeth_init; plat_dat->exit =3D renesas_gbeth_exit; - plat_dat->flags |=3D STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY | - STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP | - STMMAC_FLAG_SPH_DISABLE; + plat_dat->flags |=3D gbeth->of_data->stmmac_flags; =20 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } =20 +static const struct renesas_gbeth_of_data renesas_gbeth_of_data =3D { + .clks =3D renesas_gbeth_clks, + .num_clks =3D ARRAY_SIZE(renesas_gbeth_clks), + .handle_reset =3D true, + .set_clk_tx_rate =3D true, + .stmmac_flags =3D STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY | + STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP | + STMMAC_FLAG_SPH_DISABLE, +}; + static const struct of_device_id renesas_gbeth_match[] =3D { - { .compatible =3D "renesas,rzv2h-gbeth", }, + { .compatible =3D "renesas,rzv2h-gbeth", .data =3D &renesas_gbeth_of_data= }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, renesas_gbeth_match); --=20 2.51.0 From nobody Fri Oct 3 11:22:56 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46E542C11D2; Tue, 2 Sep 2025 00:13:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771994; cv=none; b=u4kzRHgd8wCB9HCyga21GZTL0fzVmW9bOE9j4ElkZJA5oNDhj/mX+GogWaQKcDqb+qSGFRMiWLrZWWB5msU03O4LOZtPA9AaQqbG9S/UHsY7B+zPB76IoyK79Jzk6TyjW9B5npT3xxNGC9oV7NZJnyXpwozhQcHUX2dGDB/QJbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756771994; c=relaxed/simple; bh=rYSJndT6hXCXD8jlYBfbdSRTF0KIs6xPzFEVUOaarJ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TTorBGgTwVy7q05zK+S1Z22XtWQx0jwDE/kA1AWVi/G4NSDnzUEMqA+SaG3LRi8v3OX46GETojWcSlluQZuYsbTl78Peg+GXuABEUD52Nn/szVGjW2X4yO5MeDORxAsrOXcKoQ+ckH6lPJ8B0rgGhJx0e4Z753ceNulWrzwNoeI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gN0UsaAM; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gN0UsaAM" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-45b8b7ac427so9532315e9.2; Mon, 01 Sep 2025 17:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1756771990; x=1757376790; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yYNmQYHvpUW9ygwaADrHIo+U++1cqaaqBXRIk4cWf5E=; b=gN0UsaAMCpIxfXQKYNsvpwI1rHEXHvwd+ej41+DQDW6uMC65H/B+DotWJ5jEGuV907 f0tBE08q5BxgNPgkqBTq4iVIrf50/ENYLtFpGL8krHI9uDwqqGIG0ncVwKRFZVIlYMjR BdtoU/YufSkjezVdc46pLiBB0mkezOaf9qTYlXtV8BFThcp0bbQcsHZiQYdDEmGnG0w6 HbOPHB5qILYtlv9gOG1Dkl7nXCwD7W+WhfJtAWNPyN0m+ZlKeOrXeye+79mHU4NQ/hDZ jbtQB9sxGF/HHuiX6ipy82DVJvB1qVynBhEOP0RFSFDfxiI0LF1a+kznA0vEcln0Xicj gZVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756771990; x=1757376790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yYNmQYHvpUW9ygwaADrHIo+U++1cqaaqBXRIk4cWf5E=; b=N5eSZeB9L3hEQwWmcq0S4YUustvciC2Od7e+Jq1+iJzzanlxwdOVNkXgYRcd2BIHH5 tqKtBH4vuUfwzClrf+NLMUH7zgFTtZ1eLLIW+j+PEOzh6w56WXZ+R4/hn4hCHvNtilNy aF6vv7iGfcHzQ/E4cdy7wvOPBM9Orbfv4BzXPbN5TcQrLOUernLFUkKfeuT8dthzQZZm mpwR1Z9cLicEkTRZArvb2EFLB1d5okPxvjG28PDcLOOzgWaRVrIQlG0sGzMOEOFcoWG5 c8T3UHms1lURVNcNudJVr6F/fEYQsKTRDzH5vpPO+Rwo6QiAFcLLN9MGHiGDQ+f2NtMP jOgQ== X-Forwarded-Encrypted: i=1; AJvYcCUYAy1yaZb319gsigJuPZjuEoxidBecLG6IhsygFbrkAWMxtOXqeuOl0b3VSrxGsRyK/EamM5Za@vger.kernel.org, AJvYcCUZpfIHO6inERwDpVVvKhHO3MUSmwqpoIUPPTudkwK74TOgf+saf4ZkRR25saLakmzdfW0T5MooWBV08PrN@vger.kernel.org, AJvYcCXjiYXuEHYD7y+0YKpziLoVtPLNYbKc6dIJdZxG2ReKsHJJ985j3Ip6p3z8vZgh6HVrAF1utr/MFCY3@vger.kernel.org X-Gm-Message-State: AOJu0YzN9rhw0ZnwBixsA1zlc4D4ebg6Kj59zrOm3hJmpqCC8zW7Lpy1 xZwVTvamoR6QGQYCJGgJItyB+rIzgFPOwq9YBKVhm5qM61M7TcyKKLTp X-Gm-Gg: ASbGncsg/Ndwp7jJ9waHXi90s78YDMn81lVF86ZP7P3RcDG/gcpIlJu3ULTj5XzueEL 5JN2iPpQZi4byk80ACRGk2XwghsDdbTsizbFwwB/izU28iMA8X54cGTH6SalrL7FteSEmtdC65q khBbOJhaVLtYV13yyHznzBpvoBCHZPKiqMUKVOJhDr6LVWqBPavVAJf+nfN3VNbcm6yh7+MjYpx 4r8UbE14h1Wm7wjw/HWShlxzBgI7SQs8h9kS+ZDX5P+MJcGlXMCptNA/h6c4UaVWLbwAxOIO+Y8 +H1v9aJhw0WrJ+TLoVFyOh7FezIelTGHlKBIlza93DlCu6g17EFIMTuCPJAS+3/hKPvBbrW/ZOy +aS/E1Ylfi5RpZOOLc8274Bx21OWFqXTbuK2HJVhIe5U+9Q== X-Google-Smtp-Source: AGHT+IFGGuLbjih6Gj+w7x0wLgIFZo1ltt4HE5wOWmB54nwG1DjvGnz2BT6uviOKTC8YNommrrKJIQ== X-Received: by 2002:a05:600c:4fcd:b0:45b:7185:9e5 with SMTP id 5b1f17b1804b1-45b85525cddmr83857055e9.5.1756771990377; Mon, 01 Sep 2025 17:13:10 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ca6c:86b2:c8f:84d6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d92d51982bsm2138153f8f.21.2025.09.01.17.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Sep 2025 17:13:09 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Russell King , Giuseppe Cavallaro , Jose Abreu , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 4/4] net: stmmac: dwmac-renesas-gbeth: Add support for RZ/T2H SoC Date: Tue, 2 Sep 2025 01:13:02 +0100 Message-ID: <20250902001302.3823418-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250902001302.3823418-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Extend the Renesas GBETH stmmac glue driver to support the RZ/T2H SoC, where the GMAC is connected through a MIIC PCS. Introduce a new `has_pcs` flag in `struct renesas_gbeth_of_data` to indicate when PCS handling is required. When enabled, the driver parses the `pcs-handle` phandle, creates a PCS instance with `miic_create()`, and wires it into phylink. Proper cleanup is done with `miic_destroy()`. New init/exit/select hooks are added to `plat_stmmacenet_data` for PCS integration. Update Kconfig to select `PCS_RZN1_MIIC` when building the Renesas GBETH driver so the PCS support is always available. Signed-off-by: Lad Prabhakar --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + .../stmicro/stmmac/dwmac-renesas-gbeth.c | 52 +++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..a01c83b109f9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -136,6 +136,7 @@ config DWMAC_RENESAS_GBETH tristate "Renesas RZ/V2H(P) GBETH support" default ARCH_RENESAS depends on OF && (ARCH_RENESAS || COMPILE_TEST) + select PCS_RZN1_MIIC help Support for Gigabit Ethernet Interface (GBETH) on Renesas RZ/V2H(P) SoCs. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/dr= ivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index 022e595a9e1b..ad89f7b8f279 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ * handled by the glue driver or core driver. * @set_clk_tx_rate: Flag to indicate if Tx clock is fixed or * set_clk_tx_rate is needed. + * @has_pcs: Flag to indicate if the MAC has a PCS */ struct renesas_gbeth_of_data { const char * const *clks; @@ -40,6 +42,7 @@ struct renesas_gbeth_of_data { u32 stmmac_flags; bool handle_reset; bool set_clk_tx_rate; + bool has_pcs; }; =20 struct renesas_gbeth { @@ -53,6 +56,41 @@ static const char *const renesas_gbeth_clks[] =3D { "tx", "tx-180", "rx", "rx-180", }; =20 +static const char *const renesas_gmac_clks[] =3D { + "tx", +}; + +static int renesas_gmac_pcs_init(struct stmmac_priv *priv) +{ + struct device_node *np =3D priv->device->of_node; + struct device_node *pcs_node; + struct phylink_pcs *pcs; + + pcs_node =3D of_parse_phandle(np, "pcs-handle", 0); + if (pcs_node) { + pcs =3D miic_create(priv->device, pcs_node); + of_node_put(pcs_node); + if (IS_ERR(pcs)) + return PTR_ERR(pcs); + + priv->hw->phylink_pcs =3D pcs; + } + + return 0; +} + +static void renesas_gmac_pcs_exit(struct stmmac_priv *priv) +{ + if (priv->hw->phylink_pcs) + miic_destroy(priv->hw->phylink_pcs); +} + +static struct phylink_pcs *renesas_gmac_select_pcs(struct stmmac_priv *pri= v, + phy_interface_t interface) +{ + return priv->hw->phylink_pcs; +} + static int renesas_gbeth_init(struct platform_device *pdev, void *priv) { struct plat_stmmacenet_data *plat_dat; @@ -149,6 +187,11 @@ static int renesas_gbeth_probe(struct platform_device = *pdev) plat_dat->init =3D renesas_gbeth_init; plat_dat->exit =3D renesas_gbeth_exit; plat_dat->flags |=3D gbeth->of_data->stmmac_flags; + if (of_data->has_pcs) { + plat_dat->pcs_init =3D renesas_gmac_pcs_init; + plat_dat->pcs_exit =3D renesas_gmac_pcs_exit; + plat_dat->select_pcs =3D renesas_gmac_select_pcs; + } =20 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } @@ -163,8 +206,17 @@ static const struct renesas_gbeth_of_data renesas_gbet= h_of_data =3D { STMMAC_FLAG_SPH_DISABLE, }; =20 +static const struct renesas_gbeth_of_data renesas_gmac_of_data =3D { + .clks =3D renesas_gmac_clks, + .num_clks =3D ARRAY_SIZE(renesas_gmac_clks), + .stmmac_flags =3D STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY | + STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP, + .has_pcs =3D true, +}; + static const struct of_device_id renesas_gbeth_match[] =3D { { .compatible =3D "renesas,rzv2h-gbeth", .data =3D &renesas_gbeth_of_data= }, + { .compatible =3D "renesas,rzt2h-gbeth", .data =3D &renesas_gmac_of_data = }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, renesas_gbeth_match); --=20 2.51.0