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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The VPU33 found in the SM8650 Platform requires some slighly different buffer calculation for encoding to allow working with the latest firwware uploaded on linux-firmware at [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware= .git/commit/?id=3Dece445af91bbee49bf0d8b23c2b99b596ae6eac7 Suggested-by: Vikash Garodia Signed-off-by: Neil Armstrong Reviewed-by: Vikash Garodia --- [2] https://lore.kernel.org/all/20250825-iris-video-encoder-v4-0-84aa2bc0a4= 6b@quicinc.com/ --- Changes in v3: - EDITME: use bulletpoints and terse descriptions. - renamed vpu33x to vpu33 - reformated calculation to match original code, dropped default set variab= les to 0 - Link to v2: https://lore.kernel.org/r/20250901-topic-sm8x50-iris-encoder-= v3-hevc-debug-v2-1-c65406bbdf68@linaro.org Changes in v2: - Removed calculation fix for hevc encoding, as it was added in common code - Link to v1: https://lore.kernel.org/r/20250822-topic-sm8x50-iris-encoder-= v3-hevc-debug-v1-1-633d904ff7d3@linaro.org --- drivers/media/platform/qcom/iris/iris_buffer.c | 2 +- .../platform/qcom/iris/iris_hfi_gen1_command.c | 2 +- .../platform/qcom/iris/iris_platform_common.h | 2 + .../media/platform/qcom/iris/iris_platform_gen2.c | 4 + .../platform/qcom/iris/iris_platform_sm8250.c | 2 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 103 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 3 +- 7 files changed, 111 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 8891a297d384b018b3cc8313ad6416db6317798b..c0900038e7defccf7de3cb60e17= c71e36a0e8ead 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -284,7 +284,7 @@ static void iris_fill_internal_buf_info(struct iris_ins= t *inst, { struct iris_buffers *buffers =3D &inst->buffers[buffer_type]; =20 - buffers->size =3D iris_vpu_buf_size(inst, buffer_type); + buffers->size =3D inst->core->iris_platform_data->get_vpu_buffer_size(ins= t, buffer_type); buffers->min_count =3D iris_vpu_buf_count(inst, buffer_type); } =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 29cf392ca2566da286ea3e928ce4a22c2e970cc8..e1788c266bb1080921f17248fd5= ee60156b3143d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -911,7 +911,7 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst *= inst, u32 plane) =20 if (iris_split_mode_enabled(inst)) { bufsz.type =3D HFI_BUFFER_OUTPUT; - bufsz.size =3D iris_vpu_buf_size(inst, BUF_DPB); + bufsz.size =3D inst->core->iris_platform_data->get_vpu_buffer_size(inst,= BUF_DPB); =20 ret =3D hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz)); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 96fa7b1bb592441e85664da408ea4ba42c9a15b5..7057c4cd1a9ebefa02c855014e5= f19993da58e38 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -7,6 +7,7 @@ #define __IRIS_PLATFORM_COMMON_H__ =20 #include +#include "iris_buffer.h" =20 struct iris_core; struct iris_inst; @@ -189,6 +190,7 @@ struct iris_platform_data { void (*init_hfi_command_ops)(struct iris_core *core); void (*init_hfi_response_ops)(struct iris_core *core); struct iris_inst *(*get_instance)(void); + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); const struct vpu_ops *vpu_ops; void (*set_preset_registers)(struct iris_core *core); const struct icc_info *icc_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index cf4b92f534b272a0a1ac2a0e7bb9316501374332..9b3c65ebee94998729246652578= 278e1664be9d2 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -8,6 +8,7 @@ #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_defines.h" #include "iris_platform_common.h" +#include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 #include "iris_platform_qcs8300.h" @@ -738,6 +739,7 @@ struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, .set_preset_registers =3D iris_set_sm8550_preset_registers, .icc_tbl =3D sm8550_icc_table, @@ -827,6 +829,7 @@ struct iris_platform_data sm8650_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu33_ops, .set_preset_registers =3D iris_set_sm8550_preset_registers, .icc_tbl =3D sm8550_icc_table, @@ -916,6 +919,7 @@ struct iris_platform_data qcs8300_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, .set_preset_registers =3D iris_set_sm8550_preset_registers, .icc_tbl =3D sm8550_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 978d0130d43b5f6febb65430a9bbe3932e8f24df..16486284f8acccf6a95a27f6003= e885226e28f4d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -9,6 +9,7 @@ #include "iris_resources.h" #include "iris_hfi_gen1.h" #include "iris_hfi_gen1_defines.h" +#include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 #define BITRATE_MIN 32000 @@ -317,6 +318,7 @@ struct iris_platform_data sm8250_data =3D { .get_instance =3D iris_hfi_gen1_get_instance, .init_hfi_command_ops =3D &iris_hfi_gen1_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen1_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, .set_preset_registers =3D iris_set_sm8250_preset_registers, .icc_tbl =3D sm8250_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 34a9094201ccd11d30a776f284ede8248d8017a9..86894e03e37be5cd42aef225f29= dbf751080b039 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -867,6 +867,27 @@ u32 size_vpss_line_buf(u32 num_vpp_pipes_enc, u32 fram= e_height_coded, (((((max_t(u32, (frame_width_coded), (frame_height_coded)) + 3) >> 2) << 5) + 256) * 16)), 256); } +static inline +u32 size_vpss_line_buf_vpu33(u32 num_vpp_pipes_enc, u32 frame_height_coded, + u32 frame_width_coded) +{ + u32 vpss_4tap_top, vpss_4tap_left, vpss_div2_top; + u32 vpss_div2_left, vpss_top_lb, vpss_left_lb; + u32 size_left, size_top; + u32 max_width_height; + + max_width_height =3D max_t(u32, frame_width_coded, frame_height_coded); + vpss_4tap_top =3D ((((max_width_height * 2) + 3) >> 2) << 4) + 256; + vpss_4tap_left =3D (((8192 + 3) >> 2) << 5) + 64; + vpss_div2_top =3D (((max_width_height + 3) >> 2) << 4) + 256; + vpss_div2_left =3D ((((max_width_height * 2) + 3) >> 2) << 5) + 64; + vpss_top_lb =3D (frame_width_coded + 1) << 3; + vpss_left_lb =3D (frame_height_coded << 3) * num_vpp_pipes_enc; + size_left =3D (vpss_4tap_left + vpss_div2_left) * 2 * num_vpp_pipes_enc; + size_top =3D (vpss_4tap_top + vpss_div2_top) * 2; + + return ALIGN(size_left + size_top + vpss_top_lb + vpss_left_lb, DMA_ALIGN= MENT); +} =20 static inline u32 size_top_line_buf_first_stg_sao(u32 frame_width_coded) @@ -977,8 +998,8 @@ static u32 iris_vpu_enc_non_comv_size(struct iris_inst = *inst) } =20 static inline -u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_height, bool is_ten_bit, - u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) +u32 hfi_buffer_line_enc_base(u32 frame_width, u32 frame_height, bool is_te= n_bit, + u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) { u32 width_in_lcus =3D ((frame_width) + (lcu_size) - 1) / (lcu_size); u32 height_in_lcus =3D ((frame_height) + (lcu_size) - 1) / (lcu_size); @@ -1018,10 +1039,38 @@ u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_= height, bool is_ten_bit, line_buff_recon_pix_size + size_left_linebuff_ctrl_fe(frame_height_coded, num_vpp_pipes_enc) + size_line_buf_sde(frame_width_coded) + - size_vpss_line_buf(num_vpp_pipes_enc, frame_height_coded, frame_width_co= ded) + size_top_line_buf_first_stg_sao(frame_width_coded); } =20 +static inline +u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_height, bool is_ten_bit, + u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) +{ + u32 width_in_lcus =3D ((frame_width) + (lcu_size) - 1) / (lcu_size); + u32 height_in_lcus =3D ((frame_height) + (lcu_size) - 1) / (lcu_size); + u32 frame_height_coded =3D height_in_lcus * (lcu_size); + u32 frame_width_coded =3D width_in_lcus * (lcu_size); + + return hfi_buffer_line_enc_base(frame_width, frame_height, is_ten_bit, + num_vpp_pipes_enc, lcu_size, standard) + + size_vpss_line_buf(num_vpp_pipes_enc, frame_height_coded, frame_width_co= ded); +} + +static inline +u32 hfi_buffer_line_enc_vpu33(u32 frame_width, u32 frame_height, bool is_t= en_bit, + u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) +{ + u32 width_in_lcus =3D ((frame_width) + (lcu_size) - 1) / (lcu_size); + u32 height_in_lcus =3D ((frame_height) + (lcu_size) - 1) / (lcu_size); + u32 frame_height_coded =3D height_in_lcus * (lcu_size); + u32 frame_width_coded =3D width_in_lcus * (lcu_size); + + return hfi_buffer_line_enc_base(frame_width, frame_height, is_ten_bit, + num_vpp_pipes_enc, lcu_size, standard) + + size_vpss_line_buf_vpu33(num_vpp_pipes_enc, frame_height_coded, + frame_width_coded); +} + static u32 iris_vpu_enc_line_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; @@ -1040,6 +1089,24 @@ static u32 iris_vpu_enc_line_size(struct iris_inst *= inst) lcu_size, HFI_CODEC_ENCODE_AVC); } =20 +static u32 iris_vpu33_enc_line_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + u32 lcu_size =3D 16; + + if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { + lcu_size =3D 32; + return hfi_buffer_line_enc_vpu33(width, height, 0, num_vpp_pipes, + lcu_size, HFI_CODEC_ENCODE_HEVC); + } + + return hfi_buffer_line_enc_vpu33(width, height, 0, num_vpp_pipes, + lcu_size, HFI_CODEC_ENCODE_AVC); +} + static inline u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit) { @@ -1387,7 +1454,7 @@ struct iris_vpu_buf_type_handle { u32 (*handle)(struct iris_inst *inst); }; =20 -int iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type) +u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type) { const struct iris_vpu_buf_type_handle *buf_type_handle_arr =3D NULL; u32 size =3D 0, buf_type_handle_size =3D 0, i; @@ -1431,6 +1498,34 @@ int iris_vpu_buf_size(struct iris_inst *inst, enum i= ris_buffer_type buffer_type) return size; } =20 +u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type) +{ + u32 size =3D 0, i; + + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_enc_bin_size }, + {BUF_COMV, iris_vpu_enc_comv_size }, + {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, + {BUF_LINE, iris_vpu33_enc_line_size }, + {BUF_ARP, iris_vpu_enc_arp_size }, + {BUF_VPSS, iris_vpu_enc_vpss_size }, + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, + }; + + if (inst->domain =3D=3D DECODER) + return iris_vpu_buf_size(inst, buffer_type); + + for (i =3D 0; i < ARRAY_SIZE(enc_internal_buf_type_handle); i++) { + if (enc_internal_buf_type_handle[i].type =3D=3D buffer_type) { + size =3D enc_internal_buf_type_handle[i].handle(inst); + break; + } + } + + return size; +} + static u32 internal_buffer_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 94668c5b3d15fb6e10d0b5ed6ed704cadb5a6534..04f0b7400a1e4e1d274d690a276= 1b9e57778e8b7 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -146,7 +146,8 @@ static inline u32 size_h264d_qp(u32 frame_width, u32 fr= ame_height) return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 1= 28; } =20 -int iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type); +u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type); +u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buff= er_type); int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffe= r_type); =20 #endif --- base-commit: 58717ecfffd642c1e0950dee4a247dd6cdfeb31e change-id: 20250822-topic-sm8x50-iris-encoder-v3-hevc-debug-10173f4838e3 Best regards, --=20 Neil Armstrong