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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32a698ad4c1sm1875866a91.5.2025.09.02.16.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 16:00:24 -0700 (PDT) From: DEEPA GUTHYAPPA MADIVALARA Date: Tue, 02 Sep 2025 16:00:03 -0700 Subject: [PATCH RFC 1/5] media: uapi: videodev2: Add support for AV1 stateful decoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-rfc_split-v1-1-47307a70c061@oss.qualcomm.com> References: <20250902-rfc_split-v1-0-47307a70c061@oss.qualcomm.com> In-Reply-To: <20250902-rfc_split-v1-0-47307a70c061@oss.qualcomm.com> To: Mauro Carvalho Chehab , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Deepa Guthyappa Madivalara X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756854022; l=1406; i=deepa.madivalara@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=9diWrH9N5RpjQbMIIxnIo3abYGeeRjuqJqXrS6LtQxo=; b=S/rVnIQnSXBlMIwhSoKVKh+SSJ4WhN7bPVyO4tyCvtJ4Azh5w/8zXTzmXk3tGKXHuL/BkdfTt y61Mczn9I3kA/7rjvUwC/91aBUTic5oT9aySCENvh2aFKeA0EjtrSJ7 X-Developer-Key: i=deepa.madivalara@oss.qualcomm.com; a=ed25519; pk=MOEXgyokievn+bgpHdS6Ixh/KQYyS90z2mqIbQ822FQ= X-Authority-Analysis: v=2.4 cv=OemYDgTY c=1 sm=1 tr=0 ts=68b7770b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=azbmn2n0SzSwlCbfrkoA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: sn-rkpaE37cxKaEnfUC_IWLkH6aEXfhq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyNCBTYWx0ZWRfX+brBALHNxiq6 IwEgd735Oy4965eiYAkYpIyQBj5NamRAEDQNIvSSlO+n8yYpCHy7jUWEVYwUA1aZESdI7jDeNao dtsXjmeoNwYKWlsq2KLkaO3GxMLYC+5apvCd5b2QuL/JIfEX7Jl3hHymMzsRgnDARqF+HQdY1qH ThwY0I/LLAdRrAed1NDL4pxpdKGuz13Ey/KGKg5SbahwbVIMQl8/JwM5lSYh6CsBGuTbjVZnBgt uh1OR5K4FaFZOdGk0GkxQy1OBbgx2ug3ZPEx5elxu60bNeNou5agBjPK6EAWt9mQAm7/yL3yhLj KmYjlsNJ09kPiQpilvdkvwGOyyF/hYqpyLF9IsZ/QE8J10+6wEbdQIf/CdA/D7NptFndjb1zHM5 Z2XKK8Yl X-Proofpoint-ORIG-GUID: sn-rkpaE37cxKaEnfUC_IWLkH6aEXfhq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-02_08,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 clxscore=1011 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300024 Introduce a new pixel format, V4L2_PIX_FMT_AV1, to the Video4Linux2(V4L2) API. This format is intended for AV1 bitstreams in stateful decoding/encoding workflows. The fourcc code 'AV10' is used to distinguish this format from the existing V4L2_PIX_FMT_AV1_FRAME, which is used for stateless AV1 decoder implementation. Signed-off-by: DEEPA GUTHYAPPA MADIVALARA --- include/uapi/linux/videodev2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 3dd9fa45dde1066d52a68581625a39e7ec92c9b7..bff42a71c67b3f4b570dd6f3d25= 0f1bb482ec8ae 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -775,6 +775,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 pa= rsed slices */ #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC pa= rsed slices */ #define V4L2_PIX_FMT_AV1_FRAME v4l2_fourcc('A', 'V', '1', 'F') /* AV1 pars= ed frame */ +#define V4L2_PIX_FMT_AV1 v4l2_fourcc('A', 'V', '1', '0') /* AV1 (stat= eful) */ #define V4L2_PIX_FMT_SPK v4l2_fourcc('S', 'P', 'K', '0') /* Sorenson = Spark */ #define V4L2_PIX_FMT_RV30 v4l2_fourcc('R', 'V', '3', '0') /* RealVideo= 8 */ #define V4L2_PIX_FMT_RV40 v4l2_fourcc('R', 'V', '4', '0') /* RealVideo= 9 & 10 */ --=20 2.34.1 From nobody Fri Oct 3 08:48:15 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BF1F283FC5 for ; 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Signed-off-by: DEEPA GUTHYAPPA MADIVALARA --- drivers/media/v4l2-core/v4l2-ioctl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core= /v4l2-ioctl.c index 01cf52c3ea33e1a01e1b306036ba4e57ef5c95d0..d3ee7736b74b0f277d3208782e3= ac3282eca1e6b 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1542,6 +1542,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_QC10C: descr =3D "QCOM Compressed 10-bit Format"; brea= k; case V4L2_PIX_FMT_AJPG: descr =3D "Aspeed JPEG"; break; case V4L2_PIX_FMT_AV1_FRAME: descr =3D "AV1 Frame"; break; + case V4L2_PIX_FMT_AV1: descr =3D "AV1"; break; case V4L2_PIX_FMT_MT2110T: descr =3D "Mediatek 10bit Tile Mode"; break; case V4L2_PIX_FMT_MT2110R: descr =3D "Mediatek 10bit Raster Mode"; break; case V4L2_PIX_FMT_HEXTILE: descr =3D "Hextile Compressed Format"; break; --=20 2.34.1 From nobody Fri Oct 3 08:48:15 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8906F2820B9 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32a698ad4c1sm1875866a91.5.2025.09.02.16.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 16:00:25 -0700 (PDT) From: DEEPA GUTHYAPPA MADIVALARA Date: Tue, 02 Sep 2025 16:00:05 -0700 Subject: [PATCH RFC 3/5] media: iris: Add support for AV1 format in iris decoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-rfc_split-v1-3-47307a70c061@oss.qualcomm.com> References: <20250902-rfc_split-v1-0-47307a70c061@oss.qualcomm.com> In-Reply-To: <20250902-rfc_split-v1-0-47307a70c061@oss.qualcomm.com> To: Mauro Carvalho Chehab , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Deepa Guthyappa Madivalara X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756854022; l=7441; i=deepa.madivalara@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=Kx47orXPGexZaP8p+2+3rbgEdZzv/9NvxjGLCgl4yW8=; b=h/+rtfZUH/8/HR6GweeAAXpPh4PtkD34iLLBM1hgfPt/HS3x74Oldmba/GvyZcEI8MUpB8DHb pnaxJ2AxqCPAA50fgDxCTjwFubGpbAup10T5fs6VrwajW8noJHQylzs X-Developer-Key: i=deepa.madivalara@oss.qualcomm.com; a=ed25519; pk=MOEXgyokievn+bgpHdS6Ixh/KQYyS90z2mqIbQ822FQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTAyMDAyNCBTYWx0ZWRfXywpwaRHxIyMR SJeFgLhIcym8z1FYNOqJBRCC7mQIl7V03s+8OWnuggpyBrOa+lmVXYv7sxsqRGTqu6WNaalghwe /wdrDZDzkLFiQ+BIvi1OHsMyRpYz3N2BfnFpRfrqgLGsIykAuBtDhUWq6ksIUCi9duBieBM71ir 43SKPW2W+hiRH3wBR75EnfQ1y/9A1tkxHsVWQ2ZtPQWd48vuNvvG/4r2Bxy0HZ6k5ZEta3j8N5A 96XGOT/sNYrP0iCq5hcSv4CvNnZiUXmWhF+03SGwSWjy6JiWMqJwX1/bbd/TYB6tbbIZz59eh/i dWgYUIEw4MgBxZpoxBGcGl1AqOpbLV/mCB3rvf3WlbLluNJM5G9OlHTlyfKzVd+TBZf0mO+dQ8K PWGVMDdA X-Authority-Analysis: v=2.4 cv=WKh/XmsR c=1 sm=1 tr=0 ts=68b7770c cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=Z_4drlmlzYXD-T4lrkMA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: p5CZq0E-9t94c2tomhhTcbhPPUah4TpV X-Proofpoint-ORIG-GUID: p5CZq0E-9t94c2tomhhTcbhPPUah4TpV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-02_08,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509020024 Extend iris decoder driver to support format V4L2_PIX_FMT_AV1. This change updates the format enumeration (VIDIOC_ENUM_FMT) and allows setting AV1 format via VIDIOC_S_FMT for gen2 and beyond. Gen1 iris hardware decoder does not support AV1 format. Signed-off-by: DEEPA GUTHYAPPA MADIVALARA --- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 1 + drivers/media/platform/qcom/iris/iris_instance.h | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 ++ .../media/platform/qcom/iris/iris_platform_gen2.c | 23 ++++++++++++++++++= ++ .../platform/qcom/iris/iris_platform_sm8250.c | 17 +++++++++++++++ drivers/media/platform/qcom/iris/iris_vdec.c | 25 ++++++------------= ---- 6 files changed, 50 insertions(+), 19 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index aa1f795f5626c1f76a32dd650302633877ce67be..bbfe7a0851ea94fb7041a868b4d= f8b2ec63bf427 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -138,6 +138,7 @@ enum hfi_codec_type { HFI_CODEC_DECODE_HEVC =3D 3, HFI_CODEC_ENCODE_HEVC =3D 4, HFI_CODEC_DECODE_VP9 =3D 5, + HFI_CODEC_DECODE_AV1 =3D 7, }; =20 enum hfi_picture_type { diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 5982d7adefeab80905478b32cddba7bd4651a691..f1883ffc138fd975fb76d4e4590= 4ee04e196cd20 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -19,6 +19,7 @@ enum iris_fmt_type { IRIS_FMT_H264, IRIS_FMT_HEVC, IRIS_FMT_VP9, + IRIS_FMT_AV1, }; =20 struct iris_fmt { diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 96fa7b1bb592441e85664da408ea4ba42c9a15b5..99057a624cb976af68403ef0421= 73b5ebefde8af 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -208,6 +208,8 @@ struct iris_platform_data { u64 dma_mask; const char *fwname; u32 pas_id; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index cf4b92f534b272a0a1ac2a0e7bb9316501374332..fecf2e06f19723f30777c04bc4b= 155954c2b746d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -16,6 +16,25 @@ #define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 =20 +static struct iris_fmt platform_fmts_sm8550_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] =3D { + .pixfmt =3D V4L2_PIX_FMT_AV1, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + } +}; + static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, @@ -756,6 +775,8 @@ struct iris_platform_data sm8550_data =3D { .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4.mbn", .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), @@ -847,6 +868,8 @@ struct iris_platform_data sm8650_data =3D { .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu33_p4.mbn", .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 978d0130d43b5f6febb65430a9bbe3932e8f24df..947dd25a483a792681e34fbbf43= 96342db582203 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -16,6 +16,21 @@ #define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 =20 +static struct iris_fmt platform_fmts_sm8250_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + } +}; + static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, @@ -335,6 +350,8 @@ struct iris_platform_data sm8250_data =3D { .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu-1.0/venus.mbn", .pas_id =3D IRIS_PAS_ID, + .inst_iris_fmts =3D platform_fmts_sm8250_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index ae13c3e1b426bfd81a7b46dc6c3ff5eb5c4860cb..be8d2d48c82f385e4f46807f7e0= dd52e469927cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -67,26 +67,12 @@ void iris_vdec_inst_deinit(struct iris_inst *inst) kfree(inst->fmt_src); } =20 -static const struct iris_fmt iris_vdec_formats[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32a698ad4c1sm1875866a91.5.2025.09.02.16.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 16:00:27 -0700 (PDT) From: DEEPA GUTHYAPPA MADIVALARA Date: Tue, 02 Sep 2025 16:00:06 -0700 Subject: [PATCH RFC 4/5] media: iris: Add internal buffer calculation for AV1 decoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-rfc_split-v1-4-47307a70c061@oss.qualcomm.com> References: <20250902-rfc_split-v1-0-47307a70c061@oss.qualcomm.com> In-Reply-To: <20250902-rfc_split-v1-0-47307a70c061@oss.qualcomm.com> To: Mauro Carvalho Chehab , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Deepa Guthyappa Madivalara X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756854022; l=31184; i=deepa.madivalara@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=MtqdUdwkgU4uuLVhGLd9AUT/UNS6j0VtVarwIeXOgic=; b=wlMPsBYbyxLVMf7kTn+nVm40X11MiKa2dYbqIo/E3oDbnS8s+pLyCFJpDjkCtJCtohS/KXnkS kiImxZUj12bBqCjbQeDIn2lCIOoTdeGTLTexxdmf/3YaN7DjVNe5kIj X-Developer-Key: i=deepa.madivalara@oss.qualcomm.com; a=ed25519; pk=MOEXgyokievn+bgpHdS6Ixh/KQYyS90z2mqIbQ822FQ= X-Proofpoint-ORIG-GUID: ryfe9kE4KtedQ5ZwDrhUoqZhYyA-DUwK X-Proofpoint-GUID: ryfe9kE4KtedQ5ZwDrhUoqZhYyA-DUwK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAyMCBTYWx0ZWRfX2zbV6L8irKlZ FcqlUj2I/1q6uvrWmuqi1x89gSY+ER7WhK54dgyQnzZNOwGb8iDpvvpL+lQjI2zHGPSG2ANAyNh XlBStPIEmet5f8v9YX5Up7ntVXwM57kx+EwVxUSDDOxlKSBSTEC4F7rYK8/EX7TV9MFHxA2If0Q OXgiDXD84ojQSSsNvv52JfECB4xKjeKQjtEn/jBJHhxjFjuVIR5GtNLmA0iHUQwcb7ifwkEVqPR ptVqN59K/5IWeP8Lzeu8epdD5PVtops+0peet6kK2j6mJAAo8SE3wPQFqU9j0WhOiLTGW2BmzgM CWZViH6F3SidAlXpvM45ymOWhgaAC9rhDQB02QcLWt0F8kienL6qEOdvGPj/CUmVoxKc4fpvdWy sWKS7Y0O X-Authority-Analysis: v=2.4 cv=VNndn8PX c=1 sm=1 tr=0 ts=68b7770f cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=11GS5pW4onBLkL3II1EA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-02_08,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300020 Implement internal buffer count and size calculations for AV1 decoder. Signed-off-by: DEEPA GUTHYAPPA MADIVALARA --- drivers/media/platform/qcom/iris/iris_buffer.h | 2 + .../platform/qcom/iris/iris_hfi_gen2_command.c | 109 ++++++++- .../platform/qcom/iris/iris_hfi_gen2_response.c | 3 + .../media/platform/qcom/iris/iris_platform_gen2.c | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 255 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 105 +++++++++ 7 files changed, 468 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.h b/drivers/media= /platform/qcom/iris/iris_buffer.h index 325d30fce5c99185b61ff989fbfd4de9a56762b2..75bb767761824c4c02e0df9b765= 896cc093be333 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_buffer.h @@ -27,6 +27,7 @@ struct iris_inst; * @BUF_SCRATCH_1: buffer to store decoding/encoding context data for HW * @BUF_SCRATCH_2: buffer to store encoding context data for HW * @BUF_VPSS: buffer to store VPSS context data for HW + * @BUF_PARTIAL: buffer for AV1 IBC data * @BUF_TYPE_MAX: max buffer types */ enum iris_buffer_type { @@ -42,6 +43,7 @@ enum iris_buffer_type { BUF_SCRATCH_1, BUF_SCRATCH_2, BUF_VPSS, + BUF_PARTIAL, BUF_TYPE_MAX, }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 4ce71a14250832440099e4cf3835b4aedfb749e8..e3a8b031b3f191a6d18e1084db3= 4804a8172439c 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -10,6 +10,7 @@ =20 #define UNSPECIFIED_COLOR_FORMAT 5 #define NUM_SYS_INIT_PACKETS 8 +#define NUM_COMV_AV1 18 =20 #define SYS_INIT_PKT_SIZE (sizeof(struct iris_hfi_header) + \ NUM_SYS_INIT_PACKETS * (sizeof(struct iris_hfi_packet) + sizeof(u32))) @@ -121,6 +122,7 @@ static u32 iris_hfi_gen2_get_port_from_buf_type(struct = iris_inst *inst, case BUF_COMV: case BUF_NON_COMV: case BUF_LINE: + case BUF_PARTIAL: return HFI_PORT_BITSTREAM; case BUF_OUTPUT: case BUF_DPB: @@ -380,6 +382,9 @@ static int iris_hfi_gen2_set_profile(struct iris_inst *= inst, u32 plane) case V4L2_PIX_FMT_H264: profile =3D inst->fw_caps[PROFILE_H264].value; break; + case V4L2_PIX_FMT_AV1: + profile =3D inst->fw_caps[PROFILE_AV1].value; + break; } =20 inst_hfi_gen2->src_subcr_params.profile =3D profile; @@ -409,6 +414,9 @@ static int iris_hfi_gen2_set_level(struct iris_inst *in= st, u32 plane) case V4L2_PIX_FMT_H264: level =3D inst->fw_caps[LEVEL_H264].value; break; + case V4L2_PIX_FMT_AV1: + level =3D inst->fw_caps[LEVEL_AV1].value; + break; } =20 inst_hfi_gen2->src_subcr_params.level =3D level; @@ -484,7 +492,8 @@ static int iris_hfi_gen2_set_tier(struct iris_inst *ins= t, u32 plane) u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); u32 tier =3D inst->fw_caps[TIER].value; =20 - inst_hfi_gen2->src_subcr_params.tier =3D tier; + tier =3D (inst->codec =3D=3D V4L2_PIX_FMT_AV1) ? inst->fw_caps[TIER_AV1].= value : + inst->fw_caps[TIER].value; =20 return iris_hfi_gen2_session_set_property(inst, HFI_PROP_TIER, @@ -509,6 +518,56 @@ static int iris_hfi_gen2_set_frame_rate(struct iris_in= st *inst, u32 plane) sizeof(u32)); } =20 +static int iris_hfi_gen2_set_film_grain(struct iris_inst *inst, u32 plane) +{ + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 film_grain; + + film_grain =3D inst->fw_caps[FILM_GRAIN].value; + inst_hfi_gen2->src_subcr_params.film_grain =3D film_grain; + + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_U32_ENUM, + &film_grain, + sizeof(u32)); +} + +static int iris_hfi_gen2_set_super_block(struct iris_inst *inst, u32 plane) +{ + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 super_block; + + super_block =3D inst->fw_caps[SUPER_BLOCK].value; + inst_hfi_gen2->src_subcr_params.super_block =3D super_block; + + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_U32_ENUM, + &super_block, + sizeof(u32)); +} + +static int iris_hfi_gen2_set_opb_enable(struct iris_inst *inst, u32 plane) +{ + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPL= ANE); + u32 opb_enable =3D iris_split_mode_enabled(inst); + + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_OPB_ENABLE, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_U32, + &opb_enable, + sizeof(u32)); +} + static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst,= u32 plane) { const struct iris_platform_data *pdata =3D inst->core->iris_platform_data; @@ -531,6 +590,9 @@ static int iris_hfi_gen2_session_set_config_params(stru= ct iris_inst *inst, u32 p {HFI_PROP_LINEAR_STRIDE_SCANLINE, iris_hfi_gen2_set_linear_stride_sc= anline }, {HFI_PROP_TIER, iris_hfi_gen2_set_tier = }, {HFI_PROP_FRAME_RATE, iris_hfi_gen2_set_frame_rate = }, + {HFI_PROP_AV1_FILM_GRAIN_PRESENT, iris_hfi_gen2_set_film_grain = }, + {HFI_PROP_AV1_SUPER_BLOCK_ENABLED, iris_hfi_gen2_set_super_block = }, + {HFI_PROP_OPB_ENABLE, iris_hfi_gen2_set_opb_enable = }, }; =20 if (inst->domain =3D=3D DECODER) { @@ -544,12 +606,20 @@ static int iris_hfi_gen2_session_set_config_params(st= ruct iris_inst *inst, u32 p } else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) { config_params =3D pdata->dec_input_config_params_vp9; config_params_size =3D pdata->dec_input_config_params_vp9_size; + } else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + config_params =3D pdata->dec_input_config_params_av1; + config_params_size =3D pdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params =3D pdata->dec_output_config_params; - config_params_size =3D pdata->dec_output_config_params_size; + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + config_params =3D pdata->dec_output_config_params_av1; + config_params_size =3D pdata->dec_output_config_params_av1_size; + } else { + config_params =3D pdata->dec_output_config_params; + config_params_size =3D pdata->dec_output_config_params_size; + } } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { @@ -598,6 +668,9 @@ static int iris_hfi_gen2_session_set_codec(struct iris_= inst *inst) break; case V4L2_PIX_FMT_VP9: codec =3D HFI_CODEC_DECODE_VP9; + break; + case V4L2_PIX_FMT_AV1: + codec =3D HFI_CODEC_DECODE_AV1; } =20 iris_hfi_gen2_packet_session_property(inst, @@ -763,6 +836,11 @@ static int iris_hfi_gen2_subscribe_change_param(struct= iris_inst *inst, u32 plan change_param_size =3D core->iris_platform_data->dec_input_config_params_vp9_size; break; + case V4L2_PIX_FMT_AV1: + change_param =3D core->iris_platform_data->dec_input_config_params_av1; + change_param_size =3D + core->iris_platform_data->dec_input_config_params_av1_size; + break; } =20 payload[0] =3D HFI_MODE_PORT_SETTINGS_CHANGE; @@ -845,6 +923,16 @@ static int iris_hfi_gen2_subscribe_change_param(struct= iris_inst *inst, u32 plan payload_size =3D sizeof(u32); payload_type =3D HFI_PAYLOAD_U32; break; + case HFI_PROP_AV1_FILM_GRAIN_PRESENT: + payload[0] =3D subsc_params.film_grain; + payload_size =3D sizeof(u32); + payload_type =3D HFI_PAYLOAD_U32; + break; + case HFI_PROP_AV1_SUPER_BLOCK_ENABLED: + payload[0] =3D subsc_params.super_block; + payload_size =3D sizeof(u32); + payload_type =3D HFI_PAYLOAD_U32; + break; default: prop_type =3D 0; ret =3D -EINVAL; @@ -900,6 +988,11 @@ static int iris_hfi_gen2_subscribe_property(struct iri= s_inst *inst, u32 plane) subscribe_prop_size =3D core->iris_platform_data->dec_output_prop_vp9_size; break; + case V4L2_PIX_FMT_AV1: + subcribe_prop =3D core->iris_platform_data->dec_output_prop_av1; + subscribe_prop_size =3D + core->iris_platform_data->dec_output_prop_av1_size; + break; } } =20 @@ -1075,6 +1168,8 @@ static u32 iris_hfi_gen2_buf_type_from_driver(u32 dom= ain, enum iris_buffer_type return HFI_BUFFER_ARP; case BUF_VPSS: return HFI_BUFFER_VPSS; + case BUF_PARTIAL: + return HFI_BUFFER_PARTIAL_DATA; default: return 0; } @@ -1087,7 +1182,13 @@ static int iris_set_num_comv(struct iris_inst *inst) u32 num_comv; =20 caps =3D core->iris_platform_data->inst_caps; - num_comv =3D caps->num_comv; + + /* + * If Host allocates less comv count for AV1 then + * FW can raise SESSION_ERROR + */ + num_comv =3D (inst->codec =3D=3D V4L2_PIX_FMT_AV1) ? + NUM_COMV_AV1 : caps->num_comv; =20 return core->hfi_ops->session_set_property(inst, HFI_PROP_COMV_BUFFER_COUNT, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 2f1f118eae4f6462ab1aa1d16844b34e6e699f1e..943d3884248fafccc3b8e944e45= 5c96124914353 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -54,6 +54,8 @@ static u32 iris_hfi_gen2_buf_type_to_driver(struct iris_i= nst *inst, return BUF_SCRATCH_2; case HFI_BUFFER_PERSIST: return BUF_PERSIST; + case HFI_BUFFER_PARTIAL_DATA: + return BUF_PARTIAL; default: return 0; } @@ -72,6 +74,7 @@ static bool iris_hfi_gen2_is_valid_hfi_buffer_type(u32 bu= ffer_type) case HFI_BUFFER_DPB: case HFI_BUFFER_PERSIST: case HFI_BUFFER_VPSS: + case HFI_BUFFER_PARTIAL_DATA: return true; default: return false; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index fecf2e06f19723f30777c04bc4b155954c2b746d..c0a03c03bb9349a0e551ce6dc72= b6f8b23ff696d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -739,6 +739,7 @@ static const u32 sm8550_dec_ip_int_buf_tbl[] =3D { BUF_COMV, BUF_NON_COMV, BUF_LINE, + BUF_PARTIAL, }; =20 static const u32 sm8550_dec_op_int_buf_tbl[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 798c3613e57eac1742633d61c1482229dbc32562..43a77687a668423a5547c7f1596= 22249634264e0 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -178,6 +178,7 @@ int iris_open(struct file *filp) INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_1].list); INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_2].list); INIT_LIST_HEAD(&inst->buffers[BUF_VPSS].list); + INIT_LIST_HEAD(&inst->buffers[BUF_PARTIAL].list); init_completion(&inst->completion); init_completion(&inst->flush_completion); =20 diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 7337d8d33715810669399d9f86b864d0eb002897..cfdd28f005986d5b14b18a97215= 933b171355f7a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -9,6 +9,14 @@ #include "iris_hfi_gen2_defines.h" =20 #define HFI_MAX_COL_FRAME 6 +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_HEIGHT (8) +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH (32) +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_HEIGHT (8) +#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_WIDTH (16) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_HEIGHT (4) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH (48) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_HEIGHT (4) +#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_WIDTH (24) =20 #ifndef SYSTEM_LAL_TILE10 #define SYSTEM_LAL_TILE10 192 @@ -39,6 +47,31 @@ static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 fra= me_height, u32 num_vpp_p return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); } =20 +static u32 size_av1d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 = num_vpp_pipes) +{ + u32 size_yuv, size_bin_hdr, size_bin_res; + + size_yuv =3D ((frame_width * frame_height) <=3D BIN_BUFFER_THRESHOLD) ? + ((BIN_BUFFER_THRESHOLD * 3) >> 1) : + ((frame_width * frame_height * 3) >> 1); + size_bin_hdr =3D size_yuv * AV1_CABAC_HDR_RATIO_HD_TOT; + size_bin_res =3D size_yuv * AV1_CABAC_RES_RATIO_HD_TOT; + size_bin_hdr =3D ALIGN(size_bin_hdr / num_vpp_pipes, + DMA_ALIGNMENT) * num_vpp_pipes; + size_bin_res =3D ALIGN(size_bin_res / num_vpp_pipes, + DMA_ALIGNMENT) * num_vpp_pipes; + + return size_bin_hdr + size_bin_res; +} + +static u32 hfi_buffer_bin_av1d(u32 frame_width, u32 frame_height, u32 num_= vpp_pipes) +{ + u32 n_aligned_h =3D ALIGN(frame_height, 16); + u32 n_aligned_w =3D ALIGN(frame_width, 16); + + return size_av1d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); +} + static u32 size_h265d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32= num_vpp_pipes) { u32 product =3D frame_width * frame_height; @@ -110,6 +143,20 @@ static u32 hfi_buffer_comv_h265d(u32 frame_width, u32 = frame_height, u32 _comv_bu return (_size * (_comv_bufcount)) + 512; } =20 +static u32 hfi_buffer_comv_av1d(u32 frame_width, u32 frame_height, u32 com= v_bufcount) +{ + u32 size; + + size =3D 2 * ALIGN(MAX(((frame_width + 63) / 64) * + ((frame_height + 63) / 64) * 512, + ((frame_width + 127) / 128) * + ((frame_height + 127) / 128) * 2816), + DMA_ALIGNMENT); + size *=3D comv_bufcount; + + return size; +} + static u32 size_h264d_bse_cmd_buf(u32 frame_height) { u32 height =3D ALIGN(frame_height, 32); @@ -174,6 +221,20 @@ static u32 hfi_buffer_persist_h264d(void) DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_persist_av1d(u32 max_width, u32 max_height, u32 tota= l_ref_count) +{ + u32 comv_size, size; + + comv_size =3D hfi_buffer_comv_av1d(max_width, max_height, total_ref_coun= t); + size =3D ALIGN((SIZE_AV1D_SEQUENCE_HEADER * 2 + SIZE_AV1D_METADATA + + AV1D_NUM_HW_PIC_BUF * (SIZE_AV1D_TILE_OFFSET + SIZE_AV1D_QM) + + AV1D_NUM_FRAME_HEADERS * (SIZE_AV1D_FRAME_HEADER + + 2 * SIZE_AV1D_PROB_TABLE) + comv_size + HDR10_HIST_EXTRADATA_SIZE + + SIZE_AV1D_METADATA * AV1D_NUM_HW_PIC_BUF), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u3= 2 num_vpp_pipes) { u32 size_bse =3D size_h264d_bse_cmd_buf(frame_height); @@ -459,6 +520,148 @@ static u32 hfi_buffer_line_h264d(u32 frame_width, u32= frame_height, return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT); } =20 +static u32 size_av1d_lb_opb_wr1_nv12_ubwc(u32 frame_width, u32 frame_heigh= t) +{ + u32 y_width, y_width_a =3D 128; + + y_width =3D ALIGN(frame_width, y_width_a); + + return (256 * ((y_width + 31) / 32 + (AV1D_MAX_TILE_COLS - 1))); +} + +static u32 size_av1d_lb_opb_wr1_tp10_ubwc(u32 frame_width, u32 frame_heigh= t) +{ + u32 y_width, y_width_a =3D 256; + + y_width =3D ALIGN(frame_width, 192); + y_width =3D ALIGN(y_width * 4 / 3, y_width_a); + + return (256 * ((y_width + 47) / 48 + (AV1D_MAX_TILE_COLS - 1))); +} + +static u32 hfi_buffer_line_av1d(u32 frame_width, u32 frame_height, + bool is_opb, u32 num_vpp_pipes) +{ + u32 size, vpss_lb_size, opbwrbufsize, opbwr8, opbwr10; + + size =3D ALIGN(size_av1d_lb_fe_top_data(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_fe_top_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_fe_left_data(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_av1d_lb_fe_left_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_av1d_lb_se_left_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_av1d_lb_se_top_ctrl(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_pe_top_data(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_vsp_top(frame_width, frame_height), + DMA_ALIGNMENT) + + ALIGN(size_av1d_lb_recon_dma_metadata_wr + (frame_width, frame_height), DMA_ALIGNMENT) * 2 + + ALIGN(size_av1d_qp(frame_width, frame_height), DMA_ALIGNMENT); + opbwr8 =3D size_av1d_lb_opb_wr1_nv12_ubwc(frame_width, frame_height); + opbwr10 =3D size_av1d_lb_opb_wr1_tp10_ubwc(frame_width, frame_height); + opbwrbufsize =3D opbwr8 >=3D opbwr10 ? opbwr8 : opbwr10; + size =3D ALIGN((size + opbwrbufsize), DMA_ALIGNMENT); + if (is_opb) { + size_vpss_lb(frame_width, frame_height); + size =3D ALIGN((size + vpss_lb_size) * 2, DMA_ALIGNMENT); + } + + return size; +} + +static u32 size_av1d_ibc_nv12_ubwc(u32 frame_width, u32 frame_height) +{ + u32 size; + u32 y_width_a =3D 128, y_height_a =3D 32; + u32 uv_width_a =3D 128, uv_height_a =3D 32; + u32 ybufsize, uvbufsize, y_width, y_height, uv_width, uv_height; + u32 y_meta_width_a =3D 64, y_meta_height_a =3D 16; + u32 uv_meta_width_a =3D 64, uv_meta_height_a =3D 16; + u32 meta_height, meta_stride, meta_size; + u32 tile_width_y =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH; + u32 tile_height_y =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_HEIGHT; + u32 tile_width_uv =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_WIDTH; + u32 tile_height_uv =3D HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_HEIGHT; + + y_width =3D ALIGN(frame_width, y_width_a); + y_height =3D ALIGN(frame_height, y_height_a); + uv_width =3D ALIGN(frame_width, uv_width_a); + uv_height =3D ALIGN(((frame_height + 1) >> 1), uv_height_a); + ybufsize =3D ALIGN((y_width * y_height), HFI_ALIGNMENT_4096); + uvbufsize =3D ALIGN(uv_width * uv_height, HFI_ALIGNMENT_4096); + size =3D ybufsize + uvbufsize; + meta_stride =3D ALIGN(((frame_width + (tile_width_y - 1)) / tile_width_y), + y_meta_width_a); + meta_height =3D ALIGN(((frame_height + (tile_height_y - 1)) / tile_height= _y), + y_meta_height_a); + meta_size =3D ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096); + size +=3D meta_size; + meta_stride =3D ALIGN(((((frame_width + 1) >> 1) + (tile_width_uv - 1)) / + tile_width_uv), uv_meta_width_a); + meta_height =3D ALIGN(((((frame_height + 1) >> 1) + (tile_height_uv - 1))= / + tile_height_uv), uv_meta_height_a); + meta_size =3D ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096); + size +=3D meta_size; + + return size; +} + +static u32 size_av1d_ibc_tp10_ubwc(u32 frame_width, u32 frame_height) +{ + u32 size; + u32 y_width_a =3D 256, y_height_a =3D 16, + uv_width_a =3D 256, uv_height_a =3D 16; + u32 ybufsize, uvbufsize, y_width, y_height, uv_width, uv_height; + u32 y_meta_width_a =3D 64, y_meta_height_a =3D 16, + uv_meta_width_a =3D 64, uv_meta_height_a =3D 16; + u32 meta_height, meta_stride, meta_size; + u32 tile_width_y =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH; + u32 tile_height_y =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_HEIGHT; + u32 tile_width_uv =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_WIDTH; + u32 tile_height_uv =3D HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_HEIGHT; + + y_width =3D ALIGN(frame_width, 192); + y_width =3D ALIGN(y_width * 4 / 3, y_width_a); + y_height =3D ALIGN(frame_height, y_height_a); + uv_width =3D ALIGN(frame_width, 192); + uv_width =3D ALIGN(uv_width * 4 / 3, uv_width_a); + uv_height =3D ALIGN(((frame_height + 1) >> 1), uv_height_a); + ybufsize =3D ALIGN(y_width * y_height, HFI_ALIGNMENT_4096); + uvbufsize =3D ALIGN(uv_width * uv_height, HFI_ALIGNMENT_4096); + size =3D ybufsize + uvbufsize; + meta_stride =3D ALIGN(((frame_width + (tile_width_y - 1)) / tile_width_y), + y_meta_width_a); + meta_height =3D ALIGN(((frame_height + (tile_height_y - 1)) / tile_height= _y), + y_meta_height_a); + meta_size =3D ALIGN(((frame_height + (meta_height - 1)) / meta_height), m= eta_stride); + size +=3D meta_size; + meta_stride =3D ALIGN(((((frame_width + 1) >> 1) + (tile_width_uv - 1)) / + tile_width_uv), uv_meta_width_a); + meta_height =3D ALIGN(((((frame_height + 1) >> 1) + (tile_height_uv - 1))= / + tile_height_uv), uv_meta_height_a); + meta_size =3D ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096); + size +=3D meta_size; + + return size; +} + +static u32 hfi_buffer_ibc_av1d(u32 frame_width, u32 frame_height) +{ + u32 size, ibc8, ibc10; + + ibc8 =3D size_av1d_ibc_nv12_ubwc(frame_width, frame_height); + ibc10 =3D size_av1d_ibc_tp10_ubwc(frame_width, frame_height); + size =3D ibc8 >=3D ibc10 ? ibc8 : ibc10; + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 iris_vpu_dec_bin_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; @@ -472,6 +675,8 @@ static u32 iris_vpu_dec_bin_size(struct iris_inst *inst) return hfi_buffer_bin_h265d(width, height, num_vpp_pipes); else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) return hfi_buffer_bin_vp9d(width, height, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return hfi_buffer_bin_av1d(width, height, num_vpp_pipes); =20 return 0; } @@ -487,18 +692,33 @@ static u32 iris_vpu_dec_comv_size(struct iris_inst *i= nst) return hfi_buffer_comv_h264d(width, height, num_comv); else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) return hfi_buffer_comv_h265d(width, height, num_comv); - + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + if (inst->fw_caps[DRAP].value) + return 0; + else + return hfi_buffer_comv_av1d(width, height, num_comv); + } return 0; } =20 static u32 iris_vpu_dec_persist_size(struct iris_inst *inst) { + struct platform_inst_caps *caps; + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) return hfi_buffer_persist_h264d(); else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) return hfi_buffer_persist_h265d(0); else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) return hfi_buffer_persist_vp9d(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + caps =3D inst->core->iris_platform_data->inst_caps; + if (inst->fw_caps[DRAP].value) + return hfi_buffer_persist_av1d(caps->max_frame_width, + caps->max_frame_height, 16); + else + return hfi_buffer_persist_av1d(0, 0, 0); + } =20 return 0; } @@ -545,6 +765,8 @@ static u32 iris_vpu_dec_line_size(struct iris_inst *ins= t) else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) return hfi_buffer_line_vp9d(width, height, out_min_count, is_opb, num_vpp_pipes); + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return hfi_buffer_line_av1d(width, height, is_opb, num_vpp_pipes); =20 return 0; } @@ -556,6 +778,15 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_inst= *inst) iris_vpu_dec_line_size(inst); } =20 +static u32 iris_vpu_dec_partial_size(struct iris_inst *inst) +{ + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + return hfi_buffer_ibc_av1d(width, height); +} + static inline u32 size_enc_single_pipe(u32 rc_type, u32 bitbin_size, u32 num_vpp_pipes, u32 frame_width, u32 frame_height, u32 lcu_size) @@ -1369,7 +1600,9 @@ static int output_min_count(struct iris_inst *inst) =20 /* fw_min_count > 0 indicates reconfig event has already arrived */ if (inst->fw_min_count) { - if (iris_split_mode_enabled(inst) && inst->codec =3D=3D V4L2_PIX_FMT_VP9) + if (iris_split_mode_enabled(inst) && + (inst->codec =3D=3D V4L2_PIX_FMT_VP9 || + inst->codec =3D=3D V4L2_PIX_FMT_VP9)) return min_t(u32, 4, inst->fw_min_count); else return inst->fw_min_count; @@ -1377,6 +1610,8 @@ static int output_min_count(struct iris_inst *inst) =20 if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) output_min_count =3D 9; + else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + output_min_count =3D 11; =20 return output_min_count; } @@ -1399,6 +1634,7 @@ int iris_vpu_buf_size(struct iris_inst *inst, enum ir= is_buffer_type buffer_type) {BUF_PERSIST, iris_vpu_dec_persist_size }, {BUF_DPB, iris_vpu_dec_dpb_size }, {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, + {BUF_PARTIAL, iris_vpu_dec_partial_size }, }; =20 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { @@ -1437,14 +1673,20 @@ static u32 internal_buffer_count(struct iris_inst *= inst, buffer_type =3D=3D BUF_PERSIST) { return 1; } else if (buffer_type =3D=3D BUF_COMV || buffer_type =3D=3D BUF_NON_COMV= ) { - if (inst->codec =3D=3D V4L2_PIX_FMT_H264 || inst->codec =3D=3D V4L2_PIX_= FMT_HEVC) + if (inst->codec =3D=3D V4L2_PIX_FMT_H264 || + inst->codec =3D=3D V4L2_PIX_FMT_HEVC || + inst->codec =3D=3D V4L2_PIX_FMT_AV1) return 1; } + return 0; } =20 static inline int iris_vpu_dpb_count(struct iris_inst *inst) { + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return 11; + if (iris_split_mode_enabled(inst)) { return inst->fw_min_count ? inst->fw_min_count : inst->buffers[BUF_OUTPUT].min_count; @@ -1463,9 +1705,13 @@ int iris_vpu_buf_count(struct iris_inst *inst, enum = iris_buffer_type buffer_type return MIN_BUFFERS; else return output_min_count(inst); + case BUF_NON_COMV: + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) + return 0; + else + return 1; case BUF_BIN: case BUF_COMV: - case BUF_NON_COMV: case BUF_LINE: case BUF_PERSIST: return internal_buffer_count(inst, buffer_type); @@ -1473,6 +1719,7 @@ int iris_vpu_buf_count(struct iris_inst *inst, enum i= ris_buffer_type buffer_type case BUF_SCRATCH_2: case BUF_VPSS: case BUF_ARP: + case BUF_PARTIAL: return 1; /* internal buffer count needed by firmware is 1 */ case BUF_DPB: return iris_vpu_dpb_count(inst); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 1ff1b07ecbaa85345ca948affeb1c4a1c55e36b0..71fb2a408797c3b5e2eb25222b2= dfd356f532d96 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -11,6 +11,7 @@ struct iris_inst; #define MIN_BUFFERS 4 =20 #define DMA_ALIGNMENT 256 +#define HFI_ALIGNMENT_4096 4096 =20 #define NUM_HW_PIC_BUF 32 #define LCU_MAX_SIZE_PELS 64 @@ -80,6 +81,22 @@ struct iris_inst; #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 =20 +#define AV1_CABAC_HDR_RATIO_HD_TOT 2 +#define AV1_CABAC_RES_RATIO_HD_TOT 2 +#define AV1D_LCU_MAX_SIZE_PELS 128 +#define AV1D_LCU_MIN_SIZE_PELS 64 +#define AV1D_MAX_TILE_COLS 64 +#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192 +#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96 +#define AV1D_NUM_HW_PIC_BUF 16 +#define AV1D_NUM_FRAME_HEADERS 16 +#define SIZE_AV1D_SEQUENCE_HEADER 768 +#define SIZE_AV1D_METADATA 512 +#define SIZE_AV1D_FRAME_HEADER 1280 +#define SIZE_AV1D_TILE_OFFSET 65536 +#define SIZE_AV1D_QM 3328 +#define SIZE_AV1D_PROB_TABLE 22784 + #define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256)) #define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096) #define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3) @@ -145,6 +162,94 @@ static inline u32 size_h264d_qp(u32 frame_width, u32 f= rame_height) return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 1= 28; } =20 +static inline u32 size_av1d_lb_fe_top_data(u32 frame_width, u32 frame_heig= ht) +{ + return (ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) * ((16 * 10) >> 3) + + ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 * ((16 * 6) >> 3) * 2); +} + +static inline u32 size_av1d_lb_fe_left_data(u32 frame_width, u32 frame_hei= ght) +{ + return (32 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 8) * 2 + + 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 12) * 2 + + 24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 16) + + 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 + + ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS * 12) * 2); +} + +static inline u32 size_av1d_lb_fe_top_ctrl(u32 frame_width, u32 frame_heig= ht) +{ + return (10 * ((frame_width + AV1D_LCU_MIN_SIZE_PELS - 1) / + AV1D_LCU_MIN_SIZE_PELS) * 128 / 8); +} + +static inline u32 size_av1d_lb_fe_left_ctrl(u32 frame_width, u32 frame_hei= ght) +{ + return (16 * ((ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 16) + + (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS)) + + 3 * 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / + AV1D_LCU_MIN_SIZE_PELS)); +} + +static inline u32 size_av1d_lb_se_top_ctrl(u32 frame_width, u32 frame_heig= ht) +{ + return (((frame_width + 7) / 8) * 16); +} + +static inline u32 size_av1d_lb_se_left_ctrl(u32 frame_width, u32 frame_hei= ght) +{ + return (max(((frame_height + 15) / 16) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, + max(((frame_height + 31) / 32) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, + ((frame_height + 63) / 64) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE))); +} + +static inline u32 size_av1d_lb_pe_top_data(u32 frame_width, u32 frame_heig= ht) +{ + return (max(((frame_width + 15) / 16) * + MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE, + max(((frame_width + 31) / 32) * + MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE, + ((frame_width + 63) / 64) * + MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE))); 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Set and subscribe to manadatory properties to firmware for AV1. Signed-off-by: DEEPA GUTHYAPPA MADIVALARA --- drivers/media/platform/qcom/iris/iris_ctrls.c | 8 ++ drivers/media/platform/qcom/iris/iris_hfi_common.h | 3 + .../platform/qcom/iris/iris_hfi_gen2_defines.h | 9 ++ .../platform/qcom/iris/iris_hfi_gen2_response.c | 19 +++ .../platform/qcom/iris/iris_platform_common.h | 13 ++ .../media/platform/qcom/iris/iris_platform_gen2.c | 132 +++++++++++++++++= +++- 6 files changed, 183 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 754a5ad718bc37630bb861012301df7a2e7342a1..620c7e1bd273e25febd8ca70dd1= dcfb0b862692b 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -98,6 +98,10 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(u3= 2 id) return B_FRAME_QP_H264; case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: return B_FRAME_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_AV1_PROFILE: + return PROFILE_AV1; + case V4L2_CID_MPEG_VIDEO_AV1_LEVEL: + return LEVEL_AV1; default: return INST_FW_CAP_MAX; } @@ -185,6 +189,10 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_= type cap_id) return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; case B_FRAME_QP_HEVC: return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; + case PROFILE_AV1: + return V4L2_CID_MPEG_VIDEO_AV1_PROFILE; + case LEVEL_AV1: + return V4L2_CID_MPEG_VIDEO_AV1_LEVEL; default: return 0; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index b51471fb32c70acee44c37f8e9dce0c6bc0b6ccc..3edb5ae582b49bea2e2408c4a5c= fc0a742adc05f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -141,6 +141,9 @@ struct hfi_subscription_params { u32 profile; u32 level; u32 tier; + u32 drap; + u32 film_grain; + u32 super_block; }; =20 u32 iris_hfi_get_v4l2_color_primaries(u32 hfi_primaries); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index bbfe7a0851ea94fb7041a868b4df8b2ec63bf427..9cc0989c67d74a9e051725e9ee5= 71a2ab9160519 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -89,9 +89,18 @@ enum hfi_seq_header_mode { #define HFI_PROP_DEC_START_FROM_RAP_FRAME 0x03000169 #define HFI_PROP_NO_OUTPUT 0x0300016a #define HFI_PROP_BUFFER_MARK 0x0300016c +#define HFI_PROP_WORST_COMPRESSION_RATIO 0x03000174 +#define HFI_PROP_WORST_COMPLEXITY_FACTOR 0x03000175 #define HFI_PROP_RAW_RESOLUTION 0x03000178 +#define HFI_PROP_AV1_FILM_GRAIN_PRESENT 0x03000180 +#define HFI_PROP_AV1_SUPER_BLOCK_ENABLED 0x03000181 +#define HFI_PROP_AV1_OP_POINT 0x03000182 +#define HFI_PROP_OPB_ENABLE 0x03000184 +#define HFI_PROP_AV1_TILE_ROWS_COLUMNS 0x03000187 +#define HFI_PROP_AV1_DRAP_CONFIG 0x03000189 #define HFI_PROP_TOTAL_PEAK_BITRATE 0x0300017C #define HFI_PROP_COMV_BUFFER_COUNT 0x03000193 +#define HFI_PROP_AV1_UNIFORM_TILE_SPACING 0x03000197 #define HFI_PROP_END 0x03FFFFFF =20 #define HFI_SESSION_ERROR_BEGIN 0x04000000 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 943d3884248fafccc3b8e944e455c96124914353..eb3373f0ad4a1b26fb847db0244= 9ec8d8cb3bdbb 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -599,6 +599,10 @@ static void iris_hfi_gen2_read_input_subcr_params(stru= ct iris_inst *inst) inst->fw_caps[PROFILE_H264].value =3D subsc_params.profile; inst->fw_caps[LEVEL_H264].value =3D subsc_params.level; break; + case V4L2_PIX_FMT_AV1: + inst->fw_caps[PROFILE_AV1].value =3D subsc_params.profile; + inst->fw_caps[LEVEL_AV1].value =3D subsc_params.level; + break; } =20 inst->fw_caps[POC].value =3D subsc_params.pic_order_cnt; @@ -611,6 +615,11 @@ static void iris_hfi_gen2_read_input_subcr_params(stru= ct iris_inst *inst) iris_inst_change_state(inst, IRIS_INST_ERROR); } =20 + if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { + inst->fw_caps[FILM_GRAIN].value =3D subsc_params.film_grain; + inst->fw_caps[SUPER_BLOCK].value =3D subsc_params.super_block; + } + inst->fw_min_count =3D subsc_params.fw_min_count; inst->buffers[BUF_OUTPUT].min_count =3D iris_vpu_buf_count(inst, BUF_OUTP= UT); inst->buffers[BUF_OUTPUT].size =3D pixmp_op->plane_fmt[0].sizeimage; @@ -714,6 +723,12 @@ static int iris_hfi_gen2_handle_session_property(struc= t iris_inst *inst, case HFI_PROP_NO_OUTPUT: inst_hfi_gen2->hfi_frame_info.no_output =3D 1; break; + case HFI_PROP_AV1_FILM_GRAIN_PRESENT: + inst_hfi_gen2->src_subcr_params.film_grain =3D pkt->payload[0]; + break; + case HFI_PROP_AV1_SUPER_BLOCK_ENABLED: + inst_hfi_gen2->src_subcr_params.super_block =3D pkt->payload[0]; + break; case HFI_PROP_QUALITY_MODE: case HFI_PROP_STAGE: case HFI_PROP_PIPE: @@ -844,6 +859,10 @@ static void iris_hfi_gen2_init_src_change_param(struct= iris_inst *inst) subsc_params->profile =3D inst->fw_caps[PROFILE_H264].value; subsc_params->level =3D inst->fw_caps[LEVEL_H264].value; break; + case V4L2_PIX_FMT_AV1: + subsc_params->profile =3D inst->fw_caps[PROFILE_AV1].value; + subsc_params->level =3D inst->fw_caps[LEVEL_AV1].value; + break; } =20 subsc_params->pic_order_cnt =3D inst->fw_caps[POC].value; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 99057a624cb976af68403ef042173b5ebefde8af..e543a3cc142b15e50b12cfe672d= 00dd0acfdb4d1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -95,6 +95,13 @@ enum platform_inst_fw_cap_type { LEVEL_H264, LEVEL_HEVC, LEVEL_VP9, + PROFILE_AV1, + LEVEL_AV1, + TIER_AV1, + DRAP, + FILM_GRAIN, + SUPER_BLOCK, + ENH_LAYER_COUNT, INPUT_BUF_HOST_MAX_COUNT, OUTPUT_BUF_HOST_MAX_COUNT, STAGE, @@ -231,8 +238,12 @@ struct iris_platform_data { unsigned int dec_input_config_params_hevc_size; const u32 *dec_input_config_params_vp9; unsigned int dec_input_config_params_vp9_size; + const u32 *dec_input_config_params_av1; + unsigned int dec_input_config_params_av1_size; const u32 *dec_output_config_params; unsigned int dec_output_config_params_size; + const u32 *dec_output_config_params_av1; + unsigned int dec_output_config_params_av1_size; const u32 *enc_input_config_params; unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; @@ -245,6 +256,8 @@ struct iris_platform_data { unsigned int dec_output_prop_hevc_size; const u32 *dec_output_prop_vp9; unsigned int dec_output_prop_vp9_size; + const u32 *dec_output_prop_av1; + unsigned int dec_output_prop_av1_size; const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index c0a03c03bb9349a0e551ce6dc72b6f8b23ff696d..4c2ffe3ceecc88bb3c1830357ae= 27cdafb53791b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -61,6 +61,16 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_de= c[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D PROFILE_AV1, + .min =3D V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN), + .value =3D V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, { .cap_id =3D PROFILE_VP9, .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, @@ -144,6 +154,33 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_= dec[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D LEVEL_AV1, + .min =3D V4L2_MPEG_VIDEO_AV1_LEVEL_2_0, + .max =3D V4L2_MPEG_VIDEO_AV1_LEVEL_6_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_3) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_0) | + BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_1), + .value =3D V4L2_MPEG_VIDEO_AV1_LEVEL_6_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, { .cap_id =3D TIER, .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, @@ -155,6 +192,53 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_= dec[] =3D { .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, .set =3D iris_set_u32_enum, }, + { + .cap_id =3D TIER_AV1, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_TIER, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D DRAP, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_DRAP_CONFIG, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D FILM_GRAIN, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_FILM_GRAIN_PRESENT, + .flags =3D CAP_FLAG_VOLATILE, + }, + { + .cap_id =3D SUPER_BLOCK, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + }, + { + .cap_id =3D ENH_LAYER_COUNT, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_AV1_OP_POINT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, { .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, .min =3D DEFAULT_MAX_HOST_BUF_COUNT, @@ -698,6 +782,19 @@ static const u32 sm8550_vdec_input_config_param_vp9[] = =3D { HFI_PROP_LEVEL, }; =20 +static const u32 sm8550_vdec_input_config_param_av1[] =3D { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT, + HFI_PROP_PROFILE, + HFI_PROP_LEVEL, + HFI_PROP_TIER, + HFI_PROP_AV1_FILM_GRAIN_PRESENT, + HFI_PROP_AV1_SUPER_BLOCK_ENABLED, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + static const u32 sm8550_venc_input_config_params[] =3D { HFI_PROP_COLOR_FORMAT, HFI_PROP_RAW_RESOLUTION, @@ -711,6 +808,12 @@ static const u32 sm8550_vdec_output_config_params[] = =3D { HFI_PROP_LINEAR_STRIDE_SCANLINE, }; =20 +static const u32 sm8550_vdec_output_config_param_av1[] =3D { + HFI_PROP_OPB_ENABLE, + HFI_PROP_COLOR_FORMAT, + HFI_PROP_LINEAR_STRIDE_SCANLINE, +}; + static const u32 sm8550_venc_output_config_params[] =3D { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -734,6 +837,12 @@ static const u32 sm8550_vdec_subscribe_output_properti= es_vp9[] =3D { HFI_PROP_PICTURE_TYPE, }; =20 +static const u32 sm8550_vdec_subscribe_output_properties_av1[] =3D { + HFI_PROP_PICTURE_TYPE, + HFI_PROP_WORST_COMPRESSION_RATIO, + HFI_PROP_WORST_COMPLEXITY_FACTOR, +}; + static const u32 sm8550_dec_ip_int_buf_tbl[] =3D { BUF_BIN, BUF_COMV, @@ -803,11 +912,18 @@ struct iris_platform_data sm8550_data =3D { sm8550_vdec_input_config_param_vp9, .dec_input_config_params_vp9_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 =3D + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), .dec_output_config_params =3D sm8550_vdec_output_config_params, .dec_output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), - + .dec_output_config_params_av1 =3D + sm8550_vdec_output_config_param_av1, + .dec_output_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_param_av1), .enc_input_config_params =3D sm8550_venc_input_config_params, .enc_input_config_params_size =3D @@ -828,6 +944,9 @@ struct iris_platform_data sm8550_data =3D { .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, .dec_output_prop_vp9_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), =20 .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), @@ -896,10 +1015,18 @@ struct iris_platform_data sm8650_data =3D { sm8550_vdec_input_config_param_vp9, .dec_input_config_params_vp9_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 =3D + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), .dec_output_config_params =3D sm8550_vdec_output_config_params, .dec_output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_output_config_params_av1 =3D + sm8550_vdec_output_config_param_av1, + .dec_output_config_params_av1_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_param_av1), =20 .enc_input_config_params =3D sm8550_venc_input_config_params, @@ -921,6 +1048,9 @@ struct iris_platform_data sm8650_data =3D { .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, .dec_output_prop_vp9_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), =20 .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), --=20 2.34.1