From nobody Fri Oct 3 10:15:02 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4A6C35AAB3 for ; Tue, 2 Sep 2025 20:45:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845903; cv=none; b=qCa+b/cb2VpCSvmpDBWz1DCT8KTk6PeNm5fWPEsSJyXYPIQ60NGIKljzsT1/dtX1JNFVRKGS6aPs0ibGEC5s6R8NA4KfdqBru6fRxQMTnGwQTta3usTWebTbUli6DU1qINkGv2852opyFC3u18vy0Ebcjg9cvTW1sDpuQxY6ryI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845903; c=relaxed/simple; bh=NNLPTKtx/ZzBkGT6fzsckp1Yqu0jL2qYmg8gJGldf4c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CSVPTE6KCXy4aYyEQRBuGtDRQ1YHVveHiAXaXdbDdHJ43eQSsOsAmTvKypgL16CX+Ezs7oNls1BEJCo76oSU3ZE+Z/WCvR1uC1ymQjzAW+SG8vRMsrDWHwQwT5Cdrh4WfqpWRRnxJfNmvZPd1PGfE2CUag2ivzLdgsXgwBGPz1I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ghJyRqXZ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ghJyRqXZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756845899; bh=NNLPTKtx/ZzBkGT6fzsckp1Yqu0jL2qYmg8gJGldf4c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ghJyRqXZNtVVacX25JFsyBeBoCUwgLsHoZZcjYOubidu+4pt52vJEzo5FT68gEstT xRj6wLjox6yO/n+zuwAr6DkKMA0T+cV3O993iNjqCvVtzZCq0APBL1xOTRK5O1949p 6+QEwCHFjZOV+ituyDPINz9x4yPJw0PJ5BLcxC/O9UPDBz5UZCv7DDSDqFTOF2eoIa F1ikPuh5wT5M5Jyt12i2Y9VYsDoe55WwEUU67VCSGr3SxIa3TAWZdenxM7Q3EdNwBz 4+sfyOBgY57q31cOoEj+waFbH2F5Mto35meZ34n4pCYbAThfpKF2w2dTuuAf9Lwvh/ X5GigWPGo0+3g== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 166A817E129F; Tue, 2 Sep 2025 22:44:59 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:43 +0300 Subject: [PATCH v4 08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-8-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep track of the clock rate programmed in hardware and support implementing the ->recalc_rate() callback in hdptx_phy_clk_ops. Computing the clock rate from the actual PHY PLL configuration seems to work reliably, hence remove the now redundant struct member. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 2303c132172135d3a2678cbd5a1bac6a3e139c47..7b1526c1ea3dfc26323d7b90631= dc9fd2e3a7266 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -401,7 +401,6 @@ struct rk_hdptx_phy { =20 /* clk provider */ struct clk_hw hw; - unsigned long hw_rate; bool restrict_rate_change; =20 atomic_t usage_count; @@ -963,7 +962,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdp= tx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; - int ret, i; + int i; =20 if (!hdptx->hdmi_cfg.tmds_char_rate) return 0; @@ -1025,12 +1024,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_= hdptx_phy *hdptx) regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); =20 - ret =3D rk_hdptx_post_enable_pll(hdptx); - if (!ret) - hdptx->hw_rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate = * 8, - hdptx->hdmi_cfg.bpc); - - return ret; + return rk_hdptx_post_enable_pll(hdptx); } =20 static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) @@ -1935,9 +1929,6 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(str= uct clk_hw *hw, u64 rate; int ret; =20 - if (hdptx->hw_rate) - return hdptx->hw_rate; - ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); if (ret || !(status & HDPTX_I_PLL_EN)) return 0; --=20 2.51.0