From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07C582E7F0E for ; Tue, 2 Sep 2025 20:44:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845896; cv=none; b=Bwyt8T+/JWklviFXx5ZCyvz6AwZG8saxIMju7yAcnnhVUUsV4yFB5K99zcr88qEjxaMuWeI18S7swsHBdKYIjq1lziTmABrVb4vWhoREspboV+sW62xTno7ErdpO9alxXHln6/IQWh9f5aEmn0Z0KfS2pzIxbig1Ae5Zje1bqkU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845896; c=relaxed/simple; bh=uAjAgXeRfa++7TzMQXDYJfWBDuyTpZXti/Fx/3Cs76Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MmSxMRUx/K1xJ0LKeQX/VwN+wJxLT09RQomMeVfpEnUPlceByCFcGyt3KfWLv/LU+SNY/jo44fEloTKfwvPW8yMLRsRCjPtEOoBiLncc0GAuSoj0H7rJuZOAOLwKasSqm9FonOZzDILCaIk4ROB93XcMyZ6EER2/UjHA5MRoBAM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=LkMlajey; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="LkMlajey" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756845893; bh=uAjAgXeRfa++7TzMQXDYJfWBDuyTpZXti/Fx/3Cs76Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LkMlajey5rMhK3SiLl/e9e1G+zPnjm9acE7YS3qIdCLphhOI7k8+7Kp3zkpwoB4KC RmlMF3Fe5k3wsxRp3Q0ylmVmAZcLAEnYcvz8tRPMWQ1cS8blpWAsLjS6RlRsVnryER YtvjzGCQ9LinZ+F2cp9Ll8XT8Oos2hzpA+gk4Ra6GHbcSat1A/PUYagt7HaCwZ39+7 KVt7Vp6cHLRGQVzMUVf9cZ5Rb1G0RRkpH82d3cxIfNDP/pG4qFtr23U1ghSvS4wnWr 3cz/EFmi0Y4/cQ5A5jZBZp75CiliaDz4lznTVNgZ8RPSDXsYXcKIfKbiZVxuF/7nbN LxChYZvas5Wxg== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 254AF17E0579; Tue, 2 Sep 2025 22:44:53 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:36 +0300 Subject: [PATCH v4 01/11] phy: hdmi: Add HDMI 2.1 FRL configuration options Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-1-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The HDMI 2.1 specification introduced the Fixed Rate Link (FRL) mode, aiming to replace the older Transition-Minimized Differential Signaling (TMDS) mode used in previous HDMI versions to support much higher bandwidths (up to 48 Gbps) for modern video and audio formats. FRL has been designed to support ultra high resolution formats at high refresh rates like 8K@60Hz or 4K@120Hz, and eliminates the need for dynamic bandwidth adjustments, which reduces latency. It operates with 3 or 4 lanes at different link rates: 3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps. Add support for configuring the FRL mode for HDMI PHYs. Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index f0ec963c6e84f1b7728acafc824dff191c6b873d..d4cf4430ee8f3bf0f18a109c5a7= 640293a4293b1 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -6,16 +6,31 @@ #ifndef __PHY_HDMI_H_ #define __PHY_HDMI_H_ =20 +#include + +enum phy_hdmi_mode { + PHY_HDMI_MODE_TMDS, + PHY_HDMI_MODE_FRL, +}; + /** * struct phy_configure_opts_hdmi - HDMI configuration set - * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. * @bpc: Bits per color channel. + * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps. + * @frl.lanes: HDMI FRL lanes count. * * This structure is used to represent the configuration state of a HDMI p= hy. */ struct phy_configure_opts_hdmi { - unsigned long long tmds_char_rate; unsigned int bpc; + union { + unsigned long long tmds_char_rate; + struct { + u8 rate_per_lane; + u8 lanes; + } frl; + }; }; =20 #endif /* __PHY_HDMI_H_ */ --=20 2.51.0 From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9F3E2E8892 for ; Tue, 2 Sep 2025 20:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845898; cv=none; b=rHDgHKlVF2C7k1aHz6yXVdA8OdNTtnAm/b/wn5L2xGNhnZOAXnnG24vw+/FklzVMg2Tf2hY5aTt4E5lqO04/wH+422Y92ILaeCN4PmK7t6m7hQUiiBAF/XC74fL7r34luq3xwxGk1u0RRyVS/1LKFcem87V5qld0k9Bpn7Ff0gk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845898; c=relaxed/simple; bh=fIVDagT/zvHJ/25XzWd6tRmN6zW80gwREUlw0C5elnQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G1/gz5ZvnB1tFoVDbkhFeHHwdsqtSaPPPBFXQUMIBf6KmXvEarqjSuLPDVGkNQPfVvPAFLIS95M0Els6qmeCdclHyTdDOQXSuLM8MIddKRG5o0QaqlGQ+O2VE3IBUgipEqL7FnJ956iJtlf45E6hA8QEp4EYAQMKiVx9hTpEZ18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=dGH16vcU; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="dGH16vcU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756845894; bh=fIVDagT/zvHJ/25XzWd6tRmN6zW80gwREUlw0C5elnQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dGH16vcUJKri3ZnuQqWJwg2yVJr+z1vpCDhnHxSB7SGsYcHbzXuKrFm+rtBxtlgFy 0fbwVvtfl1HiNF6NgxTmIYVlEKRdgJHEL1i/SIEIvTrG6k0xtZuMc+OUjuBNPbQCqU gBr1tbLQesVCeIWYsw4CVfJCfTTveWcDHs7b43udFwrxlzmU29CGxXX/UwiPIA4FLc 7i3MrmkybMHnJZqk9o4OGe/GbekAyfuDuuRQpYQaTpWxoYERyVENgvvtZ+4jEWdtI8 +K3LSCF2REAyhXnMEOVsvYlVJZ7wgzeQfRYhY953jUMIsjNMKpkt/xGyGnoeU6EBy+ IgYrJUraqkQGQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 03DE717E129F; Tue, 2 Sep 2025 22:44:53 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:37 +0300 Subject: [PATCH v4 02/11] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-2-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 rk_hdptx_dp_reset() is allowed to sleep, hence replace the busy waiting with usleep_range(), to allow other threads to run. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 29de2f7bdae8a31958e31b0a64281532fd76e64d..b7af27eac293c46647c3abbcb71= 28939d4ee012d 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1074,7 +1074,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hd= ptx) reset_control_assert(hdptx->rsts[RST_INIT].rstc); =20 reset_control_assert(hdptx->rsts[RST_APB].rstc); - udelay(10); + usleep_range(10, 15); reset_control_deassert(hdptx->rsts[RST_APB].rstc); =20 regmap_update_bits(hdptx->regmap, LANE_REG(0301), --=20 2.51.0 From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9EBC2E7F38 for ; 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Tue, 2 Sep 2025 22:44:54 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:38 +0300 Subject: [PATCH v4 03/11] phy: rockchip: samsung-hdptx: Fix coding style alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-3-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Handle a bunch of reported checkpatch.pl complaints: CHECK: Alignment should match open parenthesis Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index b7af27eac293c46647c3abbcb7128939d4ee012d..a729e15de9e097a54c02ea965c5= cc85534338302 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1656,11 +1656,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdpt= x_phy *hdptx, regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, LN_TX_JEQ_EVEN_CTRL_RBR_MASK, FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK, - ctrl->tx_jeq_even_ctrl)); + ctrl->tx_jeq_even_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset, LN_TX_JEQ_ODD_CTRL_RBR_MASK, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK, - ctrl->tx_jeq_odd_ctrl)); + ctrl->tx_jeq_odd_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, LN_TX_SER_40BIT_EN_RBR_MASK, FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1)); @@ -1670,11 +1670,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdpt= x_phy *hdptx, regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, LN_TX_JEQ_EVEN_CTRL_HBR_MASK, FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK, - ctrl->tx_jeq_even_ctrl)); + ctrl->tx_jeq_even_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, LN_TX_JEQ_ODD_CTRL_HBR_MASK, FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK, - ctrl->tx_jeq_odd_ctrl)); + ctrl->tx_jeq_odd_ctrl)); regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, LN_TX_SER_40BIT_EN_HBR_MASK, FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1)); @@ -1685,11 +1685,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdpt= x_phy *hdptx, regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, - ctrl->tx_jeq_even_ctrl)); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-4-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Fix the naming inconsistencies for some of the functions and global variables: * Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable * Replace '_ropll_tmds_' with '_tmds_ropll_' globally * Replace 'hdtpx' with 'hdptx' globally Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 62 +++++++++++--------= ---- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index a729e15de9e097a54c02ea965c5cc85534338302..44fda739705abc86428fa6fb41c= 545aceafbb28f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -32,17 +32,17 @@ #define HDPTX_O_PHY_RDY BIT(1) #define HDPTX_O_SB_RDY BIT(0) =20 -#define HDTPX_REG(_n, _min, _max) \ +#define HDPTX_REG(_n, _min, _max) \ ( \ BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ ((0x##_n) * 4) \ ) =20 -#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) -#define SB_REG(n) HDTPX_REG(n, 0100, 0129) -#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) -#define LANE_REG(n) HDTPX_REG(n, 0300, 062d) +#define CMN_REG(n) HDPTX_REG(n, 0000, 00a7) +#define SB_REG(n) HDPTX_REG(n, 0100, 0129) +#define LNTOP_REG(n) HDPTX_REG(n, 0200, 0229) +#define LANE_REG(n) HDPTX_REG(n, 0300, 062d) =20 /* CMN_REG(0008) */ #define OVRD_LCPLL_EN_MASK BIT(7) @@ -411,7 +411,7 @@ struct rk_hdptx_phy { unsigned int lanes; }; =20 -static const struct ropll_config ropll_tmds_cfg[] =3D { +static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] =3D { { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, @@ -456,7 +456,7 @@ static const struct ropll_config ropll_tmds_cfg[] =3D { 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, }; =20 -static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0009), 0x0c), REG_SEQ0(CMN_REG(000a), 0x83), REG_SEQ0(CMN_REG(000b), 0x06), @@ -546,7 +546,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(009b), 0x10), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0008), 0x00), REG_SEQ0(CMN_REG(0011), 0x01), REG_SEQ0(CMN_REG(0017), 0x20), @@ -588,14 +588,14 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(009b), 0x00), }; =20 -static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_sb_init_seq[] =3D { REG_SEQ0(SB_REG(0114), 0x00), REG_SEQ0(SB_REG(0115), 0x00), REG_SEQ0(SB_REG(0116), 0x00), REG_SEQ0(SB_REG(0117), 0x00), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x00), REG_SEQ0(LNTOP_REG(0202), 0x00), REG_SEQ0(LNTOP_REG(0203), 0x0f), @@ -603,7 +603,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_hi= ghbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0205), 0xff), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lntop_lowbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x07), REG_SEQ0(LNTOP_REG(0202), 0xc1), REG_SEQ0(LNTOP_REG(0203), 0xf0), @@ -611,7 +611,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lo= wbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0205), 0x1f), }; =20 -static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0303), 0x0c), REG_SEQ0(LANE_REG(0307), 0x20), REG_SEQ0(LANE_REG(030a), 0x17), @@ -666,7 +666,7 @@ static const struct reg_sequence rk_hdtpx_common_lane_i= nit_seq[] =3D { REG_SEQ0(LANE_REG(0620), 0xa0), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0312), 0x00), REG_SEQ0(LANE_REG(0412), 0x00), REG_SEQ0(LANE_REG(0512), 0x00), @@ -970,7 +970,7 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long lon= g rate, return true; } =20 -static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) +static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; @@ -979,9 +979,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdp= tx_phy *hdptx) if (!hdptx->hdmi_cfg.tmds_char_rate) return 0; =20 - for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) { - cfg =3D &ropll_tmds_cfg[i]; + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rat= e) { + cfg =3D &rk_hdptx_tmds_ropll_cfg[i]; break; } =20 @@ -1001,8 +1001,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_h= dptx_phy *hdptx) =20 rk_hdptx_pre_power_up(hdptx); =20 - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq); =20 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); @@ -1044,25 +1044,25 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk= _hdptx_phy *hdptx) return ret; } =20 -static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) +static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) { - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq); =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq); } else { /* For 1/10 bitrate clk */ - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_lowbr_seq); } =20 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq); =20 return rk_hdptx_post_enable_lane(hdptx); } @@ -1121,7 +1121,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_= phy *hdptx) if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx); + ret =3D rk_hdptx_tmds_ropll_cmn_config(hdptx); if (ret) goto dec_usage; } @@ -1468,7 +1468,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx); + ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } @@ -1491,11 +1491,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct r= k_hdptx_phy *hdptx, if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 - for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (hdmi->tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdmi->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) break; =20 - if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && + if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) return -EINVAL; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-5-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In preparation to support FRL mode, move the PHY lane output enablement from the TMDS specific configuration to the common *_post_enable_lane() helper and make sure it gets turned off in *_phy_disable(). Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 44fda739705abc86428fa6fb41c545aceafbb28f..574e468e5070d225aa5ce4d648a= ad2bcae851b4b 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -829,6 +829,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_ph= y *hdptx) HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); + ret =3D regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, (val & HDPTX_O_PHY_RDY) && (val & HDPTX_O_PLL_LOCK_DONE), @@ -882,6 +884,7 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *h= dptx) usleep_range(20, 30); reset_control_deassert(hdptx->rsts[RST_APB].rstc); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0); regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); regmap_write(hdptx->regmap, SB_REG(0110), 0x1); @@ -1059,7 +1062,6 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_= hdptx_phy *hdptx) } =20 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); - regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq); --=20 2.51.0 From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17D353570AF for ; Tue, 2 Sep 2025 20:44:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845900; 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Tue, 2 Sep 2025 22:44:57 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:41 +0300 Subject: [PATCH v4 06/11] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-6-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Drop redundant reg_sequence entries from rk_hdptx_common_cmn_init_seq[], i.e. those that are either duplicated or overridden in rk_hdptx_tmds_cmn_init_seq[]. Additionally, a few items do not really belong to the former, hence move them to the latter. That's mostly a preparatory step for adding FRL support. No functional changes intended at this point. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 22 ++++---------------= --- 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 574e468e5070d225aa5ce4d648aad2bcae851b4b..8e38adcb8f13325b87e27d6d809= cfa1bfd91521c 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -465,13 +465,11 @@ static const struct reg_sequence rk_hdptx_common_cmn_= init_seq[] =3D { REG_SEQ0(CMN_REG(000e), 0x0f), REG_SEQ0(CMN_REG(000f), 0x0f), REG_SEQ0(CMN_REG(0010), 0x04), - REG_SEQ0(CMN_REG(0011), 0x00), REG_SEQ0(CMN_REG(0012), 0x26), REG_SEQ0(CMN_REG(0013), 0x22), REG_SEQ0(CMN_REG(0014), 0x24), REG_SEQ0(CMN_REG(0015), 0x77), REG_SEQ0(CMN_REG(0016), 0x08), - REG_SEQ0(CMN_REG(0017), 0x00), REG_SEQ0(CMN_REG(0018), 0x04), REG_SEQ0(CMN_REG(0019), 0x48), REG_SEQ0(CMN_REG(001a), 0x01), @@ -479,13 +477,7 @@ static const struct reg_sequence rk_hdptx_common_cmn_i= nit_seq[] =3D { REG_SEQ0(CMN_REG(001c), 0x01), REG_SEQ0(CMN_REG(001d), 0x64), REG_SEQ0(CMN_REG(001f), 0x00), - REG_SEQ0(CMN_REG(0026), 0x53), REG_SEQ0(CMN_REG(0029), 0x01), - REG_SEQ0(CMN_REG(0030), 0x00), - REG_SEQ0(CMN_REG(0031), 0x20), - REG_SEQ0(CMN_REG(0032), 0x30), - REG_SEQ0(CMN_REG(0033), 0x0b), - REG_SEQ0(CMN_REG(0034), 0x23), REG_SEQ0(CMN_REG(0035), 0x00), REG_SEQ0(CMN_REG(0038), 0x00), REG_SEQ0(CMN_REG(0039), 0x00), @@ -496,7 +488,6 @@ static const struct reg_sequence rk_hdptx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(003f), 0x83), REG_SEQ0(CMN_REG(0040), 0x06), REG_SEQ0(CMN_REG(0041), 0x20), - REG_SEQ0(CMN_REG(0042), 0xb8), REG_SEQ0(CMN_REG(0043), 0x00), REG_SEQ0(CMN_REG(0044), 0x46), REG_SEQ0(CMN_REG(0045), 0x24), @@ -506,14 +497,9 @@ static const struct reg_sequence rk_hdptx_common_cmn_i= nit_seq[] =3D { REG_SEQ0(CMN_REG(004b), 0x00), REG_SEQ0(CMN_REG(004c), 0x01), REG_SEQ0(CMN_REG(004d), 0x64), - REG_SEQ0(CMN_REG(004e), 0x14), REG_SEQ0(CMN_REG(004f), 0x00), REG_SEQ0(CMN_REG(0050), 0x00), - REG_SEQ0(CMN_REG(005d), 0x0c), REG_SEQ0(CMN_REG(005f), 0x01), - REG_SEQ0(CMN_REG(006b), 0x04), - REG_SEQ0(CMN_REG(0073), 0x30), - REG_SEQ0(CMN_REG(0074), 0x00), REG_SEQ0(CMN_REG(0075), 0x20), REG_SEQ0(CMN_REG(0076), 0x30), REG_SEQ0(CMN_REG(0077), 0x08), @@ -525,13 +511,10 @@ static const struct reg_sequence rk_hdptx_common_cmn_= init_seq[] =3D { REG_SEQ0(CMN_REG(007e), 0x00), REG_SEQ0(CMN_REG(007f), 0x00), REG_SEQ0(CMN_REG(0080), 0x00), - REG_SEQ0(CMN_REG(0081), 0x09), REG_SEQ0(CMN_REG(0082), 0x04), REG_SEQ0(CMN_REG(0083), 0x24), REG_SEQ0(CMN_REG(0084), 0x20), REG_SEQ0(CMN_REG(0085), 0x03), - REG_SEQ0(CMN_REG(0086), 0x01), - REG_SEQ0(CMN_REG(0087), 0x0c), REG_SEQ0(CMN_REG(008a), 0x55), REG_SEQ0(CMN_REG(008b), 0x25), REG_SEQ0(CMN_REG(008c), 0x2c), @@ -543,7 +526,6 @@ static const struct reg_sequence rk_hdptx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(0092), 0x00), REG_SEQ0(CMN_REG(0093), 0x00), REG_SEQ0(CMN_REG(009a), 0x11), - REG_SEQ0(CMN_REG(009b), 0x10), }; =20 static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] =3D { @@ -577,9 +559,13 @@ static const struct reg_sequence rk_hdptx_tmds_cmn_ini= t_seq[] =3D { REG_SEQ0(CMN_REG(0048), 0x11), REG_SEQ0(CMN_REG(004e), 0x34), REG_SEQ0(CMN_REG(005c), 0x25), + REG_SEQ0(CMN_REG(005d), 0x0c), REG_SEQ0(CMN_REG(005e), 0x4f), + REG_SEQ0(CMN_REG(006b), 0x04), + REG_SEQ0(CMN_REG(0073), 0x30), REG_SEQ0(CMN_REG(0074), 0x04), REG_SEQ0(CMN_REG(0081), 0x01), + REG_SEQ0(CMN_REG(0086), 0x01), REG_SEQ0(CMN_REG(0087), 0x04), REG_SEQ0(CMN_REG(0089), 0x00), REG_SEQ0(CMN_REG(0095), 0x00), --=20 2.51.0 From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 149B03570DB for ; Tue, 2 Sep 2025 20:44:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Tue, 2 Sep 2025 22:44:58 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:42 +0300 Subject: [PATCH v4 07/11] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-7-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Improve ->recalc_rate() callback of hdptx_phy_clk_ops to calculate the initial clock rate based on the actual PHY PLL configuration as retrieved from the related hardware registers. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 91 +++++++++++++++++++= +++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 8e38adcb8f13325b87e27d6d809cfa1bfd91521c..2303c132172135d3a2678cbd5a1= bac6a3e139c47 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1850,12 +1850,101 @@ static void rk_hdptx_phy_clk_unprepare(struct clk_= hw *hw) rk_hdptx_phy_consumer_put(hdptx, true); } =20 +#define PLL_REF_CLK 24000000ULL + +static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hd= ptx) +{ + struct ropll_config ropll_hw; + u64 fout, sdm; + u32 mode, val; + int ret; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0008), &mode); + if (ret) + return 0; + + if (mode & LCPLL_LCVCO_MODE_EN_MASK) + return 0; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0051), &val); + if (ret) + return 0; + ropll_hw.pms_mdiv =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(005E), &val); + if (ret) + return 0; + ropll_hw.sdm_en =3D val & ROPLL_SDM_EN_MASK; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0064), &val); + if (ret) + return 0; + ropll_hw.sdm_num_sign =3D val & ROPLL_SDM_NUM_SIGN_RBR_MASK; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0065), &val); + if (ret) + return 0; + ropll_hw.sdm_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0060), &val); + if (ret) + return 0; + ropll_hw.sdm_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0069), &val); + if (ret) + return 0; + ropll_hw.sdc_n =3D (val & ROPLL_SDC_N_RBR_MASK) + 3; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(006c), &val); + if (ret) + return 0; + ropll_hw.sdc_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0070), &val); + if (ret) + return 0; + ropll_hw.sdc_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0086), &val); + if (ret) + return 0; + ropll_hw.pms_sdiv =3D ((val & PLL_PCG_POSTDIV_SEL_MASK) >> 4) + 1; + + fout =3D PLL_REF_CLK * ropll_hw.pms_mdiv; + if (ropll_hw.sdm_en) { + sdm =3D div_u64(PLL_REF_CLK * ropll_hw.sdc_deno * + ropll_hw.pms_mdiv * ropll_hw.sdm_num, + 16 * ropll_hw.sdm_deno * + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num)); + + if (ropll_hw.sdm_num_sign) + fout =3D fout - sdm; + else + fout =3D fout + sdm; + } + + return div_u64(fout * 2, ropll_hw.pms_sdiv * 10); +} + static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + u32 status; + u64 rate; + int ret; + + if (hdptx->hw_rate) + return hdptx->hw_rate; + + ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); + if (ret || !(status & HDPTX_I_PLL_EN)) + return 0; + + rate =3D rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx); =20 - return hdptx->hw_rate; + return DIV_ROUND_CLOSEST_ULL(rate * 8, hdptx->hdmi_cfg.bpc); } =20 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, --=20 2.51.0 From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4A6C35AAB3 for ; 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Tue, 2 Sep 2025 22:44:59 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:43 +0300 Subject: [PATCH v4 08/11] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-8-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep track of the clock rate programmed in hardware and support implementing the ->recalc_rate() callback in hdptx_phy_clk_ops. Computing the clock rate from the actual PHY PLL configuration seems to work reliably, hence remove the now redundant struct member. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 2303c132172135d3a2678cbd5a1bac6a3e139c47..7b1526c1ea3dfc26323d7b90631= dc9fd2e3a7266 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -401,7 +401,6 @@ struct rk_hdptx_phy { =20 /* clk provider */ struct clk_hw hw; - unsigned long hw_rate; bool restrict_rate_change; =20 atomic_t usage_count; @@ -963,7 +962,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdp= tx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; - int ret, i; + int i; =20 if (!hdptx->hdmi_cfg.tmds_char_rate) return 0; @@ -1025,12 +1024,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_= hdptx_phy *hdptx) regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); =20 - ret =3D rk_hdptx_post_enable_pll(hdptx); - if (!ret) - hdptx->hw_rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate = * 8, - hdptx->hdmi_cfg.bpc); - - return ret; + return rk_hdptx_post_enable_pll(hdptx); } =20 static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) @@ -1935,9 +1929,6 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(str= uct clk_hw *hw, u64 rate; int ret; =20 - if (hdptx->hw_rate) - return hdptx->hw_rate; - ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); if (ret || !(status & HDPTX_I_PLL_EN)) return 0; --=20 2.51.0 From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4B0B35AAB5 for ; Tue, 2 Sep 2025 20:45:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Tue, 2 Sep 2025 22:44:59 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:44 +0300 Subject: [PATCH v4 09/11] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-9-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In preparation to support the FRL operation mode which gets configured via the lanes and rate per lane tuple, switch to a driver specific struct for configuring the link rate and bpc. This simplifies and optimizes the implementation by allowing implicit switches between TMDS and FRL rates, without requiring additional checks of the active PHY mode followed by recalculations of the link rate when operating in FRL mode. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 44 +++++++++++++------= ---- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 7b1526c1ea3dfc26323d7b90631dc9fd2e3a7266..358625790d5ee3e2a3971abe22c= c98e8e73e1066 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -387,6 +387,11 @@ struct rk_hdptx_phy_cfg { unsigned int phy_ids[MAX_HDPTX_PHY_NUM]; }; =20 +struct rk_hdptx_hdmi_cfg { + unsigned long long rate; + unsigned int bpc; +}; + struct rk_hdptx_phy { struct device *dev; struct regmap *regmap; @@ -394,7 +399,7 @@ struct rk_hdptx_phy { =20 int phy_id; struct phy *phy; - struct phy_configure_opts_hdmi hdmi_cfg; + struct rk_hdptx_hdmi_cfg hdmi_cfg; struct clk_bulk_data *clks; int nr_clks; struct reset_control_bulk_data rsts[RST_MAX]; @@ -964,19 +969,19 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_h= dptx_phy *hdptx) struct ropll_config rc =3D {0}; int i; =20 - if (!hdptx->hdmi_cfg.tmds_char_rate) + if (!hdptx->hdmi_cfg.rate) return 0; =20 for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) - if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rat= e) { + if (hdptx->hdmi_cfg.rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) { cfg =3D &rk_hdptx_tmds_ropll_cfg[i]; break; } =20 if (!cfg) { - if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) { + if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.rate, &rc)) { dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%llu\n", - __func__, hdptx->hdmi_cfg.tmds_char_rate); + __func__, hdptx->hdmi_cfg.rate); return -EINVAL; } =20 @@ -984,7 +989,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdp= tx_phy *hdptx) } =20 dev_dbg(hdptx->dev, "%s rate=3D%llu mdiv=3D%u sdiv=3D%u sdm_en=3D%u k_sig= n=3D%u k=3D%u lc=3D%u\n", - __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv += 1, + __func__, hdptx->hdmi_cfg.rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); =20 rk_hdptx_pre_power_up(hdptx); @@ -1033,7 +1038,7 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_= hdptx_phy *hdptx) =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { + if (hdptx->hdmi_cfg.rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq); } else { @@ -1404,19 +1409,19 @@ static int rk_hdptx_phy_power_on(struct phy *phy) int ret, lane; =20 if (mode !=3D PHY_MODE_DP) { - if (!hdptx->hdmi_cfg.tmds_char_rate) { + if (!hdptx->hdmi_cfg.rate) { /* * FIXME: Temporary workaround to setup TMDS char rate * from the RK DW HDMI QP bridge driver. * Will be removed as soon the switch to the HDMI PHY * configuration API has been completed on both ends. */ - hdptx->hdmi_cfg.tmds_char_rate =3D phy_get_bus_width(hdptx->phy) & 0xff= fffff; - hdptx->hdmi_cfg.tmds_char_rate *=3D 100; + hdptx->hdmi_cfg.rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; + hdptx->hdmi_cfg.rate *=3D 100; } =20 dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); } =20 ret =3D rk_hdptx_phy_consumer_get(hdptx); @@ -1763,12 +1768,13 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->hdmi_cfg =3D opts->hdmi; + hdptx->hdmi_cfg.rate =3D opts->hdmi.tmds_char_rate; + hdptx->hdmi_cfg.bpc =3D opts->hdmi.bpc; hdptx->restrict_rate_change =3D true; } =20 dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); return ret; } =20 @@ -1948,7 +1954,7 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, * To be dropped as soon as the RK DW HDMI QP bridge driver * switches to make use of phy_configure(). */ - if (!hdptx->restrict_rate_change && rate !=3D hdptx->hdmi_cfg.tmds_char_r= ate) { + if (!hdptx->restrict_rate_change && rate !=3D hdptx->hdmi_cfg.rate) { struct phy_configure_opts_hdmi hdmi =3D { .tmds_char_rate =3D rate, }; @@ -1957,7 +1963,7 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, if (ret) return ret; =20 - hdptx->hdmi_cfg =3D hdmi; + hdptx->hdmi_cfg.rate =3D rate; } =20 /* @@ -1965,7 +1971,7 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with * a different rate argument. */ - return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->h= dmi_cfg.bpc); + return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.rate * 8, hdptx->hdmi_cfg.bp= c); } =20 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -1975,10 +1981,10 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw = *hw, unsigned long rate, unsigned long long tmds_rate =3D DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi= _cfg.bpc, 8); =20 /* Revert any unlikely TMDS char rate change since round_rate() */ - if (hdptx->hdmi_cfg.tmds_char_rate !=3D tmds_rate) { + if (hdptx->hdmi_cfg.rate !=3D tmds_rate) { dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu= \n", - tmds_rate, hdptx->hdmi_cfg.tmds_char_rate); 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Tue, 2 Sep 2025 22:45:00 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 23:44:45 +0300 Subject: [PATCH v4 10/11] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-10-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In order to facilitate introduction of HDMI 2.1 FRL support and to avoid recomputing the link rate after verifying the HDMI configuration given as input, extend rk_hdptx_phy_verify_hdmi_config() by providing an optional output parameter to store the validated configuration. For improved code readability, also rename the existing hdmi input parameter. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 35 ++++++++++++-------= ---- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 358625790d5ee3e2a3971abe22cc98e8e73e1066..048725544971ac4450c6e81f44c= 514ac320c7a55 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1471,25 +1471,24 @@ static int rk_hdptx_phy_power_off(struct phy *phy) } =20 static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, - struct phy_configure_opts_hdmi *hdmi) + struct phy_configure_opts_hdmi *hdmi_in, + struct rk_hdptx_hdmi_cfg *hdmi_out) { int i; =20 - if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) + if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) - if (hdmi->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) + if (hdmi_in->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) break; =20 if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && - !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) + !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL)) return -EINVAL; =20 - if (!hdmi->bpc) - hdmi->bpc =3D 8; - - switch (hdmi->bpc) { + switch (hdmi_in->bpc) { + case 0: case 8: case 10: case 12: @@ -1499,6 +1498,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, return -EINVAL; } =20 + if (hdmi_out) { + hdmi_out->rate =3D hdmi_in->tmds_char_rate; + hdmi_out->bpc =3D hdmi_in->bpc ?: 8; + } + return 0; } =20 @@ -1764,17 +1768,15 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt int ret; =20 if (mode !=3D PHY_MODE_DP) { - ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, &hdptx->hdmi= _cfg); if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->hdmi_cfg.rate =3D opts->hdmi.tmds_char_rate; - hdptx->hdmi_cfg.bpc =3D opts->hdmi.bpc; hdptx->restrict_rate_change =3D true; + dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); } =20 - dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); return ret; } =20 @@ -1818,7 +1820,7 @@ static int rk_hdptx_phy_validate(struct phy *phy, enu= m phy_mode mode, struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); =20 if (mode !=3D PHY_MODE_DP) - return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi, NULL); =20 return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); } @@ -1958,12 +1960,11 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_= hw *hw, unsigned long rate, struct phy_configure_opts_hdmi hdmi =3D { .tmds_char_rate =3D rate, }; - int ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi); + + int ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi, &hdptx->hdmi_c= fg); =20 if (ret) return ret; - - hdptx->hdmi_cfg.rate =3D rate; } =20 /* --=20 2.51.0 From nobody Fri Oct 3 08:50:42 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CF8A35E4C3 for ; Tue, 2 Sep 2025 20:45:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845906; cv=none; b=I+V91i00DoavL4D7OUsePVLzo5cQQELCxTucBSRq8DB4v1GC7bXl4ciNyvRHVyTLYIrZ2ARwkt0PuXkWOPWxcbF8tvBRoEZ8HL1FcjDHATrwhdw/g0oIEMkVXe3mxlmmXYyoRGVaGqApLO17vXfEq1t7pJu9qC/WmYqfA9Vyb5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756845906; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-frl-v4-11-7d69176373ce@collabora.com> References: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> In-Reply-To: <20250902-phy-hdptx-frl-v4-0-7d69176373ce@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The PHY is capable of handling four HDMI 2.1 Fixed Rate Link (FRL) lanes, and each one can operate at any of the rates of 3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps. Add the necessary driver changes to support the feature. Co-developed-by: Algea Cao Signed-off-by: Algea Cao Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 459 ++++++++++++++++++= ++-- 1 file changed, 436 insertions(+), 23 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 048725544971ac4450c6e81f44c514ac320c7a55..a474400f4aa79bd15ac3378aebb= 9e94f54fe5e2b 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -22,6 +22,7 @@ #include =20 #define GRF_HDPTX_CON0 0x00 +#define LC_REF_CLK_SEL BIT(11) #define HDPTX_I_PLL_EN BIT(7) #define HDPTX_I_BIAS_EN BIT(6) #define HDPTX_I_BGR_EN BIT(5) @@ -322,6 +323,9 @@ =20 #define HDMI14_MAX_RATE 340000000 #define HDMI20_MAX_RATE 600000000 +#define FRL_3G3L_RATE 900000000 +#define FRL_6G3L_RATE 1800000000 +#define FRL_8G4L_RATE 3200000000 =20 enum dp_link_rate { DP_BW_RBR, @@ -329,6 +333,37 @@ enum dp_link_rate { DP_BW_HBR2, }; =20 +struct lcpll_config { + unsigned long long rate; + u8 lcvco_mode_en; + u8 pi_en; + u8 clk_en_100m; + u8 pms_mdiv; + u8 pms_mdiv_afc; + u8 pms_pdiv; + u8 pms_refdiv; + u8 pms_sdiv; + u8 pi_cdiv_rstn; + u8 pi_cdiv_sel; + u8 sdm_en; + u8 sdm_rstn; + u8 sdc_frac_en; + u8 sdc_rstn; + u8 sdm_deno; + u8 sdm_num_sign; + u8 sdm_num; + u8 sdc_n; + u8 sdc_n2; + u8 sdc_num; + u8 sdc_deno; + u8 sdc_ndiv_rstn; + u8 ssc_en; + u8 ssc_fm_dev; + u8 ssc_fm_freq; + u8 ssc_clk_div_sel; + u8 cd_tx_ser_rate_sel; +}; + struct ropll_config { unsigned long long rate; u8 pms_mdiv; @@ -388,6 +423,7 @@ struct rk_hdptx_phy_cfg { }; =20 struct rk_hdptx_hdmi_cfg { + enum phy_hdmi_mode mode; unsigned long long rate; unsigned int bpc; }; @@ -415,6 +451,19 @@ struct rk_hdptx_phy { unsigned int lanes; }; =20 +static const struct lcpll_config rk_hdptx_frl_lcpll_cfg[] =3D { + { 4800000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0,= 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, + { 4000000000ULL, 1, 1, 0, 0x68, 0x68, 1, 1, 0, 0, 0, 1, 1, 1, 1, 9, 0, 1,= 1, + 0, 2, 3, 1, 0, 0x20, 0x0c, 1, 0, }, + { 2400000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0,= 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, + { 1800000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0,= 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, + { 900000000ULL, 1, 0, 0, 0x7d, 0x7d, 1, 1, 3, 0, 0, 0, 0, 1, 1, 1, 0, 0, = 2, + 0, 0x13, 0x18, 1, 0, 0x20, 0x0c, 1, 0, }, +}; + static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] =3D { { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, @@ -532,6 +581,110 @@ static const struct reg_sequence rk_hdptx_common_cmn_= init_seq[] =3D { REG_SEQ0(CMN_REG(009a), 0x11), }; =20 +static const struct reg_sequence rk_hdptx_frl_lcpll_cmn_init_seq[] =3D { + REG_SEQ0(CMN_REG(0011), 0x00), + REG_SEQ0(CMN_REG(0017), 0x00), + REG_SEQ0(CMN_REG(0025), 0x10), + REG_SEQ0(CMN_REG(0026), 0x53), + REG_SEQ0(CMN_REG(0027), 0x01), + REG_SEQ0(CMN_REG(0028), 0x0d), + REG_SEQ0(CMN_REG(002e), 0x02), + REG_SEQ0(CMN_REG(002f), 0x0d), + REG_SEQ0(CMN_REG(0030), 0x00), + REG_SEQ0(CMN_REG(0031), 0x20), + REG_SEQ0(CMN_REG(0032), 0x30), + REG_SEQ0(CMN_REG(0033), 0x0b), + REG_SEQ0(CMN_REG(0034), 0x23), + REG_SEQ0(CMN_REG(003d), 0x00), + REG_SEQ0(CMN_REG(0042), 0xb8), + REG_SEQ0(CMN_REG(0046), 0xff), + REG_SEQ0(CMN_REG(0048), 0x44), + REG_SEQ0(CMN_REG(004e), 0x14), + REG_SEQ0(CMN_REG(0051), 0x00), + REG_SEQ0(CMN_REG(0055), 0x00), + REG_SEQ0(CMN_REG(0059), 0x11), + REG_SEQ0(CMN_REG(005a), 0x03), + REG_SEQ0(CMN_REG(005c), 0x05), + REG_SEQ0(CMN_REG(005d), 0x0c), + REG_SEQ0(CMN_REG(005e), 0x07), + REG_SEQ0(CMN_REG(0060), 0x01), + REG_SEQ0(CMN_REG(0064), 0x07), + REG_SEQ0(CMN_REG(0065), 0x00), + REG_SEQ0(CMN_REG(0069), 0x00), + REG_SEQ0(CMN_REG(006b), 0x04), + REG_SEQ0(CMN_REG(006c), 0x00), + REG_SEQ0(CMN_REG(0070), 0x01), + REG_SEQ0(CMN_REG(0073), 0x30), + REG_SEQ0(CMN_REG(0074), 0x00), + REG_SEQ0(CMN_REG(0081), 0x09), + REG_SEQ0(CMN_REG(0086), 0x01), + REG_SEQ0(CMN_REG(0087), 0x0c), + REG_SEQ0(CMN_REG(0089), 0x02), + REG_SEQ0(CMN_REG(0095), 0x00), + REG_SEQ0(CMN_REG(0097), 0x00), + REG_SEQ0(CMN_REG(0099), 0x00), + REG_SEQ0(CMN_REG(009b), 0x10), +}; + +static const struct reg_sequence rk_hdptx_frl_lcpll_ropll_cmn_init_seq[] = =3D { + REG_SEQ0(CMN_REG(0008), 0xd0), + REG_SEQ0(CMN_REG(0011), 0x00), + REG_SEQ0(CMN_REG(0017), 0x00), + REG_SEQ0(CMN_REG(001e), 0x35), + REG_SEQ0(CMN_REG(0020), 0x6b), + REG_SEQ0(CMN_REG(0021), 0x6b), + REG_SEQ0(CMN_REG(0022), 0x11), + REG_SEQ0(CMN_REG(0024), 0x00), + REG_SEQ0(CMN_REG(0025), 0x10), + REG_SEQ0(CMN_REG(0026), 0x53), + REG_SEQ0(CMN_REG(0027), 0x15), + REG_SEQ0(CMN_REG(0028), 0x0d), + REG_SEQ0(CMN_REG(002a), 0x09), + REG_SEQ0(CMN_REG(002b), 0x01), + REG_SEQ0(CMN_REG(002c), 0x02), + REG_SEQ0(CMN_REG(002d), 0x02), + REG_SEQ0(CMN_REG(002e), 0x0d), + REG_SEQ0(CMN_REG(002f), 0x61), + REG_SEQ0(CMN_REG(0030), 0x00), + REG_SEQ0(CMN_REG(0031), 0x20), + REG_SEQ0(CMN_REG(0032), 0x30), + REG_SEQ0(CMN_REG(0033), 0x0b), + REG_SEQ0(CMN_REG(0034), 0x23), + REG_SEQ0(CMN_REG(0037), 0x00), + REG_SEQ0(CMN_REG(003d), 0xc0), + REG_SEQ0(CMN_REG(0042), 0xb8), + REG_SEQ0(CMN_REG(0046), 0xff), + REG_SEQ0(CMN_REG(0048), 0x44), + REG_SEQ0(CMN_REG(004e), 0x14), + REG_SEQ0(CMN_REG(0054), 0x19), + REG_SEQ0(CMN_REG(0058), 0x19), + REG_SEQ0(CMN_REG(0059), 0x11), + REG_SEQ0(CMN_REG(005b), 0x30), + REG_SEQ0(CMN_REG(005c), 0x25), + REG_SEQ0(CMN_REG(005d), 0x14), + REG_SEQ0(CMN_REG(005e), 0x0e), + REG_SEQ0(CMN_REG(0063), 0x01), + REG_SEQ0(CMN_REG(0064), 0x0e), + REG_SEQ0(CMN_REG(0068), 0x00), + REG_SEQ0(CMN_REG(0069), 0x02), + REG_SEQ0(CMN_REG(006b), 0x00), + REG_SEQ0(CMN_REG(006f), 0x00), + REG_SEQ0(CMN_REG(0073), 0x02), + REG_SEQ0(CMN_REG(0074), 0x00), + REG_SEQ0(CMN_REG(007a), 0x00), + REG_SEQ0(CMN_REG(0081), 0x09), + REG_SEQ0(CMN_REG(0086), 0x11), + REG_SEQ0(CMN_REG(0087), 0x0c), + REG_SEQ0(CMN_REG(0089), 0x00), + REG_SEQ0(CMN_REG(0095), 0x03), + REG_SEQ0(CMN_REG(0097), 0x00), + REG_SEQ0(CMN_REG(0099), 0x00), + REG_SEQ0(CMN_REG(009b), 0x10), + REG_SEQ0(CMN_REG(009e), 0x03), + REG_SEQ0(CMN_REG(009f), 0xff), + REG_SEQ0(CMN_REG(00a0), 0x60), +}; + static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0008), 0x00), REG_SEQ0(CMN_REG(0011), 0x01), @@ -585,6 +738,16 @@ static const struct reg_sequence rk_hdptx_common_sb_in= it_seq[] =3D { REG_SEQ0(SB_REG(0117), 0x00), }; =20 +static const struct reg_sequence rk_hdptx_frl_lntop_init_seq[] =3D { + REG_SEQ0(LNTOP_REG(0200), 0x04), + REG_SEQ0(LNTOP_REG(0201), 0x00), + REG_SEQ0(LNTOP_REG(0202), 0x00), + REG_SEQ0(LNTOP_REG(0203), 0xf0), + REG_SEQ0(LNTOP_REG(0204), 0xff), + REG_SEQ0(LNTOP_REG(0205), 0xff), + REG_SEQ0(LNTOP_REG(0206), 0x05), +}; + static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x00), REG_SEQ0(LNTOP_REG(0202), 0x00), @@ -656,6 +819,38 @@ static const struct reg_sequence rk_hdptx_common_lane_= init_seq[] =3D { REG_SEQ0(LANE_REG(0620), 0xa0), }; =20 +static const struct reg_sequence rk_hdptx_frl_lane_init_seq[] =3D { + REG_SEQ0(LANE_REG(0312), 0x3c), + REG_SEQ0(LANE_REG(0412), 0x3c), + REG_SEQ0(LANE_REG(0512), 0x3c), + REG_SEQ0(LANE_REG(0612), 0x3c), + REG_SEQ0(LANE_REG(0303), 0x2f), + REG_SEQ0(LANE_REG(0403), 0x2f), + REG_SEQ0(LANE_REG(0503), 0x2f), + REG_SEQ0(LANE_REG(0603), 0x2f), + REG_SEQ0(LANE_REG(0305), 0x03), + REG_SEQ0(LANE_REG(0405), 0x03), + REG_SEQ0(LANE_REG(0505), 0x03), + REG_SEQ0(LANE_REG(0605), 0x03), + REG_SEQ0(LANE_REG(0306), 0xfc), + REG_SEQ0(LANE_REG(0406), 0xfc), + REG_SEQ0(LANE_REG(0506), 0xfc), + REG_SEQ0(LANE_REG(0606), 0xfc), + REG_SEQ0(LANE_REG(0305), 0x4f), + REG_SEQ0(LANE_REG(0405), 0x4f), + REG_SEQ0(LANE_REG(0505), 0x4f), + REG_SEQ0(LANE_REG(0605), 0x4f), + REG_SEQ0(LANE_REG(0304), 0x14), + REG_SEQ0(LANE_REG(0404), 0x14), + REG_SEQ0(LANE_REG(0504), 0x14), + REG_SEQ0(LANE_REG(0604), 0x14), + /* Keep Inter-Pair Skew in the limits */ + REG_SEQ0(LANE_REG(031e), 0x02), + REG_SEQ0(LANE_REG(041e), 0x02), + REG_SEQ0(LANE_REG(051e), 0x02), + REG_SEQ0(LANE_REG(061e), 0x02), +}; + static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0312), 0x00), REG_SEQ0(LANE_REG(0412), 0x00), @@ -819,7 +1014,12 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_= phy *hdptx) HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 - regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); + /* 3 lanes FRL mode */ + if (hdptx->hdmi_cfg.rate =3D=3D FRL_6G3L_RATE || + hdptx->hdmi_cfg.rate =3D=3D FRL_3G3L_RATE) + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x07); + else + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 ret =3D regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, (val & HDPTX_O_PHY_RDY) && @@ -963,6 +1163,80 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long l= ong rate, return true; } =20 +static int rk_hdptx_frl_lcpll_cmn_config(struct rk_hdptx_phy *hdptx) +{ + const struct lcpll_config *cfg =3D NULL; + int i; + + dev_dbg(hdptx->dev, "%s rate=3D%llu\n", __func__, hdptx->hdmi_cfg.rate); + + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { + if (hdptx->hdmi_cfg.rate =3D=3D rk_hdptx_frl_lcpll_cfg[i].rate) { + cfg =3D &rk_hdptx_frl_lcpll_cfg[i]; + break; + } + } + + if (!cfg) { + dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%llu\n", + __func__, hdptx->hdmi_cfg.rate); + return -EINVAL; + } + + rk_hdptx_pre_power_up(hdptx); + + regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16); + + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_cmn_init_seq); + + regmap_update_bits(hdptx->regmap, CMN_REG(0008), + LCPLL_EN_MASK | LCPLL_LCVCO_MODE_EN_MASK, + FIELD_PREP(LCPLL_EN_MASK, 1) | + FIELD_PREP(LCPLL_LCVCO_MODE_EN_MASK, cfg->lcvco_mode_en)); + + regmap_update_bits(hdptx->regmap, CMN_REG(001e), + LCPLL_PI_EN_MASK | LCPLL_100M_CLK_EN_MASK, + FIELD_PREP(LCPLL_PI_EN_MASK, cfg->pi_en) | + FIELD_PREP(LCPLL_100M_CLK_EN_MASK, cfg->clk_en_100m)); + + regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv); + regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc); + regmap_write(hdptx->regmap, CMN_REG(0022), + (cfg->pms_pdiv << 4) | cfg->pms_refdiv); + regmap_write(hdptx->regmap, CMN_REG(0023), + (cfg->pms_sdiv << 4) | cfg->pms_sdiv); + regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno); + regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign); + regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num); + + regmap_update_bits(hdptx->regmap, CMN_REG(002d), LCPLL_SDC_N_MASK, + FIELD_PREP(LCPLL_SDC_N_MASK, cfg->sdc_n)); + + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, + FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, + FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1)); + + return rk_hdptx_post_enable_pll(hdptx); +} + +static int rk_hdptx_frl_lcpll_ropll_cmn_config(struct rk_hdptx_phy *hdptx) +{ + dev_dbg(hdptx->dev, "%s rate=3D%llu\n", __func__, hdptx->hdmi_cfg.rate); + + rk_hdptx_pre_power_up(hdptx); + + /* ROPLL input reference clock from LCPLL (cascade mode) */ + regmap_write(hdptx->grf, GRF_HDPTX_CON0, + (LC_REF_CLK_SEL << 16) | LC_REF_CLK_SEL); + + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_ropll_cmn_init_seq); + + return rk_hdptx_post_enable_pll(hdptx); +} + static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; @@ -994,6 +1268,8 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hd= ptx_phy *hdptx) =20 rk_hdptx_pre_power_up(hdptx); =20 + regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq); =20 @@ -1032,6 +1308,28 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_= hdptx_phy *hdptx) return rk_hdptx_post_enable_pll(hdptx); } =20 +static int rk_hdptx_pll_cmn_config(struct rk_hdptx_phy *hdptx) +{ + if (hdptx->hdmi_cfg.rate <=3D HDMI20_MAX_RATE) + return rk_hdptx_tmds_ropll_cmn_config(hdptx); + + if (hdptx->hdmi_cfg.rate =3D=3D FRL_8G4L_RATE) + return rk_hdptx_frl_lcpll_ropll_cmn_config(hdptx); + + return rk_hdptx_frl_lcpll_cmn_config(hdptx); +} + +static int rk_hdptx_frl_lcpll_mode_config(struct rk_hdptx_phy *hdptx) +{ + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lntop_init_seq); + + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lane_init_seq); + + return rk_hdptx_post_enable_lane(hdptx); +} + static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) { rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq); @@ -1108,7 +1406,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_= phy *hdptx) if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - ret =3D rk_hdptx_tmds_ropll_cmn_config(hdptx); + ret =3D rk_hdptx_pll_cmn_config(hdptx); if (ret) goto dec_usage; } @@ -1409,7 +1707,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) int ret, lane; =20 if (mode !=3D PHY_MODE_DP) { - if (!hdptx->hdmi_cfg.rate) { + if (!hdptx->hdmi_cfg.rate && hdptx->hdmi_cfg.mode !=3D PHY_HDMI_MODE_FRL= ) { /* * FIXME: Temporary workaround to setup TMDS char rate * from the RK DW HDMI QP bridge driver. @@ -1455,7 +1753,11 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) + ret =3D rk_hdptx_frl_lcpll_mode_config(hdptx); + else + ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); + if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } @@ -1476,16 +1778,49 @@ static int rk_hdptx_phy_verify_hdmi_config(struct r= k_hdptx_phy *hdptx, { int i; =20 - if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RATE) - return -EINVAL; + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) { + unsigned long long frl_rate =3D 100000000ULL * hdmi_in->frl.lanes * + hdmi_in->frl.rate_per_lane; =20 - for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) - if (hdmi_in->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) + switch (hdmi_in->frl.rate_per_lane) { + case 3: + case 6: + case 8: + case 10: + case 12: break; + default: + return -EINVAL; + } =20 - if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && - !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL)) - return -EINVAL; + if (!hdmi_in->frl.lanes || hdmi_in->frl.lanes > 4) + return -EINVAL; + + if (frl_rate !=3D FRL_8G4L_RATE) { + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) + if (frl_rate =3D=3D rk_hdptx_frl_lcpll_cfg[i].rate) + break; + if (i =3D=3D ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg)) + return -EINVAL; + } + + if (hdmi_out) + hdmi_out->rate =3D frl_rate; + } else { + if (!hdmi_in->tmds_char_rate || hdmi_in->tmds_char_rate > HDMI20_MAX_RAT= E) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdmi_in->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) + break; + + if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && + !rk_hdptx_phy_clk_pll_calc(hdmi_in->tmds_char_rate, NULL)) + return -EINVAL; + + if (hdmi_out) + hdmi_out->rate =3D hdmi_in->tmds_char_rate; + } =20 switch (hdmi_in->bpc) { case 0: @@ -1498,10 +1833,8 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, return -EINVAL; } =20 - if (hdmi_out) { - hdmi_out->rate =3D hdmi_in->tmds_char_rate; + if (hdmi_out) hdmi_out->bpc =3D hdmi_in->bpc ?: 8; - } =20 return 0; } @@ -1761,6 +2094,31 @@ static int rk_hdptx_phy_set_voltages(struct rk_hdptx= _phy *hdptx, return 0; } =20 +static int rk_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, int = submode) +{ + struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); + + if (mode =3D=3D PHY_MODE_DP) + return 0; + + if (mode !=3D PHY_MODE_HDMI) { + dev_err(&phy->dev, "invalid PHY mode: %d\n", mode); + return -EINVAL; + } + + switch (submode) { + case PHY_HDMI_MODE_TMDS: + case PHY_HDMI_MODE_FRL: + hdptx->hdmi_cfg.mode =3D submode; + break; + default: + dev_err(&phy->dev, "invalid HDMI mode: %d\n", submode); + return -EINVAL; + } + + return 0; +} + static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opt= s *opts) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); @@ -1828,6 +2186,7 @@ static int rk_hdptx_phy_validate(struct phy *phy, enu= m phy_mode mode, static const struct phy_ops rk_hdptx_phy_ops =3D { .power_on =3D rk_hdptx_phy_power_on, .power_off =3D rk_hdptx_phy_power_off, + .set_mode =3D rk_hdptx_phy_set_mode, .configure =3D rk_hdptx_phy_configure, .validate =3D rk_hdptx_phy_validate, .owner =3D THIS_MODULE, @@ -1856,17 +2215,62 @@ static void rk_hdptx_phy_clk_unprepare(struct clk_h= w *hw) =20 static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hd= ptx) { + struct lcpll_config lcpll_hw; struct ropll_config ropll_hw; u64 fout, sdm; u32 mode, val; - int ret; + int ret, i; =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(0008), &mode); if (ret) return 0; =20 - if (mode & LCPLL_LCVCO_MODE_EN_MASK) + if (mode & LCPLL_LCVCO_MODE_EN_MASK) { + ret =3D regmap_read(hdptx->regmap, CMN_REG(0020), &val); + if (ret) + return 0; + lcpll_hw.pms_mdiv =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(0023), &val); + if (ret) + return 0; + lcpll_hw.pms_sdiv =3D val & 0xf; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002B), &val); + if (ret) + return 0; + lcpll_hw.sdm_num_sign =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002C), &val); + if (ret) + return 0; + lcpll_hw.sdm_num =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002A), &val); + if (ret) + return 0; + lcpll_hw.sdm_deno =3D val; + + ret =3D regmap_read(hdptx->regmap, CMN_REG(002D), &val); + if (ret) + return 0; + lcpll_hw.sdc_n =3D (val & LCPLL_SDC_N_MASK) >> 1; + + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { + const struct lcpll_config *cfg =3D &rk_hdptx_frl_lcpll_cfg[i]; + + if (cfg->pms_mdiv =3D=3D lcpll_hw.pms_mdiv && + cfg->pms_sdiv =3D=3D lcpll_hw.pms_sdiv && + cfg->sdm_num_sign =3D=3D lcpll_hw.sdm_num_sign && + cfg->sdm_num =3D=3D lcpll_hw.sdm_num && + cfg->sdm_deno =3D=3D lcpll_hw.sdm_deno && + cfg->sdc_n =3D=3D lcpll_hw.sdc_n) + return cfg->rate; + } + + dev_dbg(hdptx->dev, "%s no FRL match found\n", __func__); return 0; + } =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(0051), &val); if (ret) @@ -1943,6 +2347,9 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(str= uct clk_hw *hw, =20 rate =3D rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx); =20 + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) + return rate; + return DIV_ROUND_CLOSEST_ULL(rate * 8, hdptx->hdmi_cfg.bpc); } =20 @@ -1951,6 +2358,9 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) + return hdptx->hdmi_cfg.rate; + /* * FIXME: Temporarily allow altering TMDS char rate via CCF. * To be dropped as soon as the RK DW HDMI QP bridge driver @@ -1979,23 +2389,26 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw = *hw, unsigned long rate, unsigned long parent_rate) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); - unsigned long long tmds_rate =3D DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi= _cfg.bpc, 8); + unsigned long long link_rate =3D rate; + + if (hdptx->hdmi_cfg.mode !=3D PHY_HDMI_MODE_FRL) + link_rate =3D DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8); =20 - /* Revert any unlikely TMDS char rate change since round_rate() */ - if (hdptx->hdmi_cfg.rate !=3D tmds_rate) { + /* Revert any unlikely link rate change since round_rate() */ + if (hdptx->hdmi_cfg.rate !=3D link_rate) { dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu= \n", - tmds_rate, hdptx->hdmi_cfg.rate); - hdptx->hdmi_cfg.rate =3D tmds_rate; + link_rate, hdptx->hdmi_cfg.rate); + hdptx->hdmi_cfg.rate =3D link_rate; } =20 /* - * The TMDS char rate would be normally programmed in HW during + * The link rate would be normally programmed in HW during * phy_ops.power_on() or clk_ops.prepare() callbacks, but it might * happen that the former gets fired too late, i.e. after this call, * while the latter being executed only once, i.e. when clock remains * in the prepared state during rate changes. */ - return rk_hdptx_tmds_ropll_cmn_config(hdptx); + return rk_hdptx_pll_cmn_config(hdptx); } =20 static const struct clk_ops hdptx_phy_clk_ops =3D { --=20 2.51.0