From nobody Fri Oct 3 11:26:00 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B8FF340DBD for ; Tue, 2 Sep 2025 17:07:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756832842; cv=none; b=e3/NEan/OXCEvzzTMZylq0ETNC4lXVB7B/nvC0q8Ndwy0blNSRvSqvWH5FITIF11YwceDkEFBxXAoRXZz/Q/4ZoxsEmc1tGbujNCX7D58gzAfHSAw7VXn7V8FnL3ZksXr3SMqSFWmd00vNIMIIl0wfwm3gcYdyt+QMklpGtWWLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756832842; c=relaxed/simple; bh=p9G1JdZNHBB20Qe5ZLlqmEbY+P1qY7hzK//FQaEBq4w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uxQ9S9QEYc8i8Sv0lGqbV6fBdjwo3xkAtx8MDxSYPiC93EU+nNQHWheqhfSqyXroNOUC0b+SiH2eyzPWERkAyRotr0cflbKqTeC68L9rdok/XxQJH8AgCy5uKyY0IDkabRxoFEchU5itXZiLdq79keDWJ5uY1dSH2b69wZ7/Wu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=pHqNrY+N; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="pHqNrY+N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756832838; bh=p9G1JdZNHBB20Qe5ZLlqmEbY+P1qY7hzK//FQaEBq4w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pHqNrY+N3mjBpHj7h9Np5BDPKapnNxYvnrQXzeOAGKI8HtnIFXX5EPfwWSkIz3i/y tUD/nEEExEbYIBUZPCdQyaez4Y4X01ZwJ8ScgRVjC+t3igaf6EFbByj7mm0GXLzaiE pAb50nhqMjAGswxxp2F8hRypBsluV8Yp3ZqBLxo8CDrbCFcJJGqYpADUIRbZtUUT0/ 1mcpsWqp5N+/zSBOMX5SAAb2FV6cA/Hiv7IltdnIJhBV7n/Nri7g0o5UgIQQsetcwm 1sMIb2/CfTLu9tR9NSJQT0INuNpaNBeW9feFC3Hjn/Gn+RHmOQHtRliBRAkt6i1Evb mKJHf14x1V5kg== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 4D9F417E1301; Tue, 2 Sep 2025 19:07:18 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 02 Sep 2025 20:06:59 +0300 Subject: [PATCH 1/3] phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250902-phy-hdptx-fixes-v1-1-e8d9ef9748d6@collabora.com> References: <20250902-phy-hdptx-fixes-v1-0-e8d9ef9748d6@collabora.com> In-Reply-To: <20250902-phy-hdptx-fixes-v1-0-e8d9ef9748d6@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Dmitry Baryshkov , Algea Cao Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Andy Yan X-Mailer: b4 0.14.2 When making use of the clock provider functionality, the output clock does normally match the TMDS character rate, which is what the PHY PLL gets configured to. However, this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output_clock_rate =3D tmds_char_rate * 8 / bpc Since the existence of the clock divider wasn't taken into account when support for high bpc has been introduced, make the necessary adjustments to report the correct clock rate. Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth ma= nagement") Reported-by: Andy Yan Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 01bbf668e05ef94e24a3fa11f96f219c4f942451..aee03e8655f66d4b25de39bd2b2= bf49d7a8b5b86 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1037,7 +1037,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_h= dptx_phy *hdptx) =20 ret =3D rk_hdptx_post_enable_pll(hdptx); if (!ret) - hdptx->hw_rate =3D hdptx->hdmi_cfg.tmds_char_rate; + hdptx->hw_rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate = * 8, + hdptx->hdmi_cfg.bpc); =20 return ret; } @@ -1895,19 +1896,20 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_= hw *hw, unsigned long rate, * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with * a different rate argument. */ - return hdptx->hdmi_cfg.tmds_char_rate; + return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->h= dmi_cfg.bpc); } =20 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + unsigned long long tmds_rate =3D DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi= _cfg.bpc, 8); =20 /* Revert any unlikely TMDS char rate change since round_rate() */ - if (hdptx->hdmi_cfg.tmds_char_rate !=3D rate) { - dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\= n", - rate, hdptx->hdmi_cfg.tmds_char_rate); - hdptx->hdmi_cfg.tmds_char_rate =3D rate; + if (hdptx->hdmi_cfg.tmds_char_rate !=3D tmds_rate) { + dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu= \n", + tmds_rate, hdptx->hdmi_cfg.tmds_char_rate); + hdptx->hdmi_cfg.tmds_char_rate =3D tmds_rate; } =20 /* --=20 2.51.0