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All implementors of `FalconEngine` and `FalconHal` satisfy the requirements of `Send`, and this traits also already required `Sync`, so this a minor tweak. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 2 +- drivers/gpu/nova-core/falcon/hal.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index 2dbcdf26697beb7e52083675fc9ea62a6167fef8..b16207e7242fe1ac26b8552575b= 8b4e52f34cf6a 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -286,7 +286,7 @@ fn from(value: bool) -> Self { /// Each engine provides one base for `PFALCON` and `PFALCON2` registers. = The `ID` constant is used /// to identify a given Falcon instance with register I/O methods. pub(crate) trait FalconEngine: - Sync + RegisterBase + RegisterBase + Sized + Send + Sync + RegisterBase + RegisterBase += Sized { /// Singleton of the engine, used to identify it with register I/O met= hods. const ID: Self; diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/fa= lcon/hal.rs index b233bc365882f9add9b6eab33b8d462d7913df37..bba28845561795914e9a4dba277= d72bbac0b37dd 100644 --- a/drivers/gpu/nova-core/falcon/hal.rs +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -13,7 +13,7 @@ /// Implements chipset-specific low-level operations. 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However, this will change as we add more steps of the GSP boot process, some of which are rather cumbersome to perform on a partially-constructed GPU instance. Relatedly, booting the GSP typically happens only once in the GPU reset cycle. Most of the data created to complete this step (notably firmware loaded from user-space) is needed only temporary and can be discarded once the GSP is booted; it then makes all the more sense to store these as local variables of a dedicated method, instead of inside the `Gpu` structure where they as kept as long as the GPU is bound, using dozens of megabytes of host memory. Thus, introduce a `start_gsp` method on the `Gpu` struct, which is called by `probe` after the GPU is instantiated and will return the running GSP instance, once the code completing its boot is integrated. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/driver.rs | 10 +++++++++- drivers/gpu/nova-core/gpu.rs | 41 ++++++++++++++++++++++++++++++-------= ---- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 274989ea1fb4a5e3e6678a08920ddc76d2809ab2..1062014c0a488e959379f009c2e= 8029ffaa1e2f8 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -6,6 +6,8 @@ =20 #[pin_data] pub(crate) struct NovaCore { + // Placeholder for the real `Gsp` object once it is built. + pub(crate) gsp: (), #[pin] pub(crate) gpu: Gpu, _reg: auxiliary::Registration, @@ -40,8 +42,14 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo)= -> Result, + sec2_falcon: Falcon, } =20 #[pinned_drop] @@ -190,8 +192,8 @@ impl Gpu { /// TODO: this needs to be moved into a larger type responsible for bo= oting the whole GSP /// (`GspBooter`?). fn run_fwsec_frts( + &self, dev: &device::Device, - falcon: &Falcon, bar: &Bar0, bios: &Vbios, fb_layout: &FbLayout, @@ -208,7 +210,7 @@ fn run_fwsec_frts( =20 let fwsec_frts =3D FwsecFirmware::new( dev, - falcon, + &self.gsp_falcon, bar, bios, FwsecCommand::Frts { @@ -218,7 +220,7 @@ fn run_fwsec_frts( )?; =20 // Run FWSEC-FRTS to create the WPR2 region. - fwsec_frts.run(dev, falcon, bar)?; + fwsec_frts.run(dev, &self.gsp_falcon, bar)?; =20 // SCRATCH_E contains the error code for FWSEC-FRTS. let frts_status =3D regs::NV_PBUS_SW_SCRATCH_0E_FRTS_ERR::read(bar= ).frts_err_code(); @@ -263,6 +265,28 @@ fn run_fwsec_frts( } } =20 + /// Attempt to start the GSP. + /// + /// This is a GPU-dependent and complex procedure that involves loadin= g firmware files from + /// user-space, patching them with signatures, and building firmware-s= pecific intricate data + /// structures that the GSP will use at runtime. + /// + /// Upon return, the GSP is up and running, and its runtime object giv= en as return value. + pub(crate) fn start_gsp(&self, pdev: &pci::Device) -> R= esult<()> { + let dev =3D pdev.as_ref(); + + let bar =3D self.bar.access(dev)?; + + let bios =3D Vbios::new(dev, bar)?; + + let fb_layout =3D FbLayout::new(self.spec.chipset, bar)?; + dev_dbg!(dev, "{:#x?}\n", fb_layout); + + self.run_fwsec_frts(dev, bar, &bios, &fb_layout)?; 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So far, we relied on a static `NAMES` array for the latter, and some CString hackery for the former. Replace both with a new `name` const method that returns the lowercase name of a chipset instance. We can generate it using the `paste!` macro. Using this method removes the need to create a `CString` when loading firmware, and lets us remove a couple of utility functions that now have no user. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 8 +++----- drivers/gpu/nova-core/gpu.rs | 25 +++++++++++++++++-------- drivers/gpu/nova-core/util.rs | 20 -------------------- 3 files changed, 20 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 2931912ddba0ea1fe6d027ccec70b39cdb40344a..213d4506a53f83e7474861f6f81= f033a9760fb61 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -30,9 +30,7 @@ pub(crate) struct Firmware { =20 impl Firmware { pub(crate) fn new(dev: &device::Device, chipset: Chipset, ver: &str) -= > Result { - let mut chip_name =3D CString::try_from_fmt(fmt!("{chipset}"))?; - chip_name.make_ascii_lowercase(); - let chip_name =3D &*chip_name; + let chip_name =3D chipset.name(); =20 let request =3D |name_| { CString::try_from_fmt(fmt!("nvidia/{chip_name}/gsp/{name_}-{ve= r}.bin")) @@ -180,8 +178,8 @@ pub(crate) const fn create( let mut this =3D Self(firmware::ModInfoBuilder::new(module_name)); let mut i =3D 0; =20 - while i < gpu::Chipset::NAMES.len() { - this =3D this.make_entry_chipset(gpu::Chipset::NAMES[i]); + while i < gpu::Chipset::ALL.len() { + this =3D this.make_entry_chipset(gpu::Chipset::ALL[i].name()); i +=3D 1; } =20 diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 8343276e52e6a87a8ff1aff9fc484e00d4b57417..709afbe56c7f3b713bb249a022d= 68d81783d36f5 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -10,7 +10,6 @@ use crate::firmware::{Firmware, FIRMWARE_VERSION}; use crate::gfw; use crate::regs; -use crate::util; use crate::vbios::Vbios; use core::fmt; =20 @@ -28,13 +27,23 @@ impl Chipset { $( Chipset::$variant, )* ]; =20 - pub(crate) const NAMES: [&'static str; Self::ALL.len()] =3D [ - $( util::const_bytes_to_str( - util::to_lowercase_bytes::<{ stringify!($variant).= len() }>( - stringify!($variant) - ).as_slice() - ), )* - ]; + ::kernel::macros::paste!( + /// Returns the name of this chipset, in lowercase. + /// + /// # Examples + /// + /// ``` + /// let chipset =3D Chipset::GA102; + /// assert_eq!(chipset.name(), "ga102"); + /// ``` + pub(crate) const fn name(&self) -> &'static str { + match *self { + $( + Chipset::$variant =3D> stringify!([<$variant:lower>]), + )* + } + } + ); } =20 // TODO[FPRI]: replace with something like derive(FromPrimitive) diff --git a/drivers/gpu/nova-core/util.rs b/drivers/gpu/nova-core/util.rs index 76cedf3710d7bb248f62ed50381a70f8ffb3f19a..bf35f00cb732ee4fa6644854718= a0ad99051666a 100644 --- a/drivers/gpu/nova-core/util.rs +++ b/drivers/gpu/nova-core/util.rs @@ -3,26 +3,6 @@ use kernel::prelude::*; use kernel::time::{Delta, Instant, Monotonic}; =20 -pub(crate) const fn to_lowercase_bytes(s: &str) -> [u8; N]= { - let src =3D s.as_bytes(); - let mut dst =3D [0; N]; - let mut i =3D 0; - - while i < src.len() && i < N { - dst[i] =3D (src[i] as char).to_ascii_lowercase() as u8; - i +=3D 1; - } - - dst -} - -pub(crate) const fn const_bytes_to_str(bytes: &[u8]) -> &str { - match core::str::from_utf8(bytes) { - Ok(string) =3D> string, - Err(_) =3D> kernel::build_error!("Bytes are not valid UTF-8."), - } -} - /// Wait until `cond` is true or `timeout` elapsed. /// /// When `cond` evaluates to `Some`, its return value is returned. --=20 2.51.0 From nobody Fri Oct 3 10:15:34 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2042.outbound.protection.outlook.com [40.107.243.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BCD93128D4; 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However, as we eventually want each individual firmware constructor to request its own file (and get rid of `Firmware` altogether), move this code into a dedicated function that can be called by individual firmware types. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 213d4506a53f83e7474861f6f81f033a9760fb61..4e8654d294a2205ac6f0b05b6da= 8d959a415ced1 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -19,6 +19,19 @@ =20 pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; =20 +/// Requests the GPU firmware `name` suitable for `chipset`, with version = `ver`. +fn request_nv_firmware( + dev: &device::Device, + chipset: gpu::Chipset, + name: &str, + ver: &str, +) -> Result { + let chip_name =3D chipset.name(); + + CString::try_from_fmt(fmt!("nvidia/{chip_name}/gsp/{name}-{ver}.bin")) + .and_then(|path| firmware::Firmware::request(&path, dev)) +} + /// Structure encapsulating the firmware blobs required for the GPU to ope= rate. #[expect(dead_code)] pub(crate) struct Firmware { @@ -30,12 +43,7 @@ pub(crate) struct Firmware { =20 impl Firmware { pub(crate) fn new(dev: &device::Device, chipset: Chipset, ver: &str) -= > Result { - let chip_name =3D chipset.name(); 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Add basic support for it so subsequent patches can leverage it. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 62 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 4e8654d294a2205ac6f0b05b6da8d959a415ced1..32b685c8757b1106084577c2cc7= d5ef6056c1c64 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -4,11 +4,13 @@ //! to be loaded into a given execution unit. =20 use core::marker::PhantomData; +use core::mem::size_of; =20 use kernel::device; use kernel::firmware; use kernel::prelude::*; use kernel::str::CString; +use kernel::transmute::FromBytes; =20 use crate::dma::DmaObject; use crate::falcon::FalconFirmware; @@ -156,6 +158,66 @@ fn no_patch_signature(self) -> FirmwareDmaObject { } } =20 +/// Header common to most firmware files. +#[repr(C)] +#[derive(Debug, Clone)] +struct BinHdr { + /// Magic number, must be `0x10de`. + bin_magic: u32, + /// Version of the header. + bin_ver: u32, + /// Size in bytes of the binary (to be ignored). + bin_size: u32, + /// Offset of the start of the application-specific header. + header_offset: u32, + /// Offset of the start of the data payload. + data_offset: u32, + /// Size in bytes of the data payload. + data_size: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for BinHdr {} + +// A firmware blob starting with a `BinHdr`. +struct BinFirmware<'a> { + hdr: BinHdr, + fw: &'a [u8], +} + +#[expect(dead_code)] +impl<'a> BinFirmware<'a> { + /// Interpret `fw` as a firmware image starting with a [`BinHdr`], and= returns the + /// corresponding [`BinFirmware`] that can be used to extract its payl= oad. + fn new(fw: &'a firmware::Firmware) -> Result { + const BIN_MAGIC: u32 =3D 0x10de; + let fw =3D fw.data(); + + fw.get(0..size_of::()) + // Extract header. + .and_then(BinHdr::from_bytes_copy) + // Validate header. + .and_then(|hdr| { + if hdr.bin_magic =3D=3D BIN_MAGIC { + Some(hdr) + } else { + None + } + }) + .map(|hdr| Self { hdr, fw }) + .ok_or(EINVAL) + } + + /// Returns the data payload of the firmware, or `None` if the data ra= nge is out of bounds of + /// the firmware image. + fn data(&self) -> Option<&[u8]> { + let fw_start =3D self.hdr.data_offset as usize; + let fw_size =3D self.hdr.data_size as usize; + + self.fw.get(fw_start..fw_start + fw_size) + } +} + pub(crate) struct ModInfoBuilder(firmware::ModInfoBuilder<= N>); =20 impl ModInfoBuilder { --=20 2.51.0 From nobody Fri Oct 3 10:15:34 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2040.outbound.protection.outlook.com [40.107.244.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A339731AF31; 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It is loaded on the sec2 falcon core and is responsible for loading and running the RISC-V GSP bootloader into the GSP core. Add support for parsing the Booter firmware loaded from userspace, patch its signatures, and store it into a form that is ready to be loaded and executed on the sec2 falcon. Then, move the Booter instance from the `Firmware` struct to the `start_gsp` method since it doesn't need to be kept after the GSP is booted. We do not run Booter yet, as its own payload (the GSP bootloader and firmware image) still need to be prepared. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 4 +- drivers/gpu/nova-core/firmware.rs | 6 +- drivers/gpu/nova-core/firmware/booter.rs | 375 +++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gpu.rs | 10 + 4 files changed, 388 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index b16207e7242fe1ac26b8552575b8b4e52f34cf6a..37e6298195e49a9a29e81226abe= 16cd410c9adbc 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -293,7 +293,7 @@ pub(crate) trait FalconEngine: } =20 /// Represents a portion of the firmware to be loaded into a particular me= mory (e.g. IMEM or DMEM). -#[derive(Debug)] +#[derive(Debug, Clone)] pub(crate) struct FalconLoadTarget { /// Offset from the start of the source object to copy from. pub(crate) src_start: u32, @@ -304,7 +304,7 @@ pub(crate) struct FalconLoadTarget { } =20 /// Parameters for the falcon boot ROM. -#[derive(Debug)] +#[derive(Debug, Clone)] pub(crate) struct FalconBromParams { /// Offset in `DMEM`` of the firmware's signature. pub(crate) pkc_data_offset: u32, diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 32b685c8757b1106084577c2cc7d5ef6056c1c64..d954b1e98fda82c44f87d2103e3= 1fa717c392d79 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -17,6 +17,7 @@ use crate::gpu; use crate::gpu::Chipset; =20 +pub(crate) mod booter; pub(crate) mod fwsec; =20 pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; @@ -37,8 +38,6 @@ fn request_nv_firmware( /// Structure encapsulating the firmware blobs required for the GPU to ope= rate. #[expect(dead_code)] pub(crate) struct Firmware { - booter_load: firmware::Firmware, - booter_unload: firmware::Firmware, bootloader: firmware::Firmware, gsp: firmware::Firmware, } @@ -48,8 +47,6 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset,= ver: &str) -> Result { fw: &'a [u8], } =20 -#[expect(dead_code)] impl<'a> BinFirmware<'a> { /// Interpret `fw` as a firmware image starting with a [`BinHdr`], and= returns the /// corresponding [`BinFirmware`] that can be used to extract its payl= oad. diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs new file mode 100644 index 0000000000000000000000000000000000000000..a4cd9c84bea75b68565778841e7= 8a20cdec9333e --- /dev/null +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Support for loading and patching the `Booter` firmware. `Booter` is a = Heavy Secured firmware +//! running on [`Sec2`], that is used on Turing/Ampere to load the GSP fir= mware into the GSP falcon +//! (and optionally unload it through a separate firmware image). + +use core::marker::PhantomData; +use core::mem::size_of; +use core::ops::Deref; + +use kernel::device; +use kernel::prelude::*; +use kernel::transmute::FromBytes; + +use crate::dma::DmaObject; +use crate::driver::Bar0; +use crate::falcon::sec2::Sec2; +use crate::falcon::{Falcon, FalconBromParams, FalconFirmware, FalconLoadPa= rams, FalconLoadTarget}; +use crate::firmware::{BinFirmware, FirmwareDmaObject, FirmwareSignature, S= igned, Unsigned}; +use crate::gpu::Chipset; + +/// Local convenience function to return a copy of `S` by reinterpreting t= he bytes starting at +/// `offset` in `slice`. +fn frombytes_at(slice: &[u8], offset: usize) -> Resu= lt { + slice + .get(offset..offset + size_of::()) + .and_then(S::from_bytes_copy) + .ok_or(EINVAL) +} + +/// Heavy-Secured firmware header. +/// +/// Such firmwares have an application-specific payload that needs to be p= atched with a given +/// signature. +#[repr(C)] +#[derive(Debug, Clone)] +struct HsHeaderV2 { + /// Offset to the start of the signatures. + sig_prod_offset: u32, + /// Size in bytes of the signatures. + sig_prod_size: u32, + /// Offset to a `u32` containing the location at which to patch the si= gnature in the microcode + /// image. + patch_loc_offset: u32, + /// Offset to a `u32` containing the index of the signature to patch. + patch_sig_offset: u32, + /// Start offset to the signature metadata. + meta_data_offset: u32, + /// Size in bytes of the signature metadata. + meta_data_size: u32, + /// Offset to a `u32` containing the number of signatures in the signa= tures section. + num_sig_offset: u32, + /// Offset of the application-specific header. + header_offset: u32, + /// Size in bytes of the application-specific header. + header_size: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsHeaderV2 {} + +/// Heavy-Secured Firmware image container. +/// +/// This provides convenient access to the fields of [`HsHeaderV2`] that a= re actually indices to +/// read from in the firmware data. +struct HsFirmwareV2<'a> { + hdr: HsHeaderV2, + fw: &'a [u8], +} + +impl<'a> HsFirmwareV2<'a> { + /// Interprets the header of `bin_fw` as a [`HsHeaderV2`] and returns = an instance of + /// `HsFirmwareV2` for further parsing. + /// + /// Fails if the header pointed at by `bin_fw` is not within the bound= s of the firmware image. + fn new(bin_fw: &BinFirmware<'a>) -> Result { + frombytes_at::(bin_fw.fw, bin_fw.hdr.header_offset as = usize) + .map(|hdr| Self { hdr, fw: bin_fw.fw }) + } + + /// Returns the location at which the signatures should be patched in = the microcode image. + /// + /// Fails if the offset of the patch location is outside the bounds of= the firmware + /// image. + fn patch_location(&self) -> Result { + frombytes_at::(self.fw, self.hdr.patch_loc_offset as usize) + } + + /// Returns an iterator to the signatures of the firmware. The iterato= r can be empty if the + /// firmware is unsigned. + /// + /// Fails if the pointed signatures are outside the bounds of the firm= ware image. + fn signatures_iter(&'a self) -> Result>> { + let num_sig =3D frombytes_at::(self.fw, self.hdr.num_sig_offs= et as usize)?; + let iter =3D match self.hdr.sig_prod_size.checked_div(num_sig) { + // If there are no signatures, return an iterator that will yi= eld zero elements. + None =3D> (&[] as &[u8]).chunks_exact(1), + Some(sig_size) =3D> { + let patch_sig =3D frombytes_at::(self.fw, self.hdr.pa= tch_sig_offset as usize)?; + let signatures_start =3D (self.hdr.sig_prod_offset + patch= _sig) as usize; + + self.fw + // Get signatures range. + .get(signatures_start..signatures_start + self.hdr.sig= _prod_size as usize) + .ok_or(EINVAL)? + .chunks_exact(sig_size as usize) + } + }; + + // Map the byte slices into signatures. + Ok(iter.map(BooterSignature)) + } +} + +/// Signature parameters, as defined in the firmware. +#[repr(C)] +struct HsSignatureParams { + /// Fuse version to use. + fuse_ver: u32, + /// Mask of engine IDs this firmware applies to. + engine_id_mask: u32, + /// ID of the microcode. + ucode_id: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsSignatureParams {} + +impl HsSignatureParams { + /// Returns the signature parameters contained in `hs_fw`. + /// + /// Fails if the meta data parameter of `hs_fw` is outside the bounds = of the firmware image, or + /// if its size doesn't match that of [`HsSignatureParams`]. + fn new(hs_fw: &HsFirmwareV2<'_>) -> Result { + let start =3D hs_fw.hdr.meta_data_offset as usize; + let end =3D start + .checked_add(hs_fw.hdr.meta_data_size as usize) + .ok_or(EINVAL)?; + + hs_fw + .fw + .get(start..end) + .and_then(Self::from_bytes_copy) + .ok_or(EINVAL) + } +} + +/// Header for code and data load offsets. +#[repr(C)] +#[derive(Debug, Clone)] +struct HsLoadHeaderV2 { + // Offset at which the code starts. + os_code_offset: u32, + // Total size of the code, for all apps. + os_code_size: u32, + // Offset at which the data starts. + os_data_offset: u32, + // Size of the data. + os_data_size: u32, + // Number of apps following this header. Each app is described by a [`= HsLoadHeaderV2App`]. + num_apps: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsLoadHeaderV2 {} + +impl HsLoadHeaderV2 { + /// Returns the load header contained in `hs_fw`. + /// + /// Fails if the header pointed at by `hs_fw` is not within the bounds= of the firmware image. + fn new(hs_fw: &HsFirmwareV2<'_>) -> Result { + frombytes_at::(hs_fw.fw, hs_fw.hdr.header_offset as usize) + } +} + +/// Header for app code loader. +#[repr(C)] +#[derive(Debug, Clone)] +struct HsLoadHeaderV2App { + /// Offset at which to load the app code. + offset: u32, + /// Length in bytes of the app code. + len: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for HsLoadHeaderV2App {} + +impl HsLoadHeaderV2App { + /// Returns the [`HsLoadHeaderV2App`] for app `idx` of `hs_fw`. + /// + /// Fails if `idx` is larger than the number of apps declared in `hs_f= w`, or if the header is + /// not within the bounds of the firmware image. + fn new(hs_fw: &HsFirmwareV2<'_>, idx: u32) -> Result { + let load_hdr =3D HsLoadHeaderV2::new(hs_fw)?; + if idx >=3D load_hdr.num_apps { + Err(EINVAL) + } else { + frombytes_at::( + hs_fw.fw, + (hs_fw.hdr.header_offset as usize) + // Skip the load header... + .checked_add(size_of::()) + // ... and jump to app header `idx`. + .and_then(|offset| { + offset.checked_add((idx as usize).checked_mul(size= _of::())?) + }) + .ok_or(EINVAL)?, + ) + } + } +} + +/// Signature for Booter firmware. Their size is encoded into the header a= nd not known a compile +/// time, so we just wrap a byte slices on which we can implement [`Firmwa= reSignature`]. +struct BooterSignature<'a>(&'a [u8]); + +impl<'a> AsRef<[u8]> for BooterSignature<'a> { + fn as_ref(&self) -> &[u8] { + self.0 + } +} + +impl<'a> FirmwareSignature for BooterSignature<'a> {} + +/// The `Booter` loader firmware, responsible for loading the GSP. +pub(crate) struct BooterFirmware { + // Load parameters for `IMEM` falcon memory. + imem_load_target: FalconLoadTarget, + // Load parameters for `DMEM` falcon memory. + dmem_load_target: FalconLoadTarget, + // BROM falcon parameters. + brom_params: FalconBromParams, + // Device-mapped firmware image. + ucode: FirmwareDmaObject, +} + +impl FirmwareDmaObject { + fn new_booter(dev: &device::Device, data: &[u8]) -> Res= ult { + DmaObject::from_data(dev, data).map(|ucode| Self(ucode, PhantomDat= a)) + } +} + +#[derive(Copy, Clone, Debug, PartialEq)] +pub(crate) enum BooterKind { + Loader, + #[expect(unused)] + Unloader, +} + +impl BooterFirmware { + /// Parses the Booter firmware contained in `fw`, and patches the corr= ect signature so it is + /// ready to be loaded and run on `falcon`. + pub(crate) fn new( + dev: &device::Device, + kind: BooterKind, + chipset: Chipset, + ver: &str, + falcon: &Falcon<::Target>, + bar: &Bar0, + ) -> Result { + let fw_name =3D match kind { + BooterKind::Loader =3D> "booter_load", + BooterKind::Unloader =3D> "booter_unload", + }; + let fw =3D super::request_nv_firmware(dev, chipset, fw_name, ver)?; + let bin_fw =3D BinFirmware::new(&fw)?; + + // The binary firmware embeds a Heavy-Secured firmware. + let hs_fw =3D HsFirmwareV2::new(&bin_fw)?; + + // The Heavy-Secured firmware embeds a firmware load descriptor. + let load_hdr =3D HsLoadHeaderV2::new(&hs_fw)?; + + // Offset in `ucode` where to patch the signature. + let patch_loc =3D hs_fw.patch_location()?; + + let sig_params =3D HsSignatureParams::new(&hs_fw)?; + let brom_params =3D FalconBromParams { + // `load_hdr.os_data_offset` is an absolute index, but `pkc_da= ta_offset` is from the + // signature patch location. + pkc_data_offset: patch_loc + .checked_sub(load_hdr.os_data_offset) + .ok_or(EINVAL)?, + engine_id_mask: u16::try_from(sig_params.engine_id_mask).map_e= rr(|_| EINVAL)?, + ucode_id: u8::try_from(sig_params.ucode_id).map_err(|_| EINVAL= )?, + }; + let app0 =3D HsLoadHeaderV2App::new(&hs_fw, 0)?; + + // Object containing the firmware microcode to be signature-patche= d. + let ucode =3D bin_fw + .data() + .ok_or(EINVAL) + .and_then(|data| FirmwareDmaObject::::new_booter(dev,= data))?; + + let ucode_signed =3D { + let mut signatures =3D hs_fw.signatures_iter()?.peekable(); + + if signatures.peek().is_none() { + // If there are no signatures, then the firmware is unsign= ed. + ucode.no_patch_signature() + } else { + // Obtain the version from the fuse register, and extract = the corresponding + // signature. + let reg_fuse_version =3D falcon.signature_reg_fuse_version( + bar, + brom_params.engine_id_mask, + brom_params.ucode_id, + )?; + + // `0` means the last signature should be used. + const FUSE_VERSION_USE_LAST_SIG: u32 =3D 0; + let signature =3D match reg_fuse_version { + FUSE_VERSION_USE_LAST_SIG =3D> signatures.last(), + // Otherwise hardware fuse version needs to be subtrac= ted to obtain the index. + reg_fuse_version =3D> { + let Some(idx) =3D sig_params.fuse_ver.checked_sub(= reg_fuse_version) else { + dev_err!(dev, "invalid fuse version for Booter= firmware\n"); + return Err(EINVAL); + }; + signatures.nth(idx as usize) + } + } + .ok_or(EINVAL)?; + + ucode.patch_signature(&signature, patch_loc as usize)? + } + }; + + Ok(Self { + imem_load_target: FalconLoadTarget { + src_start: app0.offset, + dst_start: 0, + len: app0.len, + }, + dmem_load_target: FalconLoadTarget { + src_start: load_hdr.os_data_offset, + dst_start: 0, + len: load_hdr.os_data_size, + }, + brom_params, + ucode: ucode_signed, + }) + } +} + +impl FalconLoadParams for BooterFirmware { + fn imem_load_params(&self) -> FalconLoadTarget { + self.imem_load_target.clone() + } + + fn dmem_load_params(&self) -> FalconLoadTarget { + self.dmem_load_target.clone() + } + + fn brom_params(&self) -> FalconBromParams { + self.brom_params.clone() + } + + fn boot_addr(&self) -> u32 { + self.imem_load_target.src_start + } +} + +impl Deref for BooterFirmware { + type Target =3D DmaObject; + + fn deref(&self) -> &Self::Target { + &self.ucode.0 + } +} + +impl FalconFirmware for BooterFirmware { + type Target =3D Sec2; +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 709afbe56c7f3b713bb249a022d68d81783d36f5..2f5ae89ab80b237eba5d5535122= 9be78cd471a72 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -6,6 +6,7 @@ use crate::falcon::{gsp::Gsp, sec2::Sec2, Falcon}; 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Its presentation is a bit peculiar as the GSP bootloader expects to be given a DMA address to a 3-levels page table mapping the GSP firmware at address 0 of its own address space. Prepare such a structure containing the DMA-mapped firmware as well as the DMA-mapped page tables, and a way to obtain the DMA handle of the level 0 page table. Then, move the GSP firmware instance from the `Firmware` struct to the `start_gsp` method since it doesn't need to be kept after the GSP is booted. As we are performing the required ELF section parsing and radix3 page table building, remove these items from the TODO file. Signed-off-by: Alexandre Courbot --- Documentation/gpu/nova/core/todo.rst | 17 --- drivers/gpu/nova-core/firmware.rs | 3 +- drivers/gpu/nova-core/firmware/gsp.rs | 237 ++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gpu.rs | 6 + drivers/gpu/nova-core/gsp.rs | 4 + drivers/gpu/nova-core/nova_core.rs | 1 + 6 files changed, 249 insertions(+), 19 deletions(-) diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/= core/todo.rst index 89431fec9041b1f35cc55799c91f48dc6bc918eb..0972cb905f7ae64dfbaef480827= 6757319009e9c 100644 --- a/Documentation/gpu/nova/core/todo.rst +++ b/Documentation/gpu/nova/core/todo.rst @@ -229,23 +229,6 @@ Rust abstraction for debugfs APIs. GPU (general) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -Parse firmware headers ----------------------- - -Parse ELF headers from the firmware files loaded from the filesystem. - -| Reference: ELF utils -| Complexity: Beginner -| Contact: Abdiel Janulgue - -Build radix3 page table ------------------------ - -Build the radix3 page table to map the firmware. - -| Complexity: Intermediate -| Contact: Abdiel Janulgue - Initial Devinit support ----------------------- =20 diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index d954b1e98fda82c44f87d2103e31fa717c392d79..cef910a7c2dc360139fafc2a01a= 050a9df40e45f 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -19,6 +19,7 @@ =20 pub(crate) mod booter; pub(crate) mod fwsec; +pub(crate) mod gsp; =20 pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; =20 @@ -39,7 +40,6 @@ fn request_nv_firmware( #[expect(dead_code)] pub(crate) struct Firmware { bootloader: firmware::Firmware, - gsp: firmware::Firmware, } =20 impl Firmware { @@ -48,7 +48,6 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset,= ver: &str) -> Result(elf: &'a [u8], name: &'b str) -> O= ption<&'a [u8]> { + let hdr =3D &elf + .get(0..size_of::()) + .and_then(Elf64Hdr::from_bytes)? + .0; + + // Get all the section headers. + let shdr =3D { + let shdr_num =3D usize::from(hdr.e_shnum); + let shdr_start =3D usize::try_from(hdr.e_shoff).ok()?; + let shdr_end =3D shdr_num + .checked_mul(size_of::()) + .and_then(|v| v.checked_add(shdr_start))?; + + elf.get(shdr_start..shdr_end) + .map(|slice| slice.as_ptr()) + .filter(|ptr| ptr.align_offset(align_of::()) =3D=3D 0) + // `FromBytes::from_bytes` does not support slices yet, so= build it manually. + // + // SAFETY: + // * `get` guarantees that the slice is within the bounds = of `elf` and of size + // `elf64_shdr * shdr_num`. + // * We checked that `ptr` had the correct alignment for `= elf64_shdr`. + .map(|ptr| unsafe { + core::slice::from_raw_parts(ptr.cast::(), shdr_num) + })? + }; + + // Get the strings table. + let strhdr =3D shdr.get(usize::from(hdr.e_shstrndx))?; + + // Find the section which name matches `name` and return it. + shdr.iter() + .find(|sh| { + let Some(name_idx) =3D strhdr + .sh_offset + .checked_add(u64::from(sh.sh_name)) + .and_then(|idx| usize::try_from(idx).ok()) + else { + return false; + }; + + // Get the start of the name. + elf.get(name_idx..) + // Stop at the first `0`. + .and_then(|nstr| nstr.get(0..=3Dnstr.iter().position(|= b| *b =3D=3D 0)?)) + // Convert into CStr. This should never fail because o= f the line above. + .and_then(|nstr| CStr::from_bytes_with_nul(nstr).ok()) + // Convert into str. + .and_then(|c_str| c_str.to_str().ok()) + // Check that the name matches. + .map(|str| str =3D=3D name) + .unwrap_or(false) + }) + // Return the slice containing the section. + .and_then(|sh| { + let start =3D usize::try_from(sh.sh_offset).ok()?; + let end =3D usize::try_from(sh.sh_size) + .ok() + .and_then(|sh_size| start.checked_add(sh_size))?; + + elf.get(start..end) + }) + } +} + +/// GSP firmware with 3-level radix page tables for the GSP bootloader. +/// +/// The bootloader expects firmware to be mapped starting at address 0 in = GSP's virtual address +/// space: +/// +/// ```text +/// Level 0: 1 page, 1 entry -> points to first level 1 page +/// Level 1: Multiple pages/entries -> each entry points to a level 2 pa= ge +/// Level 2: Multiple pages/entries -> each entry points to a firmware p= age +/// ``` +/// +/// Each page is 4KB, each entry is 8 bytes (64-bit DMA address). +/// Also known as "Radix3" firmware. +#[pin_data] +pub(crate) struct GspFirmware { + /// The GSP firmware inside a [`VVec`], device-mapped via a SG table. + #[pin] + fw: SGTable>>, + /// Level 2 page table whose entries contain DMA addresses of firmware= pages. + #[pin] + level2: SGTable>>, + /// Level 1 page table whose entries contain DMA addresses of level 2 = pages. + #[pin] + level1: SGTable>>, + /// Level 0 page table (single 4KB page) with one entry: DMA address o= f first level 1 page. + level0: DmaObject, + /// Size in bytes of the firmware contained in [`Self::fw`]. + pub size: usize, + /// Device-mapped GSP signatures matching the GPU's [`Chipset`]. + signatures: DmaObject, +} + +impl GspFirmware { + /// Loads the GSP firmware binaries, map them into `dev`'s address-spa= ce, and creates the page + /// tables expected by the GSP bootloader to load it. + pub(crate) fn new<'a, 'b>( + dev: &'a device::Device, + chipset: Chipset, + ver: &'b str, + ) -> Result + 'a> { + let fw =3D super::request_nv_firmware(dev, chipset, "gsp", ver)?; + + let fw_section =3D elf::elf64_section(fw.data(), ".fwimage").ok_or= (EINVAL)?; + + let sigs_section =3D match chipset.arch() { + Architecture::Ampere =3D> ".fwsignature_ga10x", + _ =3D> return Err(ENOTSUPP), + }; + let signatures =3D elf::elf64_section(fw.data(), sigs_section) + .ok_or(EINVAL) + .and_then(|data| DmaObject::from_data(dev, data))?; + + let size =3D fw_section.len(); + + // Move the firmware into a vmalloc'd vector and map it into the d= evice address + // space. + let fw_vvec =3D VVec::with_capacity(fw_section.len(), GFP_KERNEL) + .and_then(|mut v| { + v.extend_from_slice(fw_section, GFP_KERNEL)?; + Ok(v) + }) + .map_err(|_| ENOMEM)?; + + Ok(try_pin_init!(&this in Self { + fw <- SGTable::new(dev, fw_vvec, DataDirection::ToDevice, GFP_= KERNEL), + level2 <- { + // Allocate the level 2 page table, map the firmware onto = it, and map it into the + // device address space. + // SAFETY: `this` is a valid pointer, and `fw` has been in= itialized. + let fw_sg_table =3D unsafe { &(*this.as_ptr()).fw }; + VVec::::with_capacity( + fw_sg_table.iter().count() * core::mem::size_of::= (), + GFP_KERNEL, + ) + .map_err(|_| ENOMEM) + .and_then(|level2| map_into_lvl(fw_sg_table, level2)) + .map(|level2| SGTable::new(dev, level2, DataDirection::ToD= evice, GFP_KERNEL))? + }, + level1 <- { + // Allocate the level 1 page table, map the level 2 page t= able onto it, and map it + // into the device address space. + // SAFETY: `this` is a valid pointer, and `level2` has bee= n initialized. + let level2_sg_table =3D unsafe { &(*this.as_ptr()).level2 = }; + VVec::::with_capacity( + level2_sg_table.iter().count() * core::mem::size_of::<= u64>(), + GFP_KERNEL, + ) + .map_err(|_| ENOMEM) + .and_then(|level1| map_into_lvl(level2_sg_table, level1)) + .map(|level1| SGTable::new(dev, level1, DataDirection::ToD= evice, GFP_KERNEL))? + }, + level0: { + // Allocate the level 0 page table as a device-visible DMA= object, and map the + // level 1 page table onto it. + // SAFETY: `this` is a valid pointer, and `level1` has bee= n initialized. + let level1_sg_table =3D unsafe { &(*this.as_ptr()).level1 = }; + let mut level0 =3D DmaObject::new(dev, GSP_PAGE_SIZE)?; + // SAFETY: we are the only owner of this newly-created obj= ect, making races + // impossible. + let level0_slice =3D unsafe { level0.as_slice_mut(0, GSP_P= AGE_SIZE) }?; + level0_slice[0..core::mem::size_of::()].copy_from_sli= ce( + #[allow(clippy::useless_conversion)] + &(u64::from(level1_sg_table.iter().next().unwrap().dma= _address())) + .to_le_bytes(), + ); + + level0 + }, + size, + signatures, + })) + } + + #[expect(unused)] + /// Returns the DMA handle of the radix3 level 0 page table. + pub(crate) fn radix3_dma_handle(&self) -> DmaAddress { + self.level0.dma_handle() + } +} + +/// Build a page table from a scatter-gather list. +/// +/// Takes each DMA-mapped region from `sg_table` and writes page table ent= ries +/// for all 4KB pages within that region. For example, a 16KB SG entry bec= omes +/// 4 consecutive page table entries. +fn map_into_lvl(sg_table: &SGTable>>, mut dst: VVec) ->= Result> { + for sg_entry in sg_table.iter() { + // Number of pages we need to map. + let num_pages =3D (sg_entry.dma_len() as usize).div_ceil(GSP_PAGE_= SIZE); + + for i in 0..num_pages { + let entry =3D sg_entry.dma_address() + (i as u64 * GSP_PAGE_SI= ZE as u64); + dst.extend_from_slice(&entry.to_le_bytes(), GFP_KERNEL)?; + } + } + + Ok(dst) +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 2f5ae89ab80b237eba5d55351229be78cd471a72..547e5dd31aeb9650b226c267de5= f0412173b3fe0 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -8,6 +8,7 @@ use crate::fb::SysmemFlush; use crate::firmware::booter::{BooterFirmware, BooterKind}; use crate::firmware::fwsec::{FwsecCommand, FwsecFirmware}; +use crate::firmware::gsp::GspFirmware; use crate::firmware::{Firmware, FIRMWARE_VERSION}; use crate::gfw; use crate::regs; @@ -289,6 +290,11 @@ pub(crate) fn start_gsp(&self, pdev: &pci::Device) -> Result<()> =20 let bios =3D Vbios::new(dev, bar)?; =20 + let _gsp_fw =3D KBox::pin_init( + GspFirmware::new(dev, self.spec.chipset, FIRMWARE_VERSION)?, + GFP_KERNEL, + )?; + let fb_layout =3D FbLayout::new(self.spec.chipset, bar)?; dev_dbg!(dev, "{:#x?}\n", fb_layout); =20 diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs new file mode 100644 index 0000000000000000000000000000000000000000..a0e7ec5f6c9c959d57540b3ebf4= b782f2e002b08 --- /dev/null +++ b/drivers/gpu/nova-core/gsp.rs @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 + +pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; +pub(crate) const GSP_PAGE_SIZE: usize =3D 1 << GSP_PAGE_SHIFT; diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index cb2bbb30cba142265b354c9acf70349a6e40759e..fffcaee2249fe6cd7f55a7291c1= e44be42e791d9 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -9,6 +9,7 @@ mod firmware; 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It is a regular binary firmware file containing a specific header. Create a type holding the DMA-mapped firmware as well as useful information extracted from the header, and hook it into our firmware structure for later use. The GSP bootloader is stored into the `GspFirmware` structure, since it is part of the GSP firmware package. This makes the `Firmware` structure empty, so remove it. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 18 +------ drivers/gpu/nova-core/firmware/gsp.rs | 7 +++ drivers/gpu/nova-core/firmware/riscv.rs | 89 +++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gpu.rs | 5 +- 4 files changed, 98 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index cef910a7c2dc360139fafc2a01a050a9df40e45f..af7356a14def2ee92c3285878ea= 4de64eb48d344 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -15,11 +15,11 @@ use crate::dma::DmaObject; use crate::falcon::FalconFirmware; use crate::gpu; -use crate::gpu::Chipset; =20 pub(crate) mod booter; pub(crate) mod fwsec; pub(crate) mod gsp; +pub(crate) mod riscv; =20 pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; =20 @@ -36,22 +36,6 @@ fn request_nv_firmware( .and_then(|path| firmware::Firmware::request(&path, dev)) } =20 -/// Structure encapsulating the firmware blobs required for the GPU to ope= rate. -#[expect(dead_code)] -pub(crate) struct Firmware { - bootloader: firmware::Firmware, -} - -impl Firmware { - pub(crate) fn new(dev: &device::Device, chipset: Chipset, ver: &str) -= > Result { - let request =3D |name| request_nv_firmware(dev, chipset, name, ver= ); - - Ok(Firmware { - bootloader: request("bootloader")?, - }) - } -} - /// Structure used to describe some firmwares, notably FWSEC-FRTS. #[repr(C)] #[derive(Debug, Clone)] diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index ddbf3f27dd795b9b2480f0392160a3bfb68c6ab7..a377c5138294c9cc70714cd18ee= d54d679aba835 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -8,6 +8,7 @@ use kernel::scatterlist::SGTable; =20 use crate::dma::DmaObject; +use crate::firmware::riscv::RiscvFirmware; use crate::gpu::Architecture; use crate::gpu::Chipset; use crate::gsp::GSP_PAGE_SIZE; @@ -127,6 +128,8 @@ pub(crate) struct GspFirmware { pub size: usize, /// Device-mapped GSP signatures matching the GPU's [`Chipset`]. signatures: DmaObject, + /// GSP bootloader, verifies the GSP firmware before loading and runni= ng it. + bootloader: RiscvFirmware, } =20 impl GspFirmware { @@ -160,6 +163,9 @@ pub(crate) fn new<'a, 'b>( }) .map_err(|_| ENOMEM)?; =20 + let bl =3D super::request_nv_firmware(dev, chipset, "bootloader", = ver)?; + let bootloader =3D RiscvFirmware::new(dev, &bl)?; + Ok(try_pin_init!(&this in Self { fw <- SGTable::new(dev, fw_vvec, DataDirection::ToDevice, GFP_= KERNEL), level2 <- { @@ -207,6 +213,7 @@ pub(crate) fn new<'a, 'b>( }, size, signatures, + bootloader, })) } =20 diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-cor= e/firmware/riscv.rs new file mode 100644 index 0000000000000000000000000000000000000000..b7eef29956995c49ab1466bb6a7= 1a756731bf78a --- /dev/null +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Support for firmware binaries designed to run on a RISC-V core. Such f= irmwares files have a +//! dedicated header. + +use kernel::device; +use kernel::firmware::Firmware; +use kernel::prelude::*; +use kernel::transmute::FromBytes; + +use crate::dma::DmaObject; +use crate::firmware::BinFirmware; + +/// Descriptor for microcode running on a RISC-V core. +#[repr(C)] +#[derive(Debug)] +struct RmRiscvUCodeDesc { + version: u32, + bootloader_offset: u32, + bootloader_size: u32, + bootloader_param_offset: u32, + bootloader_param_size: u32, + riscv_elf_offset: u32, + riscv_elf_size: u32, + app_version: u32, + manifest_offset: u32, + manifest_size: u32, + monitor_data_offset: u32, + monitor_data_size: u32, + monitor_code_offset: u32, + monitor_code_size: u32, +} + +// SAFETY: all bit patterns are valid for this type, and it doesn't use in= terior mutability. +unsafe impl FromBytes for RmRiscvUCodeDesc {} + +impl RmRiscvUCodeDesc { + /// Interprets the header of `bin_fw` as a [`RmRiscvUCodeDesc`] and re= turns it. + /// + /// Fails if the header pointed at by `bin_fw` is not within the bound= s of the firmware image. + fn new(bin_fw: &BinFirmware<'_>) -> Result { + let offset =3D bin_fw.hdr.header_offset as usize; + + bin_fw + .fw + .get(offset..offset + size_of::()) + .and_then(Self::from_bytes_copy) + .ok_or(EINVAL) + } +} + +/// A parsed firmware for a RISC-V core, ready to be loaded and run. +#[expect(unused)] +pub(crate) struct RiscvFirmware { + /// Offset at which the code starts in the firmware image. + code_offset: u32, + /// Offset at which the data starts in the firmware image. + data_offset: u32, + /// Offset at which the manifest starts in the firmware image. + manifest_offset: u32, + /// Application version. + app_version: u32, + /// Device-mapped firmware image. + ucode: DmaObject, +} + +impl RiscvFirmware { + /// Parses the RISC-V firmware image contained in `fw`. + pub(crate) fn new(dev: &device::Device, fw: &Firmware) = -> Result { + let bin_fw =3D BinFirmware::new(fw)?; + + let riscv_desc =3D RmRiscvUCodeDesc::new(&bin_fw)?; + + let ucode =3D { + let start =3D bin_fw.hdr.data_offset as usize; + let len =3D bin_fw.hdr.data_size as usize; + + DmaObject::from_data(dev, fw.data().get(start..start + len).ok= _or(EINVAL)?)? + }; + + Ok(Self { + ucode, + code_offset: riscv_desc.monitor_code_offset, + data_offset: riscv_desc.monitor_data_offset, + manifest_offset: riscv_desc.manifest_offset, + app_version: riscv_desc.app_version, + }) + } +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 547e5dd31aeb9650b226c267de5f0412173b3fe0..b7798257e463a2a0e29e33a1e10= 76380de077bee 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -9,7 +9,7 @@ use crate::firmware::booter::{BooterFirmware, BooterKind}; use crate::firmware::fwsec::{FwsecCommand, FwsecFirmware}; use crate::firmware::gsp::GspFirmware; -use crate::firmware::{Firmware, FIRMWARE_VERSION}; +use crate::firmware::FIRMWARE_VERSION; use crate::gfw; use crate::regs; use crate::vbios::Vbios; @@ -179,7 +179,6 @@ pub(crate) struct Gpu { spec: Spec, /// MMIO mapping of PCI BAR 0 bar: Arc>, - fw: Firmware, /// System memory page required for flushing all pending GPU-side memo= ry writes done through /// PCIE into system memory, via sysmembar (A GPU-initiated HW memory-= barrier operation). sysmem_flush: SysmemFlush, @@ -318,7 +317,6 @@ pub(crate) fn new( ) -> Result> { let bar =3D devres_bar.access(pdev.as_ref())?; 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It should eventually be dropped for a newer version before the driver becomes able to do anything useful. The newer firmware is expected to iron out some of the inelegances of 570.144, notably related to packaging. Reviewed-by: John Hubbard Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index af7356a14def2ee92c3285878ea4de64eb48d344..9a97e97a3c7b4ac65b66e4e5f09= 2839720ded82d 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -21,7 +21,7 @@ pub(crate) mod gsp; pub(crate) mod riscv; =20 -pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; +pub(crate) const FIRMWARE_VERSION: &str =3D "570.144"; =20 /// Requests the GPU firmware `name` suitable for `chipset`, with version = `ver`. fn request_nv_firmware( --=20 2.51.0 From nobody Fri Oct 3 10:15:34 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2049.outbound.protection.outlook.com [40.107.93.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A855C32254B; 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Rust definitions for the types needed for Nova core will be generated using the Rust bindgen tool. This patch adds the base module to allow inclusion of the generated bindings. The generated bindings themselves are added by subsequent patches when they are first used. Currently we only intend to support a single firmware version, 570.144, with these bindings. Longer term we intend to move to a more stable GSP interface that isn't tied to specific firmware versions. Signed-off-by: Alistair Popple Reviewed-by: John Hubbard [acourbot@nvidia.com: adapt the bindings module comment a bit] Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/nvfw.rs | 6 +++++ drivers/gpu/nova-core/nvfw/r570_144.rs | 29 +++++++++++++++++++++= ++++ drivers/gpu/nova-core/nvfw/r570_144_bindings.rs | 1 + 4 files changed, 37 insertions(+) diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index fffcaee2249fe6cd7f55a7291c1e44be42e791d9..db197498b0b7b1ff9234ef6645a= 4ea5ff44bd285 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -10,6 +10,7 @@ mod gfw; mod gpu; mod gsp; +mod nvfw; mod regs; mod util; mod vbios; diff --git a/drivers/gpu/nova-core/nvfw.rs b/drivers/gpu/nova-core/nvfw.rs new file mode 100644 index 0000000000000000000000000000000000000000..779db25095892d6d88652fb7da2= 43a8d2f7db047 --- /dev/null +++ b/drivers/gpu/nova-core/nvfw.rs @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 + +mod r570_144; + +// Alias to avoid repeating the version number with every use. +use r570_144 as bindings; diff --git a/drivers/gpu/nova-core/nvfw/r570_144.rs b/drivers/gpu/nova-core= /nvfw/r570_144.rs new file mode 100644 index 0000000000000000000000000000000000000000..2e7bba80fa8b9c5fcb4e2688782= 5d2cca3f7b6b7 --- /dev/null +++ b/drivers/gpu/nova-core/nvfw/r570_144.rs @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Firmware bindings. +//! +//! Imports the generated bindings by `bindgen`. +//! +//! This module may not be directly used. Please abstract or re-export the= needed symbols in the +//! parent module instead. + +#![cfg_attr(test, allow(deref_nullptr))] +#![cfg_attr(test, allow(unaligned_references))] +#![cfg_attr(test, allow(unsafe_op_in_unsafe_fn))] +#![allow( + dead_code, + unused_imports, + clippy::all, + clippy::undocumented_unsafe_blocks, + clippy::ptr_as_ptr, + clippy::ref_as_ptr, + missing_docs, + non_camel_case_types, + non_upper_case_globals, + non_snake_case, + improper_ctypes, + unreachable_pub, + unsafe_op_in_unsafe_fn +)] +use kernel::ffi; +include!("r570_144_bindings.rs"); diff --git a/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs b/drivers/gpu/= nova-core/nvfw/r570_144_bindings.rs new file mode 100644 index 0000000000000000000000000000000000000000..cec5940325151e407aa90128a35= cb683afd436d7 --- /dev/null +++ b/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0 --=20 2.51.0 From nobody Fri Oct 3 10:15:34 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2053.outbound.protection.outlook.com [40.107.244.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62A51322C77; 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This information is dependent on the firmware itself, so first we need to import and abstract the required firmware bindings in the `nvfw` module. Then, a new FB HAL method is introduced in `fb::hal` that uses these bindings and hardware information to compute the correct layout information. This information is then used in `fb` and the result made visible in `FbLayout`. These 3 things are grouped into the same patch to avoid lots of unused warnings that would be tedious to work around. As they happen in different files, they should not be too difficult to track separately. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/fb.rs | 64 +++++++++++- drivers/gpu/nova-core/fb/hal.rs | 4 + drivers/gpu/nova-core/fb/hal/ga100.rs | 5 + drivers/gpu/nova-core/fb/hal/ga102.rs | 10 ++ drivers/gpu/nova-core/fb/hal/tu102.rs | 11 +++ drivers/gpu/nova-core/firmware/gsp.rs | 2 +- drivers/gpu/nova-core/firmware/riscv.rs | 2 +- drivers/gpu/nova-core/gpu.rs | 4 +- drivers/gpu/nova-core/gsp.rs | 3 + drivers/gpu/nova-core/nvfw.rs | 86 ++++++++++++++++ drivers/gpu/nova-core/nvfw/r570_144.rs | 1 - drivers/gpu/nova-core/nvfw/r570_144_bindings.rs | 125 ++++++++++++++++++++= ++++ 12 files changed, 310 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index b0e860498b883815b3861b8717f8ee1832d25440..8f75d7fff99f845cd6ba0d9c273= 4fc556c0097bb 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -10,7 +10,9 @@ =20 use crate::dma::DmaObject; use crate::driver::Bar0; +use crate::firmware::gsp::GspFirmware; use crate::gpu::Chipset; +use crate::nvfw; use crate::regs; =20 mod hal; @@ -87,14 +89,28 @@ pub(crate) fn unregister(&self, bar: &Bar0) { #[derive(Debug)] #[expect(dead_code)] pub(crate) struct FbLayout { + /// Range of the framebuffer. Starts at `0`. pub(crate) fb: Range, + /// VGA workspace, small area of reserved memory at the end of the fra= mebuffer. pub(crate) vga_workspace: Range, + /// FRTS range. pub(crate) frts: Range, + /// Memory area containing the GSP bootloader image. + pub(crate) boot: Range, + /// Memory area containing the GSP firmware image. + pub(crate) elf: Range, + /// WPR2 heap. + pub(crate) wpr2_heap: Range, + // WPR2 region range, starting with an instance of `GspFwWprMeta`. + pub(crate) wpr2: Range, + pub(crate) heap: Range, + pub(crate) vf_partition_count: u8, } =20 impl FbLayout { - /// Computes the FB layout. - pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Result { + /// Computes the FB layout for `chipset`, for running the `bl` GSP boo= tloader and `gsp` GSP + /// firmware. + pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) = -> Result { let hal =3D hal::fb_hal(chipset); =20 let fb =3D { @@ -138,10 +154,54 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Re= sult { frts_base..frts_base + FRTS_SIZE }; =20 + let boot =3D { + const BOOTLOADER_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_4= K); + let bootloader_size =3D gsp_fw.bootloader.ucode.size() as u64; + let bootloader_base =3D (frts.start - bootloader_size).align_d= own(BOOTLOADER_DOWN_ALIGN); + + bootloader_base..bootloader_base + bootloader_size + }; + + let elf =3D { + const ELF_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_64K); + let elf_size =3D gsp_fw.size as u64; + let elf_addr =3D (boot.start - elf_size).align_down(ELF_DOWN_A= LIGN); + + elf_addr..elf_addr + elf_size + }; + + let wpr2_heap =3D { + const WPR2_HEAP_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_1M= ); + let wpr2_heap_size =3D hal.libos_params().wpr_heap_size(chipse= t, fb.end); + let wpr2_heap_addr =3D (elf.start - wpr2_heap_size).align_down= (WPR2_HEAP_DOWN_ALIGN); + + wpr2_heap_addr..(elf.start).align_down(WPR2_HEAP_DOWN_ALIGN) + }; + + let wpr2 =3D { + const WPR2_DOWN_ALIGN: Alignment =3D Alignment::new(SZ_1M); + let wpr2_addr =3D (wpr2_heap.start - size_of::() as u64) + .align_down(WPR2_DOWN_ALIGN); + + wpr2_addr..frts.end + }; + + let heap =3D { + const HEAP_SIZE: u64 =3D SZ_1M as u64; + + wpr2.start - HEAP_SIZE..wpr2.start + }; + Ok(Self { fb, vga_workspace, frts, + boot, + elf, + wpr2_heap, + wpr2, + heap, + vf_partition_count: 0, }) } } diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index 2f914948bb9a9842fd00a4c6381420b74de81c3f..d87d285d75841134e5837577254= 3344131d804b3 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -4,6 +4,7 @@ =20 use crate::driver::Bar0; use crate::gpu::Chipset; +use crate::nvfw::LibosParams; =20 mod ga100; mod ga102; @@ -23,6 +24,9 @@ pub(crate) trait FbHal { =20 /// Returns the VRAM size, in bytes. fn vidmem_size(&self, bar: &Bar0) -> u64; + + /// Returns the libos requirements to start the GSP firmware. + fn libos_params(&self) -> &'static LibosParams; } =20 /// Returns the HAL corresponding to `chipset`. diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs index 871c42bf033acd0b9c5735c43d408503075099af..3ca46861ab4ffd267a50ffe04ba= ad7e861fae04a 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -6,6 +6,7 @@ =20 use crate::driver::Bar0; use crate::fb::hal::FbHal; +use crate::nvfw::LibosParams; use crate::regs; =20 use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; @@ -51,6 +52,10 @@ fn supports_display(&self, bar: &Bar0) -> bool { fn vidmem_size(&self, bar: &Bar0) -> u64 { super::tu102::vidmem_size_gp102(bar) } + + fn libos_params(&self) -> &'static LibosParams { + super::tu102::libos_params_tu102() + } } =20 const GA100: Ga100 =3D Ga100; diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs index a73b77e3971513d088211a97ad8e50b00a9131f7..8f54aff4418316f7bdf873a64e6= 95df97d0eda28 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -4,12 +4,18 @@ =20 use crate::driver::Bar0; use crate::fb::hal::FbHal; +use crate::nvfw; +use crate::nvfw::LibosParams; use crate::regs; =20 fn vidmem_size_ga102(bar: &Bar0) -> u64 { regs::NV_USABLE_FB_SIZE_IN_MB::read(bar).usable_fb_size() } =20 +fn libos_params_ga102() -> &'static LibosParams { + &nvfw::LIBOS3_PARAMS +} + struct Ga102; =20 impl FbHal for Ga102 { @@ -30,6 +36,10 @@ fn supports_display(&self, bar: &Bar0) -> bool { fn vidmem_size(&self, bar: &Bar0) -> u64 { vidmem_size_ga102(bar) } + + fn libos_params(&self) -> &'static LibosParams { + libos_params_ga102() + } } =20 const GA102: Ga102 =3D Ga102; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs index b022c781caf4514b4060fa2083cdc0ca12573c5b..220e865242dcc11271d28860b2e= a5834fbe00399 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -2,7 +2,10 @@ =20 use crate::driver::Bar0; use crate::fb::hal::FbHal; +use crate::nvfw; +use crate::nvfw::LibosParams; use crate::regs; + use kernel::prelude::*; =20 /// Shift applied to the sysmem address before it is written into `NV_PFB_= NISO_FLUSH_SYSMEM_ADDR`, @@ -34,6 +37,10 @@ pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 { regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::read(bar).usable_fb_size() } =20 +pub(super) fn libos_params_tu102() -> &'static LibosParams { + &nvfw::LIBOS2_PARAMS +} + struct Tu102; =20 impl FbHal for Tu102 { @@ -52,6 +59,10 @@ fn supports_display(&self, bar: &Bar0) -> bool { fn vidmem_size(&self, bar: &Bar0) -> u64 { vidmem_size_gp102(bar) } + + fn libos_params(&self) -> &'static LibosParams { + libos_params_tu102() + } } =20 const TU102: Tu102 =3D Tu102; diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index a377c5138294c9cc70714cd18eed54d679aba835..61e664db38ad4f73d4a344ea3ee= b944c486e24f4 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -129,7 +129,7 @@ pub(crate) struct GspFirmware { /// Device-mapped GSP signatures matching the GPU's [`Chipset`]. signatures: DmaObject, /// GSP bootloader, verifies the GSP firmware before loading and runni= ng it. - bootloader: RiscvFirmware, + pub bootloader: RiscvFirmware, } =20 impl GspFirmware { diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-cor= e/firmware/riscv.rs index b7eef29956995c49ab1466bb6a71a756731bf78a..b90acfc81e7898ed1726430001d= 31ebbc976f9f1 100644 --- a/drivers/gpu/nova-core/firmware/riscv.rs +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -61,7 +61,7 @@ pub(crate) struct RiscvFirmware { /// Application version. app_version: u32, /// Device-mapped firmware image. - ucode: DmaObject, + pub ucode: DmaObject, } =20 impl RiscvFirmware { diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index b7798257e463a2a0e29e33a1e1076380de077bee..7bb0dc80d6e08c3c1b95ea13c5f= bbee63153252e 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -289,12 +289,12 @@ pub(crate) fn start_gsp(&self, pdev: &pci::Device) -> Result<()> =20 let bios =3D Vbios::new(dev, bar)?; =20 - let _gsp_fw =3D KBox::pin_init( + let gsp_fw =3D KBox::pin_init( GspFirmware::new(dev, self.spec.chipset, FIRMWARE_VERSION)?, GFP_KERNEL, )?; =20 - let fb_layout =3D FbLayout::new(self.spec.chipset, bar)?; + let fb_layout =3D FbLayout::new(self.spec.chipset, bar, &gsp_fw)?; dev_dbg!(dev, "{:#x?}\n", fb_layout); =20 self.run_fwsec_frts(dev, bar, &bios, &fb_layout)?; diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index a0e7ec5f6c9c959d57540b3ebf4b782f2e002b08..ead471746ccad02f1e0d6ec114a= b2aa67b1ed733 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use kernel::ptr::Alignment; + pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; pub(crate) const GSP_PAGE_SIZE: usize =3D 1 << GSP_PAGE_SHIFT; +pub(crate) const GSP_HEAP_ALIGNMENT: Alignment =3D Alignment::new(1 << 20); diff --git a/drivers/gpu/nova-core/nvfw.rs b/drivers/gpu/nova-core/nvfw.rs index 779db25095892d6d88652fb7da243a8d2f7db047..1e0d134904fca3ac5a56b6828ff= 11894584029bd 100644 --- a/drivers/gpu/nova-core/nvfw.rs +++ b/drivers/gpu/nova-core/nvfw.rs @@ -4,3 +4,89 @@ =20 // Alias to avoid repeating the version number with every use. use r570_144 as bindings; + +use core::ops::Range; + +use kernel::ptr::Alignable; +use kernel::sizes::SZ_1M; + +use crate::gpu::Chipset; +use crate::gsp; + +/// Dummy type to group methods related to heap parameters for running the= GSP firmware. +pub(crate) struct GspFwHeapParams(()); + +impl GspFwHeapParams { + /// Returns the amount of GSP-RM heap memory used during GSP-RM boot a= nd initialization (up to + /// and including the first client subdevice allocation). + fn base_rm_size(_chipset: Chipset) -> u64 { + // TODO: this needs to be updated to return the correct value for = Hopper+ once support for + // them is added: + // u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100) + u64::from(bindings::GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X) + } + + /// Returns the amount of heap memory required to support a single cha= nnel allocation. + fn client_alloc_size() -> u64 { + u64::from(bindings::GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE) + .align_up(gsp::GSP_HEAP_ALIGNMENT) + .unwrap_or(u64::MAX) + } + + /// Returns the amount of memory to reserve for management purposes fo= r a framebuffer of size + /// `fb_size`. + fn management_overhead(fb_size: u64) -> u64 { + let fb_size_gb =3D fb_size.div_ceil(kernel::sizes::SZ_1G as u64); + + u64::from(bindings::GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB) + .saturating_mul(fb_size_gb) + .align_up(gsp::GSP_HEAP_ALIGNMENT) + .unwrap_or(u64::MAX) + } +} + +/// Heap memory requirements and constraints for a given version of the GS= P LIBOS. +pub(crate) struct LibosParams { + /// The base amount of heap required by the GSP operating system, in b= ytes. + pub(crate) carveout_size: u64, + /// The minimum and maximum sizes allowed for the GSP FW heap, in byte= s. + pub(crate) allowed_heap_size: Range, +} + +/// Version 2 of the GSP LIBOS (Turing and GA100) +pub(crate) const LIBOS2_PARAMS: LibosParams =3D LibosParams { + carveout_size: bindings::GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2 as u64, + allowed_heap_size: bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB a= s u64 * SZ_1M as u64 + ..bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB as u64 * SZ_1M= as u64, +}; + +/// Version 3 of the GSP LIBOS (GA102+) +pub(crate) const LIBOS3_PARAMS: LibosParams =3D LibosParams { + carveout_size: bindings::GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL as= u64, + allowed_heap_size: bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETA= L_MIN_MB as u64 + * SZ_1M as u64 + ..bindings::GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB as u= 64 * SZ_1M as u64, +}; + +impl LibosParams { + /// Returns the amount of memory (in bytes) to allocate for the WPR he= ap for a framebuffer size + /// of `fb_size` (in bytes) for `chipset`. + pub(crate) fn wpr_heap_size(&self, chipset: Chipset, fb_size: u64) -> = u64 { + // The WPR heap will contain the following: + // LIBOS carveout, + self.carveout_size + // RM boot working memory, + .saturating_add(GspFwHeapParams::base_rm_size(chipset)) + // One RM client, + .saturating_add(GspFwHeapParams::client_alloc_size()) + // Overhead for memory management. + .saturating_add(GspFwHeapParams::management_overhead(fb_size)) + // Clamp to the supported heap sizes. + .clamp(self.allowed_heap_size.start, self.allowed_heap_size.en= d - 1) + } +} + +/// Structure passed to the GSP bootloader, containing the framebuffer lay= out as well as the DMA +/// addresses of the GSP bootloader and firmware. +#[repr(transparent)] +pub(crate) struct GspFwWprMeta(bindings::GspFwWprMeta); diff --git a/drivers/gpu/nova-core/nvfw/r570_144.rs b/drivers/gpu/nova-core= /nvfw/r570_144.rs index 2e7bba80fa8b9c5fcb4e26887825d2cca3f7b6b7..bb8074797b550c7976a7432b418= 41c6bf61bf5f8 100644 --- a/drivers/gpu/nova-core/nvfw/r570_144.rs +++ b/drivers/gpu/nova-core/nvfw/r570_144.rs @@ -12,7 +12,6 @@ #![cfg_attr(test, allow(unsafe_op_in_unsafe_fn))] #![allow( dead_code, - unused_imports, clippy::all, clippy::undocumented_unsafe_blocks, clippy::ptr_as_ptr, diff --git a/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs b/drivers/gpu/= nova-core/nvfw/r570_144_bindings.rs index cec5940325151e407aa90128a35cb683afd436d7..0407000cca2296e713cc4701b63= 5718fe51488cb 100644 --- a/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs +++ b/drivers/gpu/nova-core/nvfw/r570_144_bindings.rs @@ -1 +1,126 @@ // SPDX-License-Identifier: GPL-2.0 + +pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2: u32 =3D 0; +pub const GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL: u32 =3D 23068672; +pub const GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X: u32 =3D 8388608; +pub const GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB: u32 =3D 98304; +pub const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE: u32 =3D 100663296; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB: u32 =3D 64; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB: u32 =3D 256; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB: u32 =3D 88; +pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB: u32 =3D 280; +pub type __u8 =3D ffi::c_uchar; +pub type __u16 =3D ffi::c_ushort; +pub type __u32 =3D ffi::c_uint; +pub type __u64 =3D ffi::c_ulonglong; +pub type u8_ =3D __u8; +pub type u16_ =3D __u16; +pub type u32_ =3D __u32; +pub type u64_ =3D __u64; +#[repr(C)] +#[derive(Copy, Clone)] +pub struct GspFwWprMeta { + pub magic: u64_, + pub revision: u64_, + pub sysmemAddrOfRadix3Elf: u64_, + pub sizeOfRadix3Elf: u64_, + pub sysmemAddrOfBootloader: u64_, + pub sizeOfBootloader: u64_, + pub bootloaderCodeOffset: u64_, + pub bootloaderDataOffset: u64_, + pub bootloaderManifestOffset: u64_, + pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1, + pub gspFwRsvdStart: u64_, + pub nonWprHeapOffset: u64_, + pub nonWprHeapSize: u64_, + pub gspFwWprStart: u64_, + pub gspFwHeapOffset: u64_, + pub gspFwHeapSize: u64_, + pub gspFwOffset: u64_, + pub bootBinOffset: u64_, + pub frtsOffset: u64_, + pub frtsSize: u64_, + pub gspFwWprEnd: u64_, + pub fbSize: u64_, + pub vgaWorkspaceOffset: u64_, + pub vgaWorkspaceSize: u64_, + pub bootCount: u64_, + pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2, + pub gspFwHeapVfPartitionCount: u8_, + pub flags: u8_, + pub padding: [u8_; 2usize], + pub pmuReservedSize: u32_, + pub verified: u64_, +} +#[repr(C)] +#[derive(Copy, Clone)] +pub union GspFwWprMeta__bindgen_ty_1 { + pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_1__bindgen_ty_1, + pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_1__bindgen_ty_2, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_1 { + pub sysmemAddrOfSignature: u64_, + pub sizeOfSignature: u64_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_1__bindgen_ty_2 { + pub gspFwHeapFreeListWprOffset: u32_, + pub unused0: u32_, + pub unused1: u64_, +} +impl Default for GspFwWprMeta__bindgen_ty_1 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +#[repr(C)] +#[derive(Copy, Clone)] +pub union GspFwWprMeta__bindgen_ty_2 { + pub __bindgen_anon_1: GspFwWprMeta__bindgen_ty_2__bindgen_ty_1, + pub __bindgen_anon_2: GspFwWprMeta__bindgen_ty_2__bindgen_ty_2, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_1 { + pub partitionRpcAddr: u64_, + pub partitionRpcRequestOffset: u16_, + pub partitionRpcReplyOffset: u16_, + pub elfCodeOffset: u32_, + pub elfDataOffset: u32_, + pub elfCodeSize: u32_, + pub elfDataSize: u32_, + pub lsUcodeVersion: u32_, +} +#[repr(C)] +#[derive(Debug, Default, Copy, Clone)] +pub struct GspFwWprMeta__bindgen_ty_2__bindgen_ty_2 { + pub partitionRpcPadding: [u32_; 4usize], + pub sysmemAddrOfCrashReportQueue: u64_, + pub sizeOfCrashReportQueue: u32_, + pub lsUcodeVersionPadding: [u32_; 1usize], +} +impl Default for GspFwWprMeta__bindgen_ty_2 { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} +impl Default for GspFwWprMeta { + fn default() -> Self { + let mut s =3D ::core::mem::MaybeUninit::::uninit(); + unsafe { + ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1); + s.assume_init() + } + } +} --=20 2.51.0