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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250902-microchip-qspi-v1-1-37af59a0406a@microchip.com> References: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> In-Reply-To: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Nicolas Ferre" , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus CC: , , , , Dharma Balasubiramani X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756792344; l=878; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=g9qQXv2V8dA8IDQzFPk9fFZ2WneEXRTGvShebfzPtjM=; b=RXLzmMxnP+ToN+Z5oDPtF+Ea94CKvLTLwp5jSikf1MtD2AeOR7+ez1eDz8FFGXArQU76S7HRC HyNXMhbLmr4DKegxye+QNurlMaBOIchdFnsq2nOnOmPZ9VClBFbWItx X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= Document the sam9x75 quad spi that supports interface to serial memories operating in - Single-bit SPI, Dual SPI, Quad SPI and Octal SPI - Single Data Rate or Double Data Rate modes Signed-off-by: Dharma Balasubiramani --- Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Doc= umentation/devicetree/bindings/spi/atmel,quadspi.yaml index b0d99bc10535..c17114123034 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -17,6 +17,7 @@ properties: enum: - atmel,sama5d2-qspi - microchip,sam9x60-qspi + - microchip,sam9x7-ospi - microchip,sama7g5-qspi - microchip,sama7g5-ospi =20 --=20 2.43.0 From nobody Fri Oct 3 11:14:51 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2B932E0B77; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250902-microchip-qspi-v1-2-37af59a0406a@microchip.com> References: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> In-Reply-To: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Nicolas Ferre" , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus CC: , , , , Dharma Balasubiramani X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756792344; l=1008; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=e9VWFRSwNpYXqnNmw9kbScIHMnZuxvIjyF1UMqscb90=; b=CO/fzW2/g67HTEueiWARb6WQARJam9NyTFZ58DKURxITPnaOkQ9Gdva4yY1aw6hsH3A0ZaB+z LQHJWeg68T2DEZZmD6ea3x1LT8SbjjXKLDnC+/PocJ2pOok16NkwDqE X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= sama7d65 has 2 instances of the QSPI controller: =E2=80=A2 One Octal Serial Peripheral Interface (QSPI0) supporting DDR. Oct= al, Twin-Quad, HyperFlashTM and OctaFlashTM protocols supported. =E2=80=A2 One Quad Serial Peripheral Interface (QSPI1) supporting DDR/SDR. Signed-off-by: Dharma Balasubiramani --- Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Doc= umentation/devicetree/bindings/spi/atmel,quadspi.yaml index c17114123034..30ab42c95c08 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -18,6 +18,8 @@ properties: - atmel,sama5d2-qspi - microchip,sam9x60-qspi - microchip,sam9x7-ospi + - microchip,sama7d65-qspi + - microchip,sama7d65-ospi - microchip,sama7g5-qspi - microchip,sama7g5-ospi =20 --=20 2.43.0 From nobody Fri Oct 3 11:14:51 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B075D2E1F1C; Tue, 2 Sep 2025 05:53:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="45366267" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Sep 2025 22:53:15 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 1 Sep 2025 22:52:45 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 1 Sep 2025 22:52:40 -0700 From: Dharma Balasubiramani Date: Tue, 2 Sep 2025 11:22:20 +0530 Subject: [PATCH 3/5] spi: atmel-quadspi: add padcalib, 2xgclk, and dllon capabilities Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250902-microchip-qspi-v1-3-37af59a0406a@microchip.com> References: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> In-Reply-To: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Nicolas Ferre" , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus CC: , , , , Dharma Balasubiramani , Varshini Rajendran X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756792344; l=5762; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=5JBcqmcHgI/B+uULblX7KzhNUtP6rsZ4FszumigJ6xc=; b=KJLwwD9ImNsoAPK9a4UWF5NPzOxEXxmTS1gxhtirQp4HoCeol57zVJy6aHVG0/9qIXL5bfzEu FMHmUG8nldmBYeBuAQdHUl6jTuqhoblX30keLMseGBWJ8DoqNsdl9Ey X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= Introduce capability flags for SoC-specific variations of the QuadSPI controller: - has_padcalib: controller supports pad calibration - has_2xgclk: requires GCLK at half the data rate (2x clocking) - has_dllon: controller supports DLL clock Set `has_padcalib` for Octal controllers that provide pad calibration support. Use `has_2xgclk` for controllers that require the GCLK to run at twice the data rate. Differentiate SoC integration variants with the `has_dllon` flag and set it as needed. Signed-off-by: Varshini Rajendran Signed-off-by: Dharma Balasubiramani --- drivers/spi/atmel-quadspi.c | 92 +++++++++++++++++++++++++++++------------= ---- 1 file changed, 60 insertions(+), 32 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 4e9bfd26aa80..83cea5faff78 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -262,6 +262,9 @@ struct atmel_qspi_caps { bool has_ricr; bool octal; bool has_dma; + bool has_2xgclk; + bool has_padcalib; + bool has_dllon; }; =20 struct atmel_qspi_ops; @@ -1027,13 +1030,25 @@ static int atmel_qspi_set_pad_calibration(struct at= mel_qspi *aq) aq, QSPI_PCALCFG); =20 /* DLL On + start calibration. */ - atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); + if (aq->caps->has_dllon) + atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); + /* If there is no DLL support only start calibration. */ + else + atmel_qspi_write(QSPI_CR_STPCAL, aq, QSPI_CR); =20 - /* Check synchronization status before updating configuration. */ - ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, - (val & QSPI_SR2_DLOCK) && - !(val & QSPI_SR2_CALBSY), 40, - ATMEL_QSPI_TIMEOUT); + /* + * Check DLL clock lock and synchronization status before updating + * configuration. + */ + if (aq->caps->has_dllon) + ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, + (val & QSPI_SR2_DLOCK) && + !(val & QSPI_SR2_CALBSY), 40, + ATMEL_QSPI_TIMEOUT); + else + ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, + !(val & QSPI_SR2_CALBSY), 40, + ATMEL_QSPI_TIMEOUT); =20 /* Refresh analogic blocks every 1 ms.*/ atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, @@ -1049,23 +1064,28 @@ static int atmel_qspi_set_gclk(struct atmel_qspi *a= q) int ret; =20 /* Disable DLL before setting GCLK */ - status =3D atmel_qspi_read(aq, QSPI_SR2); - if (status & QSPI_SR2_DLOCK) { - atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); + if (aq->caps->has_dllon) { + status =3D atmel_qspi_read(aq, QSPI_SR2); + if (status & QSPI_SR2_DLOCK) { + atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); + ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, + !(val & QSPI_SR2_DLOCK), 40, + ATMEL_QSPI_TIMEOUT); + if (ret) + return ret; + } =20 - ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, - !(val & QSPI_SR2_DLOCK), 40, - ATMEL_QSPI_TIMEOUT); - if (ret) - return ret; + if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) + atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); + else + atmel_qspi_write(0, aq, QSPI_DLLCFG); } =20 - if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) - atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); + if (aq->caps->has_2xgclk) + ret =3D clk_set_rate(aq->gclk, 2 * aq->target_max_speed_hz); else - atmel_qspi_write(0, aq, QSPI_DLLCFG); + ret =3D clk_set_rate(aq->gclk, aq->target_max_speed_hz); =20 - ret =3D clk_set_rate(aq->gclk, aq->target_max_speed_hz); if (ret) { dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); return ret; @@ -1088,11 +1108,16 @@ static int atmel_qspi_sama7g5_init(struct atmel_qsp= i *aq) if (ret) return ret; =20 - if (aq->caps->octal) { + /* + * Check if the SoC supports pad calibration in Octal SPI mode. + * Proceed only if both the capabilities are true. + */ + if (aq->caps->octal && aq->caps->has_padcalib) { ret =3D atmel_qspi_set_pad_calibration(aq); if (ret) return ret; - } else { + /* Start DLL on only if the SoC supports the same */ + } else if (aq->caps->has_dllon) { atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR); ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, (val & QSPI_SR2_DLOCK), 40, @@ -1458,19 +1483,19 @@ static int atmel_qspi_sama7g5_suspend(struct atmel_= qspi *aq) =20 clk_disable_unprepare(aq->gclk); =20 - atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); - ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, - !(val & QSPI_SR2_DLOCK), 40, - ATMEL_QSPI_TIMEOUT); - if (ret) - return ret; - - ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, - !(val & QSPI_SR2_CALBSY), 40, - ATMEL_QSPI_TIMEOUT); - if (ret) - return ret; + if (aq->caps->has_dllon) { + atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); + ret =3D readl_poll_timeout(aq->regs + QSPI_SR2, val, + !(val & QSPI_SR2_DLOCK), 40, + ATMEL_QSPI_TIMEOUT); + if (ret) + return ret; + } =20 + if (aq->caps->has_padcalib) + return readl_poll_timeout(aq->regs + QSPI_SR2, val, + !(val & QSPI_SR2_CALBSY), 40, + ATMEL_QSPI_TIMEOUT); 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Mon, 1 Sep 2025 22:52:50 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 1 Sep 2025 22:52:46 -0700 From: Dharma Balasubiramani Date: Tue, 2 Sep 2025 11:22:21 +0530 Subject: [PATCH 4/5] spi: atmel-quadspi: add support for SAM9X7 QSPI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250902-microchip-qspi-v1-4-37af59a0406a@microchip.com> References: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> In-Reply-To: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Nicolas Ferre" , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus CC: , , , , Dharma Balasubiramani , Varshini Rajendran X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756792344; l=1692; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=f7DOA5wDFdEWR6ikCwi4zK/5qKnnx4GBTbYYi9JaLJw=; b=+go7VqpZKGWssX4BiHB4VD7oA4MOm2sbqhMKZvwE3v7H9D3JptWnXIujiVjp/AISEQOofGT7u 2PTTzt9ftwLCZoZCuSVMZyzB3R7kmC5SGQsBZUz0msuKNGsHke0LbF+ X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= Add support for the QuadSPI controller found on the SAM9X7 SoC. This controller does not implement pad calibration. It supports operation up to 100 MHz, and requires the GCK to run at twice the data rate. Signed-off-by: Varshini Rajendran Signed-off-by: Dharma Balasubiramani --- drivers/spi/atmel-quadspi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 83cea5faff78..342cdd6e8d64 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -63,6 +63,7 @@ =20 #define SAMA7G5_QSPI0_MAX_SPEED_HZ 200000000 #define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ 133000000 +#define SAM9X7_QSPI_MAX_SPEED_HZ 100000000 =20 /* Bitfields in QSPI_CR (Control Register) */ #define QSPI_CR_QSPIEN BIT(0) @@ -1627,6 +1628,16 @@ static const struct atmel_qspi_caps atmel_sam9x60_qs= pi_caps =3D { .has_ricr =3D true, }; =20 +static const struct atmel_qspi_caps atmel_sam9x7_ospi_caps =3D { + .max_speed_hz =3D SAM9X7_QSPI_MAX_SPEED_HZ, + .has_gclk =3D true, + .octal =3D true, + .has_dma =3D true, + .has_2xgclk =3D true, + .has_padcalib =3D false, + .has_dllon =3D false, +}; + static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps =3D { .max_speed_hz =3D SAMA7G5_QSPI0_MAX_SPEED_HZ, .has_gclk =3D true, @@ -1660,6 +1671,10 @@ static const struct of_device_id atmel_qspi_dt_ids[]= =3D { .compatible =3D "microchip,sama7g5-qspi", .data =3D &atmel_sama7g5_qspi_caps, }, + { + .compatible =3D "microchip,sam9x7-ospi", + .data =3D &atmel_sam9x7_ospi_caps, + }, =20 { /* sentinel */ } }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250902-microchip-qspi-v1-5-37af59a0406a@microchip.com> References: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> In-Reply-To: <20250902-microchip-qspi-v1-0-37af59a0406a@microchip.com> To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Nicolas Ferre" , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus CC: , , , , Dharma Balasubiramani , Varshini Rajendran X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756792344; l=1545; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=f0BEjRg0ecgW3mbWEOamZAvt1r/7v97MsNFu6rAL6n8=; b=KmbhvXvmgW8U/7xZW5mTNMEm/DMGTIOv8a+kUdEn+t0dzTGnHnQetDBdEepFTJaa0BW9OCgtp JKeFRkYi6icCnPqSnrWzbpG+No0okW9MP4ad9W2lz7+H1j32OfD7HCl X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= From: Varshini Rajendran Add support for sama7d65 QSPI controller and define its caps. Signed-off-by: Varshini Rajendran --- drivers/spi/atmel-quadspi.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 342cdd6e8d64..d7a3d85d00c2 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -1638,6 +1638,24 @@ static const struct atmel_qspi_caps atmel_sam9x7_osp= i_caps =3D { .has_dllon =3D false, }; =20 +static const struct atmel_qspi_caps atmel_sama7d65_ospi_caps =3D { + .max_speed_hz =3D SAMA7G5_QSPI0_MAX_SPEED_HZ, + .has_gclk =3D true, + .octal =3D true, + .has_dma =3D true, + .has_2xgclk =3D true, + .has_padcalib =3D true, + .has_dllon =3D false, +}; + +static const struct atmel_qspi_caps atmel_sama7d65_qspi_caps =3D { + .max_speed_hz =3D SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, + .has_gclk =3D true, + .has_dma =3D true, + .has_2xgclk =3D true, + .has_dllon =3D false, +}; + static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps =3D { .max_speed_hz =3D SAMA7G5_QSPI0_MAX_SPEED_HZ, .has_gclk =3D true, @@ -1675,6 +1693,15 @@ static const struct of_device_id atmel_qspi_dt_ids[]= =3D { .compatible =3D "microchip,sam9x7-ospi", .data =3D &atmel_sam9x7_ospi_caps, }, + { + .compatible =3D "microchip,sama7d65-ospi", + .data =3D &atmel_sama7d65_ospi_caps, + }, + { + .compatible =3D "microchip,sama7d65-qspi", + .data =3D &atmel_sama7d65_qspi_caps, + }, + =20 { /* sentinel */ } }; --=20 2.43.0