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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next 08/10] net: pcs: rzn1-miic: add per-SoC control for MIIC register unlock/lock Date: Mon, 1 Sep 2025 23:43:21 +0100 Message-ID: <20250901224327.3429099-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250901224327.3429099-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250901224327.3429099-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Make MIIC accessory register unlock/lock behaviour selectable via SoC/OF data. Add init_unlock_lock_regs and miic_write to struct miic_of_data so the driver can either perform the traditional global unlock sequence (as used on RZ/N1) or use a different policy for other SoCs (for example RZ/T2H, which does not require leaving registers unlocked). miic_reg_writel() now calls the per-SoC miic_write callback to perform register writes. Provide miic_reg_writel_unlocked() as the default writer and set it for the RZ/N1 OF data so existing platforms keep the same behaviour. Add a miic_unlock_regs() helper that implements the accessory register unlock sequence so the unlock/lock sequence can be reused where needed (for example when a SoC requires explicit unlock/lock around individual accesses). This change is preparatory work for supporting RZ/T2H. Signed-off-by: Lad Prabhakar --- drivers/net/pcs/pcs-rzn1-miic.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index d97554e203f0..86d4dccd694e 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -155,6 +155,8 @@ struct miic { * @sw_mode_mask: Switch mode mask * @reset_ids: Reset names array * @reset_count: Number of entries in the reset_ids array + * @init_unlock_lock_regs: Flag to indicate if registers need to be unlock= ed before access + * @miic_write: Function pointer to write a value to a MIIC register */ struct miic_of_data { struct modctrl_match *match_table; @@ -169,6 +171,8 @@ struct miic_of_data { u8 sw_mode_mask; const char * const *reset_ids; u8 reset_count; + bool init_unlock_lock_regs; + void (*miic_write)(struct miic *miic, int offset, u32 value); }; =20 /** @@ -190,11 +194,25 @@ static struct miic_port *phylink_pcs_to_miic_port(str= uct phylink_pcs *pcs) return container_of(pcs, struct miic_port, pcs); } =20 -static void miic_reg_writel(struct miic *miic, int offset, u32 value) +static inline void miic_unlock_regs(struct miic *miic) +{ + /* Unprotect register writes */ + writel(0x00A5, miic->base + MIIC_PRCMD); + writel(0x0001, miic->base + MIIC_PRCMD); + writel(0xFFFE, miic->base + MIIC_PRCMD); + writel(0x0001, miic->base + MIIC_PRCMD); +} + +static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 va= lue) { writel(value, miic->base + offset); } =20 +static void miic_reg_writel(struct miic *miic, int offset, u32 value) +{ + miic->of_data->miic_write(miic, offset, value); +} + static u32 miic_reg_readl(struct miic *miic, int offset) { return readl(miic->base + offset); @@ -421,10 +439,8 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mod= e) * is going to be used in conjunction with the Cortex-M3, this sequence * will have to be moved in register write */ - miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); - miic_reg_writel(miic, MIIC_PRCMD, 0x0001); - miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); - miic_reg_writel(miic, MIIC_PRCMD, 0x0001); + if (miic->of_data->init_unlock_lock_regs) + miic_unlock_regs(miic); =20 miic_reg_writel(miic, MIIC_MODCTRL, ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); @@ -625,6 +641,8 @@ static struct miic_of_data rzn1_miic_of_data =3D { .miic_port_start =3D 1, .miic_port_max =3D 5, .sw_mode_mask =3D GENMASK(4, 0), + .init_unlock_lock_regs =3D true, + .miic_write =3D miic_reg_writel_unlocked, }; =20 static const struct of_device_id miic_of_mtable[] =3D { --=20 2.51.0