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Shenoy" , Babu Moger , Suravee Suthikulpanit , K Prateek Nayak , , "Naveen N Rao" Subject: [PATCH v5 1/4] x86/cpu/topology: Always try cpu_parse_topology_ext() on AMD/Hygon Date: Mon, 1 Sep 2025 17:04:15 +0000 Message-ID: <20250901170418.4314-2-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250901170418.4314-1-kprateek.nayak@amd.com> References: <20250901170418.4314-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|CH3PR12MB9394:EE_ X-MS-Office365-Filtering-Correlation-Id: 73624e75-417e-474e-2497-08dde979bc88 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014|7416014|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Ng9vRDmxlz2f7rzqOm1AW+LxxuiTtgBD1g5moywXeiTneHA8anmMZRM3j2oQ?= =?us-ascii?Q?BisVnJ5ThYPnFpYYLHGU/0OKFqeDJMAegwcI49VJsvPLWPjAm3ueDe/wxl9p?= =?us-ascii?Q?R6g8Mo9wknkrPVVcblPFSD11JjkU3AgbC2KCgf3c2KyNCV2x1lJNf4kki1x1?= =?us-ascii?Q?x1NFF0cz5r+2StE6Pzt9hmbgjVDoxHEWfFaq/c/dyBN4TQOLf+YhU6fEUnXf?= =?us-ascii?Q?hdtTVW8dQxgyuFj0FhHSn3KqNfHxQq9WVcFc2l5DM0pFoueesvCvAtfBDGwa?= =?us-ascii?Q?g/bRp8ybPw+M2c04uK3gw5dp37MaoMtGZdARLPImY2eFRswCkyJbFoQ+PawY?= =?us-ascii?Q?X9pzY6rRXEl7uNHCQPdkdmIBhG6unRe4f++irLr+bQ04hCH5J2lN9YoTGwKg?= =?us-ascii?Q?7pcwDCZqpVT5ABWfo5LEK4Y5OZpOuuq3UiaESvXHC0vrfRJTTAty8M9sR2xE?= =?us-ascii?Q?VDifW1iH+34FFTWbmyjQRSAgOvTBsGbt5HJghiO22afbnvf51KoiX0mdp7RC?= =?us-ascii?Q?VVyj9SkgzDyTOzRgPzvPcBgwlXAv5eMduvGg1VVCAhRsqcZfNlhoWijyb5c2?= =?us-ascii?Q?dl1WAZqV48ryfyDJA6ZtphwDIKGErvHBrmKEaltV4lwPyElFh+Pi7RdBq1/7?= =?us-ascii?Q?PiHo6aQU0c3NQ1KtSHsT9eBq5+0lngC1QC9RD2H7foj/1UgmbI0+9pMhY0iz?= =?us-ascii?Q?eXh0zfwza0K+znAVJYBrJCnCZ0ISKNw/u+qMjA/mGj8Fc/FDawsYeuHFlIQv?= =?us-ascii?Q?N1dIvVGDKYy2odUmhO1RyEGkboUItfHCcH01FEzB+1vBYAxKLisFiY/B4gO0?= =?us-ascii?Q?9ggl93FyK6eRZT0MwJeaWbmHjjFjmjkLhg5Apw1l8QEJ99r6wLqgNBFwxGw+?= =?us-ascii?Q?qbXYBZIVzMGoFBLCx9iCUwTs3Xlq+1TSktDAPYioBA5WxI/u1/mdI0rmJytZ?= =?us-ascii?Q?lugA2a2WOwu7eeQ7tGAbuLM8y5QEFAGCVJ5W6F7cXpm9UXw/c0b0+F8zPe/W?= =?us-ascii?Q?DV6AqbT9oYOxm4WgK5ySIduqY72aB/brIEvf+to9k5uNTfsH2VYAYo92ooaZ?= =?us-ascii?Q?00QxzUXRa3LN8kvmkxrEyJyelXnpKmYf5UNNUFXMabCs1p61Tr9t2/DoJ3bs?= =?us-ascii?Q?xPAFYG3N4owAXFEZf1C91T3IqtTUV5Hh9VLJWS1duTVPA9gzEkvyyegcY7S4?= =?us-ascii?Q?miC22i/T293jYGc7SsWBmUI/HWuupUPnSq/lY5liVEzu3cUMNup68DiJsnRt?= =?us-ascii?Q?0THQoMTHj5mdtCuhG0elEQkqYVsJGAFcLp9fv5aE5B7D1zafmQOVSrUgAcEp?= =?us-ascii?Q?9vXU+vZnm/tLJlr6q7CD1pR+qWqc14gx8AP2WP8DzLG1Arxp0iY5ewP3Xk/X?= =?us-ascii?Q?r5bizRVRWiX8FxP3X26PTLfju3UlOV4cJb+80eK/E4OS1OalGYQs2lCV676E?= =?us-ascii?Q?bhIWuUaJpb8cWfaU+4zuZvKNJw9981gnh1h6hftmEegc1MgggCmaQ4N4nbDy?= =?us-ascii?Q?9idDBjV5iGQwa93WHdeYvR0V5vMKzDLMLqsbUK0wCgKc/vQpwhweFMIkgA?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014)(7416014)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2025 17:05:21.9369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73624e75-417e-474e-2497-08dde979bc88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9394 Content-Type: text/plain; charset="utf-8" Support for parsing the topology on AMD/Hygon processors using CPUID leaf 0xb was added in commit 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available"). In an effort to keep all the topology parsing bits in one place, this commit also introduced a pseudo dependency on the TOPOEXT feature to parse the CPUID leaf 0xb. TOPOEXT feature (CPUID 0x80000001 ECX[22]) advertises the support for Cache Properties leaf 0x8000001d and the CPUID leaf 0x8000001e EAX for "Extended APIC ID" however support for 0xb was introduced alongside the x2APIC support not only on AMD [1], but also historically on x86 [2]. Similar to 0xb, the support for extended CPU topology leaf 0x80000026 too does not depend on the TOPOEXT feature. The support for these leaves is expected to be confirmed by ensuring "leaf <=3D {extended_}cpuid_level" and then parsing the level 0 of the respective leaf to confirm EBX[15:0] (LogProcAtThisLevel) is non-zero as stated in the definition of "CPUID_Fn0000000B_EAX_x00 [Extended Topology Enumeration] (Core::X86::Cpuid::ExtTopEnumEax0)" in Processor Programming Reference (PPR) for AMD Family 19h Model 01h Rev B1 Vol1 [3] Sec. 2.1.15.1 "CPUID Instruction Functions". This has not been a problem on baremetal platforms since support for TOPOEXT (Fam 0x15 and later) predates the support for CPUID leaf 0xb (Fam 0x17[Zen2] and later), however, for AMD guests on QEMU, "x2apic" feature can be enabled independent of the "topoext" feature where QEMU expects topology and the initial APICID to be parsed using the CPUID leaf 0xb (especially when number of cores > 255) which is populated independent of the "topoext" feature flag. Unconditionally call cpu_parse_topology_ext() on AMD and Hygon processors to first parse the topology using the XTOPOLOGY leaves (0x80000026 / 0xb) before using the TOPOEXT leaf (0x8000001e). While at it, break down the single large comment in parse_topology_amd() to better highlight the purpose of each CPUID leaf. Cc: stable@vger.kernel.org # Only v6.9 and above; Depends on x86 topology r= ewrite Link: https://lore.kernel.org/lkml/1529686927-7665-1-git-send-email-suravee= .suthikulpanit@amd.com/ [1] Link: https://lore.kernel.org/lkml/20080818181435.523309000@linux-os.sc.int= el.com/ [2] Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 [3] Suggested-by: Naveen N Rao (AMD) Fixes: 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function = 0xB when available") Signed-off-by: K Prateek Nayak --- Changelog v4..v5: o Made a note on only targeting versions >=3D v6.9 for stable backports since the fix depends on the x86 topology rewrite. (Boris) o Renamed "has_topoext" to "has_xtopology". (Boris) o Broke down the large comment in parse_topology_amd() to better highlight the purpose of each leaf and the overall parsing flow. (Boris) --- arch/x86/kernel/cpu/topology_amd.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 827dd0dbb6e9..c79ebbb639cb 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -175,27 +175,30 @@ static void topoext_fixup(struct topo_scan *tscan) =20 static void parse_topology_amd(struct topo_scan *tscan) { - bool has_topoext =3D false; - /* - * If the extended topology leaf 0x8000_001e is available - * try to get SMT, CORE, TILE, and DIE shifts from extended + * Try to get SMT, CORE, TILE, and DIE shifts from extended * CPUID leaf 0x8000_0026 on supported processors first. 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Shenoy" , Babu Moger , Suravee Suthikulpanit , K Prateek Nayak Subject: [PATCH v5 2/4] x86/cpu/topology: Check for X86_FEATURE_XTOPOLOGY instead of passing has_xtopology Date: Mon, 1 Sep 2025 17:04:16 +0000 Message-ID: <20250901170418.4314-3-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250901170418.4314-1-kprateek.nayak@amd.com> References: <20250901170418.4314-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB77:EE_|BY5PR12MB4068:EE_ X-MS-Office365-Filtering-Correlation-Id: e1089548-6d61-446d-4c0a-08dde979c9ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YvGyOp8thKuoY4UJQU6v+nalSNU4MO23kju03Y+vDzVxSSvUjFb/5TFGLqWR?= =?us-ascii?Q?gAu8wX8A7If9eniM952UEP2FG7dsbFL3jv1qNHroK6VStAGun+P3go0eMMkI?= =?us-ascii?Q?6z+RM7/UPeS9sSki95b1pR3283BJf6pn+9IAbwI5ZKMKsBMOA5LqhcDLSoTK?= =?us-ascii?Q?oamaDADhAAhQdpcA1rNCieq7v3KnVAGv4u9DAk+nPO5HDQ43c0VpqCpTVSWK?= =?us-ascii?Q?s2wmXn6j29KyYMZ3OBg7UbacxzGykPTW+UnfwYGhtTbAtBmXShi3m6gTd4Vs?= =?us-ascii?Q?6OGc0caGloSHXCBZdS+sbFFHwCVtEWZ98FlxnqoRKrLadoWcVPMzW5L7TLjY?= =?us-ascii?Q?1DUkFOoYfOmI5CvGyP+efUiochlGcKwppKGU0q8JkPp08f6RRrndaRoXFfyT?= =?us-ascii?Q?+Tc8eJi8BrjxMsO5zH/isaVBN/iiYY0uA7aL/+ybjcnbiGkANErbtlxaEa6i?= =?us-ascii?Q?5j1tgvm4tWhGGPA8AmTRUvFKgx2VeHNHw6185DR5RUObOK0WzfEIDwL8S1gH?= =?us-ascii?Q?/P9BgnNHX3H2HBF1tmH0rX07Q9ly7HbRDIvfAzklIC796yNPhFTN8NO81F8Y?= =?us-ascii?Q?R5Ld874CZlokZrVyJ91u1R+r229yS2KyiYtQwlSdw63nlF+AzW0Kyp/FZVgD?= =?us-ascii?Q?0eeAfd0bEA8WE+nS/V3yWdj2wlWZt+QHXY4Z7Zrx5T2jv2+pWV3W/yQrciht?= =?us-ascii?Q?zsFckVa6dbRRUSvIuDbdcknq2F8bEIpvY1lr3aRyVNcsXJz8eGLPKWXjcHVe?= =?us-ascii?Q?k8+QzVb/eFnKdFMBxFnOuS00Y+NI+aCN/8sdFeqApGHxDWe5X6rbLWZMboOo?= =?us-ascii?Q?WepbKqTcP1xK/6y8xMmmxXnP5kpGWk1nmrPCSXyVeY25BIVJZZpuYrP2GDCJ?= =?us-ascii?Q?USYCRfCtBVEE8wt5TSM1HuUHVO2XlnuSgzNmg1JkB18C3k9KLtzkEfYrL4Mi?= =?us-ascii?Q?IDdw3aU1lxDXc62LgA1iyQ2ZdO64t0PpJYLK3HbFEnGH12nTTq1L8VziPGXw?= =?us-ascii?Q?ZykqmTYXu4hWAE3sQeGnGlIFe4ql+dfpDDxD3fuuBMJUANO8nlbzhH8oS2/k?= =?us-ascii?Q?Ku4/SVo1kBeEvovz2keZ0Vm6QWnuJ759ZJYe+jCzom4uv4F7TdCEi8S+olyL?= =?us-ascii?Q?mgGM0IQTUN9vBw7y/zL/M+ppSuzNrnF9VjNy+hxgBKBBRgfn9atDy45wA8Dy?= =?us-ascii?Q?SoUTfaodw3TwyEKJ+QiwgYFmOoZ4yFh4FgCfK7YNRCzEA47QOqGY0Oj7/KXF?= =?us-ascii?Q?b5iX4zVY/8T8yBLuOQA0YPxxwwGbdyST665TqRDgFG6QEWH76F7TzNWFVNtS?= =?us-ascii?Q?cyyw7+EK56u/aG6ypYJ6HjpuwluHFH7WUKWaU+yDo5Mpcx83/44nLdzPqDyx?= =?us-ascii?Q?/TPIqLiVqI1OD8pjbpAFt+SiA+aj5U82jr1wZgy9935VowFYd64JYIn7ddUH?= =?us-ascii?Q?J7ZPiLxgiSuQGvmlUSoBWufDxL7wHa6TuYW1usR4SzLHh0V4oJTL8MF7SdEe?= =?us-ascii?Q?NlIql4ejhmiCuhryfRlJe++TjrgHFT8d00zT?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2025 17:05:44.0004 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1089548-6d61-446d-4c0a-08dde979c9ae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4068 Content-Type: text/plain; charset="utf-8" cpu_parse_topology_ext() sets X86_FEATURE_XTOPOLOGY before returning true if any of the XTOPOLOGY leaf (0x80000026 / 0xb) could be parsed successfully. Instead of storing and passing around this return value using "has_xtopology" in parse_topology_amd(), check for X86_FEATURE_XTOPOLOGY directly in parse_8000_001e() to simplify the flow. No functional changes intended. Signed-off-by: K Prateek Nayak --- Changelog v4..v5: o No functional changes. The diff is slightly altered as a result of modifying the comment in parse_topology_amd() in Patch 1. --- arch/x86/kernel/cpu/topology_amd.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index c79ebbb639cb..7ebd4a15c561 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -59,7 +59,7 @@ static void store_node(struct topo_scan *tscan, u16 nr_no= des, u16 node_id) tscan->amd_node_id =3D node_id; } =20 -static bool parse_8000_001e(struct topo_scan *tscan, bool has_topoext) +static bool parse_8000_001e(struct topo_scan *tscan) { struct { // eax @@ -85,7 +85,7 @@ static bool parse_8000_001e(struct topo_scan *tscan, bool= has_topoext) * If leaf 0xb/0x26 is available, then the APIC ID and the domain * shifts are set already. */ - if (!has_topoext) { + if (!cpu_feature_enabled(X86_FEATURE_XTOPOLOGY)) { tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; =20 /* @@ -175,30 +175,27 @@ static void topoext_fixup(struct topo_scan *tscan) =20 static void parse_topology_amd(struct topo_scan *tscan) { + if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) + tscan->c->topo.cpu_type =3D cpuid_ebx(0x80000026); + /* * Try to get SMT, CORE, TILE, and DIE shifts from extended * CPUID leaf 0x8000_0026 on supported processors first. If * extended CPUID leaf 0x8000_0026 is not supported, try to * get SMT and CORE shift from leaf 0xb. If either leaf is * available, cpu_parse_topology_ext() will return true. - */ - bool has_xtopology =3D cpu_parse_topology_ext(tscan); - - if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) - tscan->c->topo.cpu_type =3D cpuid_ebx(0x80000026); - - /* + * * If XTOPOLOGY leaves (0x26/0xb) are not available, try to * get the CORE shift from leaf 0x8000_0008 first. */ - if (!has_xtopology && !parse_8000_0008(tscan)) + if (!cpu_parse_topology_ext(tscan) && !parse_8000_0008(tscan)) return; =20 /* * Prefer leaf 0x8000001e if available to get the SMT shift and * the initial APIC ID if XTOPOLOGY leaves are not available. */ - if (parse_8000_001e(tscan, has_xtopology)) + if (parse_8000_001e(tscan)) return; =20 /* Try the NODEID MSR */ --=20 2.34.1 From nobody Fri Oct 3 11:26:00 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2074.outbound.protection.outlook.com [40.107.243.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D66452DF142; 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Also define and use the bits necessary for an old TOPOEXT fixup on AMD Family 0x15 processors. No functional changes intended. Signed-off-by: K Prateek Nayak --- Changelog v4..v5: o No changes. --- arch/x86/include/asm/msr-index.h | 5 +++++ arch/x86/kernel/cpu/topology_amd.c | 7 ++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index f627196eb796..176ca7040139 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -633,6 +633,11 @@ #define MSR_AMD_PPIN 0xc00102f1 #define MSR_AMD64_CPUID_FN_7 0xc0011002 #define MSR_AMD64_CPUID_FN_1 0xc0011004 + +#define MSR_AMD64_CPUID_FN_EXT 0xc0011005 +#define MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED_BIT 54 +#define MSR_AMD64_CPUID_FN_EXT_TOPOEXT_ENABLED BIT_ULL(MSR_AMD64_CPUID_FN= _EXT_TOPOEXT_ENABLED_BIT) + #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 #define MSR_AMD64_TW_CFG 0xc0011023 diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 7ebd4a15c561..07510647a378 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -163,11 +163,12 @@ static void topoext_fixup(struct topo_scan *tscan) c->x86 !=3D 0x15 || c->x86_model < 0x10 || c->x86_model > 0x6f) return; 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Mon, 1 Sep 2025 10:06:19 -0700 From: K Prateek Nayak To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Sean Christopherson , Paolo Bonzini , Jonathan Corbet , CC: Naveen rao , Sairaj Kodilkar , "H. Peter Anvin" , "Peter Zijlstra (Intel)" , "Xin Li (Intel)" , Pawan Gupta , , , Mario Limonciello , "Gautham R. Shenoy" , Babu Moger , Suravee Suthikulpanit , K Prateek Nayak Subject: [RFC PATCH v5 4/4] Documentation/x86/topology: Detail CPUID leaves used for topology enumeration Date: Mon, 1 Sep 2025 17:04:18 +0000 Message-ID: <20250901170418.4314-5-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250901170418.4314-1-kprateek.nayak@amd.com> References: <20250901170418.4314-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F9:EE_|IA1PR12MB6211:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c1235a8-6e98-4e50-c0ad-08dde979e431 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?A1MCHn5vQlLJ3oZNRYgRc9ypw0f2VZDe0jzv5xQSWijxdpUjxccE5JK8nCTH?= =?us-ascii?Q?dz41fTxpn9L5ncwRkso4Hye93UOAVicB9FRMT6ELJ0R6nnZKwmgrzGppM17w?= =?us-ascii?Q?4LDSXookY8QpRNGyL9rbxO/SN1+zeAoeg9HcKSWi0ROlvdld/nNI92uoaj7c?= =?us-ascii?Q?+UoV6LtpXinyRc1aLx6JISbHytSjkP6KBXKAK2YdxmdcG9XLThbtvOynEZZR?= =?us-ascii?Q?0suzMGfkHl3uK5VfYlwlcqF5xwdAdK4EnhMeq5HZTXvCiaMiWWs0c0d7j9ek?= =?us-ascii?Q?1bGR2D2fSGTC4I76KQ5SJ6AlYXZwe5es22H3nHWYWBt0Js8+TUxHRkN6pYJX?= =?us-ascii?Q?BZpd4q4Mo7+gfN3I3+AFglCuqTANyYYCrRwbmFHn8zqQinOpLaBktXlxqPpz?= =?us-ascii?Q?oyZ82GADhqklZ774j8EB6hE2mU0Hi7kR/MIqLWn1D2h3nAbnR3cPZlrLxpNs?= =?us-ascii?Q?y70a+1W6dTNQ39vyZWkog0zIh1WspejWk6m2QJlddW945IVSRAOKNW90kVtV?= =?us-ascii?Q?OPuVtZM7wb1R9IIhYA13e5FEgY/WbWEx+7ELgGrnFzjR3Ws+wpqEu/MrSgpl?= =?us-ascii?Q?rX5MV4aEtsv+f4msC1MjaDXCuRcKbpvLon+RXXkeiXZaBTQkgVss+AUUb2YP?= =?us-ascii?Q?0dlzFMKTIx4dQUwS83Ua/eU88yxNngpkrdfYBw5MbJYt56vk3Sd7jutOvzQ4?= =?us-ascii?Q?0yz9E6pAenKQBvrXyyh94jOkgWw7FvAnxaqWfYFOdC24flf0kZA48Bgn+7r8?= =?us-ascii?Q?U7N5uqoJk+h/E+hNf9YXyQWpuCDw2/nmiWCrwf9IDtkmE2EpHVy/my2u9bgi?= =?us-ascii?Q?QONfsGWaDbeYbXJt0aJuBfAEIKOUwngCkDOTpe9SFhci9h7UZrazAAIy8pUD?= =?us-ascii?Q?x28PzOSnMoZrY+/DO6P8SfbO4g3C6sj3YhsrDySXLIuuxAyDCLbcJ9Zox8/2?= =?us-ascii?Q?bSOjahBexpTWYIZJ9tj+ZchkuugSyQqCJyNCoPBpFnY6yCTPVoqXT5rfEK1D?= =?us-ascii?Q?WwygXSAjn16iXuTnyxeGAdT1X7drhTkAUKpFA0tA8g0qWX+6LTIfaW1GWPUh?= =?us-ascii?Q?nRe3LwMhMv/84BaWORznVqKrbdWLBvAc31hCYy9iCcHfKrc6DQ28ZcqLbTNx?= =?us-ascii?Q?D3wq0QWVaPrhsnzQy7ssr8MMumBtKzjfIVzHypFE1mp9BlKH9WwQO4h6LTxd?= =?us-ascii?Q?ZAWcLC0unHpiLNBJPNMMkMcinenabbhViC0KFNiHjM737mt1bAT+hW7lraG3?= =?us-ascii?Q?PMxZIzbblVvBv3KIXYASLQEY3IDrXsxEXhwycx+pJRIAg7vK4tmJsYisMtfV?= =?us-ascii?Q?FcX7YQjrMQNowpCGZuL0eRawacG67IJ9PUFbDm5BMKuRHJV/LTj0nKjOiAaX?= =?us-ascii?Q?dHTtrJ/hQssqrI/BFJdXPgb/7kcKEtucxQs6lHJgR1wIpDbZDZquobIWs1Mn?= =?us-ascii?Q?szlg+rAPXCeMgtYMrLJ3eWcW+1utQrrpOLRxJcY8//2YhOMb6c4z9FSQ5Nx1?= =?us-ascii?Q?cyqYCz5tu1/GbEYJ3CbBADHPjO4I3bSAP+73?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2025 17:06:28.3915 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c1235a8-6e98-4e50-c0ad-08dde979e431 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6211 Content-Type: text/plain; charset="utf-8" Add a new section describing the different CPUID leaves and fields used to parse topology on x86 systems. Suggested-by: Borislav Petkov Signed-off-by: K Prateek Nayak --- Changelog v4..v5: o Added a nte about the NODE_ID_MSR on AMD platforms. --- Documentation/arch/x86/topology.rst | 198 ++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/Documentation/arch/x86/topology.rst b/Documentation/arch/x86/t= opology.rst index c12837e61bda..4227eba65957 100644 --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -141,6 +141,204 @@ Thread-related topology information in the kernel: =20 =20 =20 +System topology enumeration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D +The topology on x86 systems can be discovered using a combination of vendor +specific CPUID leaves introduced specifically to enumerate the processor +topology and the cache hierarchy. + +The CPUID leaves in their preferred order of parsing for each x86 vendor i= s as +follows: + +1) AMD and Hygon + + On AMD and Hygon platforms, the CPUID leaves that enumerate the process= or + topology are as follows: + + 1) CPUID leaf 0x80000026 [Extended CPU Topology] (Core::X86::Cpuid::ExC= puTopology) + + The extended CPUID leaf 0x80000026 is the extension of the CPUID lea= f 0xB + and provides the topology information of Core, Complex, CCD(Die), and + Socket in each level. + + The support for the leaf is expected to be discovered by checking if= the + supported extended CPUID level is >=3D 0x80000026 and then checking = if + `LogProcAtThisLevel` in `EBX[15:0]` at a particular level (starting = from + 0) is non-zero. + + The `LevelType` in `ECX[15:8]` at the level provides the detail of t= he + topology domain that the level describes - Core, Complex, CCD(Die), = or + the Socket. + + The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the + number of bits that need to be right shifted from the + `ExtendedLocalApicId` in `EDX[31:0]` to get a unique Topology ID for + the topology level. CPUs with the same Topology ID share the resourc= es + at that level. + + CPUID leaf 0x80000026 also provides more information regarding the + power and efficiency rankings, and about the core type on AMD + processors with heterogeneous characteristics. + + If CPUID leaf 0x80000026 is supported, further parsing is not requir= ed. + + + 2) CPUID leaf 0x0000000B [Extended Topology Enumeration] (Core::X86::Cp= uid::ExtTopEnum) + + The extended CPUID leaf 0x0000000B is the predecessor on the extended + CPUID leaf 0x80000026 and only describes the core, and the socket do= mains + of the processor topology. + + The support for the leaf is expected to be discovered by checking if= the + supported CPUID level is >=3D 0xB and then checking if `EBX[31:0]` a= t a + particular level (starting from 0) is non-zero. + + The `LevelType` in `ECX[15:8]` at the level provides the detail of t= he + topology domain that the level describes - Thread, or Processor (Soc= ket). + + The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the + number of bits that need to be right shifted from the + `ExtendedLocalApicId` in `EDX[31:0]` to get a unique Topology ID for + that topology level. CPUs sharing the Topology ID share the resources + at that level. + + If CPUID leaf 0xB is supported, further parsing is not required. + + + 3) CPUID leaf 0x80000008 ECX [Size Identifiers] (Core::X86::Cpuid::Size= Id) + + If neither the CPUID leaf 0x80000026 or CPUID leaf 0xB is supported,= the + number of CPUs on the package is detected using the Size Identifier = leaf + 0x80000008 ECX. + + The support for the leaf is expected to be discovered by checking if= the + supported extended CPUID level is >=3D 0x80000008. + + The shifts from the APIC ID for the Socket ID is calculated from the + `ApicIdSize` field in `ECX[15:12]` if it is non-zero. + + If `ApicIdSize` is reported to be zero, the shift is calculated as t= he + order of the `number of threads` calculated from `NC` field in + `ECX[7:0]` which describes the `number of threads - 1` on the packag= e. + + Unless Extended APIC ID is supported, the APIC ID used to find the + Socket ID is from the `LocalApicId` field of CPUID leaf 0x00000001 + `EBX[31:24]`. + + The topology parsing continues to detect if Extended APIC ID is + supported or not. + + + 4) CPUID leaf 0x8000001E [Extended APIC ID, Core Identifiers, Node Iden= tifiers] + (Core::X86::Cpuid::{ExtApicId,CoreId,NodeId}) + + The support for Extended APIC ID can be detected by checking for the + presence of `TopologyExtensions` in `ECX[22]` of CPUID leaf 0x800000= 01 + [Feature Identifiers] (Core::X86::Cpuid::FeatureExtIdEcx). + + If Topology Extensions is supported, the APIC ID from `ExtendedApicI= d` + from CPUID leaf 0x8000001E `EAX[31:0]` should be preferred over that= from + `LocalApicId` field of CPUID leaf 0x00000001 `EBX[31:24]` for topolo= gy + enumeration. + + On processors of Family 0x17 and above that do not support CPUID leaf + 0x80000026 or CPUID leaf 0xB, the shifts from the APIC ID for the Co= re + ID is calculated using the order of `number of threads per core` + calculated using the `ThreadsPerCore` field in `EBX[15:8]` which + describes `number of threads per core - 1`. + + On Processors of Family 0x15, the Core ID from `EBX[7:0]` is used as= the + `cu_id` (Compute Unit ID) to detect CPUs that share the compute unit= s. + + + All AMD and Hygon processors that support the `TopologyExtensions` feat= ure + stores the `NodeId` from the `ECX[7:0]` of CPUID leaf 0x8000001E + (Core::X86::Cpuid::NodeId) as the per-CPU `node_id`. On older processor= s, + the `node_id` was discovered using MSR_FAM10H_NODE_ID MSR (MSR + 0x0xc001_100c). The presence of the NODE_ID MSR was detected by checking + `ECX[19]` of CPUID leaf 0x80000001 [Feature Identifiers] + (Core::X86::Cpuid::FeatureExtIdEcx). + + +2) Intel + + On Intel platforms, the CPUID leaves that enumerate the processor + topology are as follows: + + 1) CPUID leaf 0x1F (V2 Extended Topology Enumeration Leaf) + + The CPUID leaf 0x1F is the extension of the CPUID leaf 0xB and provi= des + the topology information of Core, Module, Tile, Die, DieGrp, and Soc= ket + in each level. + + The support for the leaf is expected to be discovered by checking if + the supported CPUID level is >=3D 0x1F and then `EBX[31:0]` at a + particular level (starting from 0) is non-zero. + + The `Domain Type` in `ECX[15:8]` of the sub-leaf provides the detail= of + the topology domain that the level describes - Core, Module, Tile, D= ie, + DieGrp, and Socket. + + The kernel uses the value from `EAX[4:0]` to discover the number of + bits that need to be right shifted from the `x2APIC ID` in `EDX[31:0= ]` + to get a unique Topology ID for the topology level. CPUs with the sa= me + Topology ID share the resources at that level. + + If CPUID leaf 0x1F is supported, further parsing is not required. + + + 2) CPUID leaf 0x0000000B (Extended Topology Enumeration Leaf) + + The extended CPUID leaf 0x0000000B is the predecessor of the V2 Exte= nded + Topology Enumeration Leaf 0x1F and only describes the core, and the + socket domains of the processor topology. + + The support for the leaf is expected to be discovered by checking if= the + supported CPUID level is >=3D 0xB and then checking if `EBX[31:0]` a= t a + particular level (starting from 0) is non-zero. + + CPUID leaf 0x0000000B shares the same layout as CPUID leaf 0x1F and + should be enumerated in a similar manner. + + If CPUID leaf 0xB is supported, further parsing is not required. + + + 3) CPUID leaf 0x00000004 (Deterministic Cache Parameters Leaf) + + On Intel processors that support neither CPUID leaf 0x1F, nor CPUID = leaf + 0xB, the shifts for the SMT domains is calculated using the number of + CPUs sharing the L1 cache. + + Processors that feature Hyper-Threading is detected using `EDX[28]` = of + CPUID leaf 0x1 (Basic CPUID Information). + + The order of `Maximum number of addressable IDs for logical processo= rs + sharing this cache` from `EAX[25:14]` of level-0 of CPUID 0x4 provid= es + the shifts from the APIC ID required to compute the Core ID. + + The APIC ID and Package information is computed using the data from + CPUID leaf 0x1. + + + 4) CPUID leaf 0x00000001 (Basic CPUID Information) + + The mask and shifts to derive the Physical Package (socket) ID is + computed using the `Maximum number of addressable IDs for logical + processors in this physical package` from `EBX[23:16]` of CPUID leaf + 0x1. + + The APIC ID on the legacy platforms is derived from the `Initial APIC + ID` field from `EBX[31:24]` of CPUID leaf 0x1. + + +3) Centaur and Zhaoxin + + Similar to Intel, Centaur and Zhaoxin use a combination of CPUID leaf + 0x00000004 (Deterministic Cache Parameters Leaf) and CPUID leaf 0x00000= 001 + (Basic CPUID Information) to derive the topology information. + + + System topology examples =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 --=20 2.34.1