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Mon, 01 Sep 2025 06:24:34 -0700 (PDT) From: Tomer Maimon To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon Subject: [PATCH RESEND v2 2/2] arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845 Date: Mon, 1 Sep 2025 16:24:26 +0300 Message-Id: <20250901132426.3081648-3-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901132426.3081648-1-tmaimon77@gmail.com> References: <20250901132426.3081648-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a 25 MHz fixed-clock node (refclk) in the NPCM845-EVB board device tree to represent the external reference clock used by the NPCM845 reset and clock controller. Update peripherals (timer0, watchdog0-2) in the NPCM845 device tree to reference this refclk directly instead of the previous clock controller output (NPCM8XX_CLK_REFCLK). Signed-off-by: Tomer Maimon --- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++---- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 6 ++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch= /arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index e4053ffefe90..ee7da5e8f95b 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -47,6 +47,7 @@ clk: rstc: reset-controller@f0801000 { reg =3D <0x0 0xf0801000 0x0 0xC4>; nuvoton,sysgcr =3D <&gcr>; #reset-cells =3D <2>; + clocks =3D <&refclk>; #clock-cells =3D <1>; }; =20 @@ -71,7 +72,7 @@ timer0: timer@8000 { compatible =3D "nuvoton,npcm845-timer"; interrupts =3D ; reg =3D <0x8000 0x1C>; - clocks =3D <&clk NPCM8XX_CLK_REFCLK>; + clocks =3D <&refclk>; clock-names =3D "refclk"; }; =20 @@ -143,7 +144,7 @@ watchdog0: watchdog@801c { interrupts =3D ; reg =3D <0x801c 0x4>; status =3D "disabled"; - clocks =3D <&clk NPCM8XX_CLK_REFCLK>; + clocks =3D <&refclk>; syscon =3D <&gcr>; }; =20 @@ -152,7 +153,7 @@ watchdog1: watchdog@901c { interrupts =3D ; reg =3D <0x901c 0x4>; status =3D "disabled"; - clocks =3D <&clk NPCM8XX_CLK_REFCLK>; + clocks =3D <&refclk>; syscon =3D <&gcr>; }; =20 @@ -161,7 +162,7 @@ watchdog2: watchdog@a01c { interrupts =3D ; reg =3D <0xa01c 0x4>; status =3D "disabled"; - clocks =3D <&clk NPCM8XX_CLK_REFCLK>; + clocks =3D <&refclk>; syscon =3D <&gcr>; }; }; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm= 64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index eeceb5b292a8..2638ee1c3846 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -19,6 +19,12 @@ chosen { memory@0 { reg =3D <0x0 0x0 0x0 0x40000000>; }; + + refclk: refclk-25mhz { + compatible =3D "fixed-clock"; + clock-frequency =3D <25000000>; + #clock-cells =3D <0>; + }; }; =20 &serial0 { --=20 2.34.1