From nobody Sun Dec 14 08:06:22 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B43A13376B8; Mon, 1 Sep 2025 12:28:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729735; cv=none; b=MpufSQTwHEJxfSDRwpEjKr9FR1pJLnELOL3/Tq2E4CrzKphoOuQvNdHURC78tP1ERsCYiCViADVe4AkW77MWeREf5BZ/wY/E31K3bb14KWCg2HJwHJbWm8OvhDI5QzzEyuBY+ETfbTdtcmOcyQHkikhnJQMXgFFHkqXm1eWGeaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729735; c=relaxed/simple; bh=AHuXy/9bn643v++FikekyjR7rOzZzAKBSXF7Oymd12Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eK4uYp7fD4nmgO8VgIsgsiXIVoGnz6V/+kvp0Fyv8UbVah3OF2V0oSn5j2yu9+Ma8fOg5cFnsTtmNeReDzkuhmU83d4mE0IDXT4olOoxsgaUX9a2IOS0wSW8evOwQ83fRUo8Gr5FA3h9d+MQ8ScEb5FuOAsYmEuYMKyJoS+3EUw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=yEYf4Gu5; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="yEYf4Gu5" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 581CSmFN2369163; Mon, 1 Sep 2025 07:28:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756729728; bh=Kn7DKCsCS2OB/QdeXfV3m9IgHXEdPCeFN7iaFb5kKUY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yEYf4Gu5AW64jonL5aXlI7ByVrPNFu7DkZVQaNvybH6eGB2xZJ66S3Fa/gRtTu4lK u3RZZ7rYvXGMtxboyxHTS9DxPkhQblxV58wk49CQ/TGEObnymp5N3qu0yQ1tabKNrR /T+1Bv7FFc4r7rwKyWMeBbHUJXJEzplQ+u06Du/w= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 581CSmiE2721492 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 1 Sep 2025 07:28:48 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 1 Sep 2025 07:28:48 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 1 Sep 2025 07:28:48 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 581CSc7r2504775; Mon, 1 Sep 2025 07:28:44 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v2 1/3] arm64: dts: ti: k3-am62p5-sk: Remove the unused config from USB1_DRVVBUS Date: Mon, 1 Sep 2025 17:58:33 +0530 Message-ID: <20250901122835.3022850-2-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901122835.3022850-1-a-kaur@ti.com> References: <20250901122835.3022850-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requir= es that the pin corresponding to the Type-A connector remains pulled up even a= fter the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup can be selected or the pin can have the same configuration that it had when SoC was in active mode. In order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the DeepSleep state configuration from USB1_DRVBUS pin as it is anyways not taking effect (DeepSleep control bit is not set). This reverts commit 115290c112952db27009668aa7ae2f29920704f0. Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 899da7896563b..e8f0ac2c55e2f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -360,7 +360,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACL= KR.UART1_TXD */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1 From nobody Sun Dec 14 08:06:22 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 986A0338F3B; Mon, 1 Sep 2025 12:28:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729741; cv=none; b=bVV7CLCKUsp2f38GADe1symbptwlrozBOC9DgsKoWa1rW7svk6uVYS+aiJxOqnp/wNI1pNsJykDbsjOAaxWNwPbvjki08nO+41xaHFOCpizRAGFBM87OtI46sO3/0ON6szSdHppSelBqf2M4nLjT/9cw5sXI8/jpwv42eQeSCiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729741; c=relaxed/simple; bh=ROxo+6HBRTu2WhNyNfP/6zbMmPihIqMWbmoJDRa+QXg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Bj3s+sZHeyu7nYzkCwJL8Bu+0QCl55ZMPdJO6IGaJPrzAwoYqTmybQFTwmMHnQ4Hx24DbKwawYHAD8NrSs6e4pVowNo9+Fai1IstjWRUFxMctzhnK4E9eMDJ70FRWUpPOBPj0QmjWzzYpTqUS4TNWF17ClEXibaSE/DV5rjkem4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=SswIjOZ+; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SswIjOZ+" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 581CSsE62805457; Mon, 1 Sep 2025 07:28:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756729734; bh=WN+whkUQ8XqfkuukuvJSM7K0OZfjbIY1Xk7U8MUNQGM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SswIjOZ+vPoWXNa1AUtTi5wq8sXs9BJbN8Gw0lqU12UkU1+jU/9oQFxb8QtCoppRm IOQ/GfrjSpl6MNsXEpWvSbnq2qlDuRcRL/hqwcJt1QBeTS8kFvJDLwtknFMhm+0NBt ZnWeUHrFHL5mpW6EBIFYcl189AEliuWwuI+hY8fo= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 581CSsMf1538228 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 1 Sep 2025 07:28:54 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 1 Sep 2025 07:28:54 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 1 Sep 2025 07:28:54 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 581CSc7s2504775; Mon, 1 Sep 2025 07:28:50 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v2 2/3] arm64: dts: ti: k3-am62x-sk-common: Remove the unused config from USB1_DRVVBUS Date: Mon, 1 Sep 2025 17:58:34 +0530 Message-ID: <20250901122835.3022850-3-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901122835.3022850-1-a-kaur@ti.com> References: <20250901122835.3022850-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup can be selected or the pin can have the same configuration that it had when SoC was in active mode. In order for DeepSleep configuration to take effect, the DeepSleep control bit has to be enabled. Remove the DeepSleep state configuration from USB1_DRVBUS pin as it is anyways not taking effect (DeepSleep control bit is not set). This reverts commit 527f884d2d94981016e181dcbd4c4b5bf597c0ad. Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d51..d3bed23134ca0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -249,7 +249,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_= TX_CTL */ =20 main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins =3D < - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; =20 --=20 2.34.1 From nobody Sun Dec 14 08:06:22 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D19CD33A012; Mon, 1 Sep 2025 12:29:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729748; cv=none; b=Ia2/j/jWPt+6rPikNnG7/M7+4EbBNgNfvFgyiEuPX6IDRxSU7K+GgbQh0Tve6YTiOE89cBbpzAJJejyHrrnadJJYVeRLKoZWTdZ6M0GMP/yc35J4Mc0jXOMeNcD7Wrr84iBQYazZnLwRx+iOUjElzdZO8pdeK1wED+0BHAgouEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729748; c=relaxed/simple; bh=cmSiKiS5EE7WRHs1BQqsvrdfNYc0p8vUf0Nj2KA4XZA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pMG5T09JrPr+hXj128kHbM4Ygg5i3TYMpK7CH0qIKyiQYU9GOhgExxHZ6RN87r4bpnVbotTg5aEQDkC3gz3cazoqTr/8sdD3RYSwApaiiN93NYFDiwzXnI/QsAziDVX51r13cDlBdB2SSucCuXqU4KJ5moYp+DR7ehpfjbXaJAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=f4FvVwhB; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="f4FvVwhB" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 581CT1iG2369183; Mon, 1 Sep 2025 07:29:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756729741; bh=wVHBx19iLTQy7v40qomYm/I4NT1A84lCMrZzoEXUF/I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f4FvVwhBapk3J+Dqdf4qb6W6M7KFWCoOriZ6oqFPry4GwrxCYW/wzHUoWc4a0VuHY f7qzPBWAbmM5XVKVap0U3QuQnDK9R8o0pGfnCryjdLYOubUDvPLASdj5xrFq+YHI40 TqcCv5sy74FqgiZjOjQwyBUhEyNjslPHdbqqqrxI= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 581CT0d42721597 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 1 Sep 2025 07:29:01 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 1 Sep 2025 07:29:00 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 1 Sep 2025 07:29:00 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 581CSc7t2504775; Mon, 1 Sep 2025 07:28:56 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , CC: , Subject: [PATCH v2 3/3] arm64: dts: ti: k3-pinctrl: Add the remaining macros Date: Mon, 1 Sep 2025 17:58:35 +0530 Message-ID: <20250901122835.3022850-4-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901122835.3022850-1-a-kaur@ti.com> References: <20250901122835.3022850-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add the drive stregth, schmitt trigger enable macros to pinctrl file. Add the missing macros for DeepSleep configuration control referenced from "Table 14-6172. Description Of The Pad Configuration Register Bits" in AM625 TRM[0]. Add some DeepSleep macros to provide combinations that can be used directly in device tree files example PIN_DS_OUTPUT_LOW that configures pin to be output and also sets its value to 0. [0] https://www.ti.com/lit/ug/spruiv7b/spruiv7b.pdf Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 55 +++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index c0f09be8d3f94..ad53880b0dda0 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -3,15 +3,20 @@ * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti= .com/ + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti= .com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H =20 +#define WKUP_LVL_EN_SHIFT (7) +#define WKUP_LVL_POL_SHIFT (8) #define ST_EN_SHIFT (14) #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DRV_STR_SHIFT (19) +#define DS_ISO_OVERRIDE_EN_SHIFT(22) +#define DS_ISO_BYPASS_EN_SHIFT (23) #define DEBOUNCE_SHIFT (11) #define FORCE_DS_EN_SHIFT (15) #define DS_EN_SHIFT (24) @@ -19,6 +24,7 @@ #define DS_OUT_VAL_SHIFT (26) #define DS_PULLUD_EN_SHIFT (27) #define DS_PULLTYPE_SEL_SHIFT (28) +#define WKUP_EN_SHIFT (29) =20 /* Schmitt trigger configuration */ #define ST_DISABLE (0 << ST_EN_SHIFT) @@ -33,6 +39,26 @@ #define INPUT_EN (1 << RXACTIVE_SHIFT) #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) =20 +#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) + +#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENAB= LE) +#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) + +#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT) +#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT) + +#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) + +#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) +#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) +#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) +#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) +#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) + +#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) + /* Only these macros are expected be used directly in device tree files */ #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) @@ -53,18 +79,41 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) =20 +#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) + +#define PIN_SCHMITT_TRIGGER_DISABLE (0 << ST_EN_SHIFT) +#define PIN_SCHMITT_TRIGGER_ENABLE (1 << ST_EN_SHIFT) + #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) #define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) #define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT) -#define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) -#define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) +#define PIN_DS_OUT_ENABLE DS_INPUT_DISABLE +#define PIN_DS_OUT_DISABLE DS_INPUT_EN #define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) #define PIN_DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) #define PIN_DS_PULLUD_ENABLE (0 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) #define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_ISO_BYPASS (1 << DS_ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS_DISABLE (0 << DS_ISO_BYPASS_EN_SHIFT) + +#define DS_STATE_VAL (1 << DS_EN_SHIFT) +#define ACTIVE_STATE_VAL (0 << DS_EN_SHIFT) + +#define PIN_DS_OUTPUT_LOW (DS_STATE_VAL | DS_INPUT_DISABLE |= DS_OUT_VALUE_ZERO) +#define PIN_DS_OUTPUT_HIGH (DS_STATE_VAL | DS_INPUT_DISABLE |= DS_OUT_VALUE_ONE) +#define PIN_DS_INPUT (DS_STATE_VAL | DS_INPUT_EN | DS_P= ULL_DISABLE) +#define PIN_DS_INPUT_PULLUP (DS_STATE_VAL | DS_INPUT_EN | DS_P= ULL_UP) +#define PIN_DS_INPUT_PULLDOWN (DS_STATE_VAL | DS_INPUT_EN | DS_P= ULL_DOWN) + +#define PIN_WKUP_EN_EDGE (WKUP_ENABLE | WKUP_ON_EDGE) +#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_= LEVEL_LOW) +#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP= _LEVEL_HIGH) +#define PIN_WKUP_EN WKUP_EN_EDGE =20 /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) --=20 2.34.1