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Mon, 01 Sep 2025 04:41:53 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-249066e042asm103147055ad.146.2025.09.01.04.41.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 01 Sep 2025 04:41:53 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com, Xu Lu Subject: [PATCH RESEND 1/2] riscv: mm: Apply svinval in update_mmu_cache() Date: Mon, 1 Sep 2025 19:41:40 +0800 Message-Id: <20250901114141.5438-2-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250901114141.5438-1-luxu.kernel@bytedance.com> References: <20250901114141.5438-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only flush tlb of the specified mm, and apply svinval if available. Signed-off-by: Xu Lu --- arch/riscv/include/asm/pgtable.h | 16 +++++++++++++++- arch/riscv/include/asm/tlbflush.h | 23 +++++++++++++++++++++++ arch/riscv/mm/tlbflush.c | 23 ----------------------- 3 files changed, 38 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 91697fbf1f901..165cd02d51629 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -495,9 +495,15 @@ static inline void update_mmu_cache_range(struct vm_fa= ult *vmf, struct vm_area_struct *vma, unsigned long address, pte_t *ptep, unsigned int nr) { + int i; + unsigned long asid =3D get_mm_asid(vma->vm_mm); + asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) : : : : svvptc); =20 + asm goto(ALTERNATIVE("nop", "j %l[svinval]", 0, RISCV_ISA_EXT_SVINVAL, 1) + : : : : svinval); + /* * The kernel assumes that TLBs don't cache invalid entries, but * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a @@ -506,7 +512,15 @@ static inline void update_mmu_cache_range(struct vm_fa= ult *vmf, * the extra traps reduce performance. So, eagerly SFENCE.VMA. */ while (nr--) - local_flush_tlb_page(address + nr * PAGE_SIZE); + local_flush_tlb_page_asid(address + nr * PAGE_SIZE, asid); + return; + +svinval: + local_sfence_w_inval(); + for (i =3D 0; i < nr; i++) + local_sinval_vma(address + nr * PAGE_SIZE, asid); + local_sfence_inval_ir(); + return; =20 svvptc:; /* diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlb= flush.h index eed0abc405143..9636d07fe9eed 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -15,6 +15,29 @@ #define FLUSH_TLB_NO_ASID ((unsigned long)-1) =20 #ifdef CONFIG_MMU +static inline unsigned long get_mm_asid(struct mm_struct *mm) +{ + return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_A= SID; +} + +static inline void local_sfence_inval_ir(void) +{ + asm volatile(SFENCE_INVAL_IR() ::: "memory"); +} + +static inline void local_sfence_w_inval(void) +{ + asm volatile(SFENCE_W_INVAL() ::: "memory"); +} + +static inline void local_sinval_vma(unsigned long vma, unsigned long asid) +{ + if (asid !=3D FLUSH_TLB_NO_ASID) + asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); + else + asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); +} + static inline void local_flush_tlb_all(void) { __asm__ __volatile__ ("sfence.vma" : : : "memory"); diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 8404530ec00f9..962db300a1665 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -11,24 +11,6 @@ =20 #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) =20 -static inline void local_sfence_inval_ir(void) -{ - asm volatile(SFENCE_INVAL_IR() ::: "memory"); -} - -static inline void local_sfence_w_inval(void) -{ - asm volatile(SFENCE_W_INVAL() ::: "memory"); -} - -static inline void local_sinval_vma(unsigned long vma, unsigned long asid) -{ - if (asid !=3D FLUSH_TLB_NO_ASID) - asm volatile(SINVAL_VMA(%0, %1) : : "r" (vma), "r" (asid) : "memory"); - else - asm volatile(SINVAL_VMA(%0, zero) : : "r" (vma) : "memory"); -} - /* * Flush entire TLB if number of entries to be flushed is greater * than the threshold below. @@ -110,11 +92,6 @@ static void __ipi_flush_tlb_range_asid(void *info) local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); 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Mon, 01 Sep 2025 04:41:57 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-249066e042asm103147055ad.146.2025.09.01.04.41.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 01 Sep 2025 04:41:57 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com, Xu Lu Subject: [PATCH RESEND 2/2] riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid Date: Mon, 1 Sep 2025 19:41:41 +0800 Message-Id: <20250901114141.5438-3-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250901114141.5438-1-luxu.kernel@bytedance.com> References: <20250901114141.5438-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Clear corresponding bit of current cpu in mm_cpumask after executing local_flush_tlb_all_asid(). This reduces the number of IPI due to tlb flush: * ltp - mmapstress01 Before: ~98k After: 268 Signed-off-by: Xu Lu --- arch/riscv/mm/tlbflush.c | 41 ++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 962db300a1665..571358f385879 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -17,7 +17,8 @@ */ unsigned long tlb_flush_all_threshold __read_mostly =3D 64; =20 -static void local_flush_tlb_range_threshold_asid(unsigned long start, +static void local_flush_tlb_range_threshold_asid(struct mm_struct *mm, + unsigned long start, unsigned long size, unsigned long stride, unsigned long asid) @@ -27,6 +28,8 @@ static void local_flush_tlb_range_threshold_asid(unsigned= long start, =20 if (nr_ptes_in_range > tlb_flush_all_threshold) { local_flush_tlb_all_asid(asid); + if (mm && mm !=3D current->active_mm) + cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(mm)); return; } =20 @@ -46,21 +49,28 @@ static void local_flush_tlb_range_threshold_asid(unsign= ed long start, } } =20 -static inline void local_flush_tlb_range_asid(unsigned long start, - unsigned long size, unsigned long stride, unsigned long asid) +static inline void local_flush_tlb_range_mm(struct mm_struct *mm, + unsigned long start, + unsigned long size, + unsigned long stride) { - if (size <=3D stride) + unsigned long asid =3D get_mm_asid(mm); + + if (size <=3D stride) { local_flush_tlb_page_asid(start, asid); - else if (size =3D=3D FLUSH_TLB_MAX_SIZE) + } else if (size =3D=3D FLUSH_TLB_MAX_SIZE) { local_flush_tlb_all_asid(asid); - else - local_flush_tlb_range_threshold_asid(start, size, stride, asid); + if (mm && mm !=3D current->active_mm) + cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(mm)); + } else { + local_flush_tlb_range_threshold_asid(mm, start, size, stride, asid); + } } =20 /* Flush a range of kernel pages without broadcasting */ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { - local_flush_tlb_range_asid(start, end - start, PAGE_SIZE, FLUSH_TLB_NO_AS= ID); + local_flush_tlb_range_mm(NULL, start, end - start, PAGE_SIZE); } =20 static void __ipi_flush_tlb_all(void *info) @@ -79,17 +89,17 @@ void flush_tlb_all(void) } =20 struct flush_tlb_range_data { - unsigned long asid; + struct mm_struct *mm; unsigned long start; unsigned long size; unsigned long stride; }; =20 -static void __ipi_flush_tlb_range_asid(void *info) +static void __ipi_flush_tlb_range_mm(void *info) { struct flush_tlb_range_data *d =3D info; =20 - local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); + local_flush_tlb_range_mm(d->mm, d->start, d->size, d->stride); } =20 static void __flush_tlb_range(struct mm_struct *mm, @@ -97,7 +107,6 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long size, unsigned long stride) { - unsigned long asid =3D get_mm_asid(mm); unsigned int cpu; =20 if (cpumask_empty(cmask)) @@ -107,17 +116,17 @@ static void __flush_tlb_range(struct mm_struct *mm, =20 /* Check if the TLB flush needs to be sent to other CPUs. */ if (cpumask_any_but(cmask, cpu) >=3D nr_cpu_ids) { - local_flush_tlb_range_asid(start, size, stride, asid); + local_flush_tlb_range_mm(mm, start, size, stride); } else if (riscv_use_sbi_for_rfence()) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); + sbi_remote_sfence_vma_asid(cmask, start, size, get_mm_asid(mm)); } else { struct flush_tlb_range_data ftd; =20 - ftd.asid =3D asid; + ftd.mm =3D mm; ftd.start =3D start; ftd.size =3D size; ftd.stride =3D stride; - on_each_cpu_mask(cmask, __ipi_flush_tlb_range_asid, &ftd, 1); + on_each_cpu_mask(cmask, __ipi_flush_tlb_range_mm, &ftd, 1); } =20 put_cpu(); --=20 2.20.1