From nobody Fri Oct 3 12:13:09 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3899130AD02; Mon, 1 Sep 2025 10:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756721755; cv=none; b=pZg5owsokNQTN8iKn91sjYGpilu+zi9ZwzkP+hIwYHPzvz7hbfvF3XrjGdC+9AiqErlsPv2g4I4QwoS054cY4lUE7Zf4FX2/8tye/BF6Fqszn9x3ewz7ffVjItou4eDn3aIPMwB07v62gJGVwQGzRkFhHhnx28jVkEXHni5H4Gg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756721755; c=relaxed/simple; bh=zIcrzw6TL6zyle5IVpzx7t1ozRLs4iTla+xQD7hMd8U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m3AoTxoEmVkrAjfYrKa/5+chdI+Opz2yo7qisGjFCx2zkLkaq79IUPww42Jrg3MZJGVqOw5Rq3693E8wjnIMugXWiQuU1WA0LUTtWCq9wMF+7EJrnf5K1619Pc3RtSkYR1iiaO1F1DsmEIu8MlhAlIVhYt6JMSz66RVKLuYuqn4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=D89SC8OH; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="D89SC8OH" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 581AFWuo2350247; Mon, 1 Sep 2025 05:15:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756721732; bh=FGm2vmsIh7BDsFYc7DX3BbZlQOoHSUGuJH2eHrg5Nd8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=D89SC8OH/z4uxUV/Gxmer9f+0V8qaQ9kE0V3WMx4xpCXyLTnOuatZ2cjpk4jME5OE VcU8Rfvivaw+mJ653kFixSZFqhVzsubr/g2apAdoXZ5kgtN01y8e05h4BGgHA/+xUO 4yTYDcPV+IdR1fsikvPiNXMchtG22ywMlB8hSmas= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 581AFWDu1475714 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 1 Sep 2025 05:15:32 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 1 Sep 2025 05:15:32 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 1 Sep 2025 05:15:32 -0500 Received: from a-dutta.dhcp.ti.com (a-dutta.dhcp.ti.com [10.24.68.237]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 581AFPrZ2047319; Mon, 1 Sep 2025 05:15:29 -0500 From: Anurag Dutta To: , , , , CC: , , , Subject: [PATCH v2 1/2] bus: ti-sysc: Add DRA7 SoC matching Date: Mon, 1 Sep 2025 15:45:24 +0530 Message-ID: <20250901101525.1090334-2-a-dutta@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901101525.1090334-1-a-dutta@ti.com> References: <20250901101525.1090334-1-a-dutta@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Sinthu Raja Kernel Commit 25de4ce5ed02 ("clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940") states that "There is a timer wrap issue on dra7 and as a work around, we need to use timer-ti-dm percpu timers instead. So, configure dmtimer3 and 4 as percpu timers by default." In this commit, the author has used ti,no-reset-on-init and ti,no-idle quirks. The sysc_check_active_timer() checks for these quirks and accordingly, returns EBUSY error if the quirks match. Because of this, the timer modules fail to probe as can be observed during bootup :"ti-sysc 4882c000.target-module: probe with driver ti-sysc failed with error -16" Return 'ENXIO' instead of 'EBUSY' for DRA7 SoC, so that the error is set to ENXIO. This tags the system timer as reserved and probes it without probing any interconnected target child devices. Signed-off-by: Sinthu Raja Signed-off-by: Anurag Dutta --- drivers/bus/ti-sysc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 5566ad11399e..90766f804706 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -3117,7 +3117,8 @@ static int sysc_check_active_timer(struct sysc *ddata) * can be dropped if we stop supporting old beagleboard revisions * A to B4 at some point. */ - if (sysc_soc->soc =3D=3D SOC_3430 || sysc_soc->soc =3D=3D SOC_AM35) + if (sysc_soc->soc =3D=3D SOC_3430 || sysc_soc->soc =3D=3D SOC_AM35 || + sysc_soc->soc =3D=3D SOC_DRA7) error =3D -ENXIO; else error =3D -EBUSY; --=20 2.34.1 From nobody Fri Oct 3 12:13:09 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C40722FDFF; Mon, 1 Sep 2025 10:15:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756721753; cv=none; b=i3773OzGPqGsSXi4787UDoFo0Z9xVNItaq5XKz6+zz0h92H9ZSx60eFPSro/FKYPLAZadgC/3xjd+W+EjdQSu5HVXfi7z1lsOiTceHprjB0sJJaWrqmnI5cmRARZs1XbID0SlgcSyTmektJ2rY5wB9qxBQqtwiJaqp94vrPcKcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756721753; c=relaxed/simple; bh=WybEx41eWF9bJFyhbt3p1DGvcahsk7+xAnzqa3K3cpU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ra6RI5jFRCEh1OA/giq3HIxsKDQEYHFWZyNgr40fxCrPQbq+fAlmatYHlPcqk3WwAlUKtmMN9uucf7kboIPyD08t4B0PU7QUOLCg2ZKGW7f6l2rxFxkeKCYUJ5QOBHKep6fbxHg4v0y40PTB5GhTiHJeL8fhqGwOD7AN4MMJJ34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=HFVqgzRE; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="HFVqgzRE" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 581AFZFh2752446; Mon, 1 Sep 2025 05:15:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1756721735; bh=FtSKijCGs8TP0WXDGPNicHmfbjLsgr0U/Gpa7edboAg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HFVqgzREmbZC5VggXKTWMxzizQOGFV/XPs3yT0lFvLpl1dmGJfquLUG3pgC5n+qLw OJ5yn5uKVXJ7Mo97wYw2CeEPzd/RFjq4znkkEXe9wh49ah4z2mwv7vx0RW+JR8/SYr dtsLrMNr9seZONncj9XyiEh43Cx0Ggu+RPB+ycDw= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 581AFZFP1475747 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 1 Sep 2025 05:15:35 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 1 Sep 2025 05:15:35 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 1 Sep 2025 05:15:35 -0500 Received: from a-dutta.dhcp.ti.com (a-dutta.dhcp.ti.com [10.24.68.237]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 581AFPra2047319; Mon, 1 Sep 2025 05:15:32 -0500 From: Anurag Dutta To: , , , , CC: , , , Subject: [PATCH v2 2/2] ARM: dts: ti: omap: Use DMTimer as Clocksource instead of counter_32k Date: Mon, 1 Sep 2025 15:45:25 +0530 Message-ID: <20250901101525.1090334-3-a-dutta@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901101525.1090334-1-a-dutta@ti.com> References: <20250901101525.1090334-1-a-dutta@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Sinthu Raja Clock drift of approximately 500 ppm is observed with 'counter_32k' as clocksource. Clock drift is seen because 'counter_32k' is running with 32786Hz frequency instead it should run with 32768Hz. Use DMTimer as clocksource, which is running at 32768Hz to fix the clock drift issue. Signed-off-by: Sinthu Raja Signed-off-by: Anurag Dutta --- arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts | 9 +++++++++ arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts b/arch/arm/boo= t/dts/ti/omap/am57xx-beagle-x15.dts index 0a8b16505ed9..83009883277e 100644 --- a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts @@ -36,3 +36,12 @@ &mmc2 { &phy1 { max-speed =3D <100>; }; + +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; +}; + +&counter32k { + status =3D "disabled"; +}; diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/= omap/dra7-l4.dtsi index ba7fdaae9c6e..0e0b5364be2b 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -4439,7 +4439,7 @@ segment@20000 { /* 0x4ae20000 */ <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ =20 - target-module@0 { /* 0x4ae20000, ap 19 08.0 */ + timer12_target: target-module@0 { /* 0x4ae20000, ap 19 08.0 */ compatible =3D "ti,sysc-omap4-timer", "ti,sysc"; reg =3D <0x0 0x4>, <0x10 0x4>; --=20 2.34.1