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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 1200E41C0154; Mon, 1 Sep 2025 17:21:05 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v9 04/14] PCI: cadence: Add helper functions for supporting High Perf Architecture (HPA) Date: Mon, 1 Sep 2025 17:20:42 +0800 Message-ID: <20250901092052.4051018-5-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250901092052.4051018-1-hans.zhang@cixtech.com> References: <20250901092052.4051018-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E2:EE_|SG2PR06MB5191:EE_ X-MS-Office365-Filtering-Correlation-Id: f65b6794-0013-425f-48b4-08dde938e29e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?P3IRSSuHTTwAbN88W830mJqaGdTjR2Fbm35VDNtVnHYOiTbOTsYLN9JbIMIH?= =?us-ascii?Q?YO4Uc4ID8+ODp3RdC82N5iN+0jBId9rf5OoPx82vmAEAGZL24QDeKlHnjDAD?= =?us-ascii?Q?PLpXry00zOcVESRKuzBgTjSj1uCdgMrWwo0IRzKVY0d8femRKWt31EnOBsDM?= =?us-ascii?Q?zP/VyGC1Zc3ikKBvmEquyvonfpYxeY7hMHLGs8VaZa9ru27/Ts+wvfqV6EAa?= =?us-ascii?Q?F1LGgVrnSF6VRE5TG8TU8iOUC73XB/fsv5gH9IyTg71XcfHLCNMcOgLDFdd8?= =?us-ascii?Q?5MtQZPH6jyYA2p6OviJ6Gi8k5N8ERHzsSozQ3LOab3HTnaUo54wbPX7cwj/c?= =?us-ascii?Q?AWtnit6hGds7/SjKHQQLAcNMAiYn/jnXQMCnXAPxSlq5r1Td9dmmUyjIh713?= =?us-ascii?Q?OCFHiza0aZWIFg2Q5zmGcu7FjNrCJt9tN1pppk2OdrCrLd2Vjv4x5Ow74+tz?= =?us-ascii?Q?YjStmlfRyKzDhNaLwa8t2UyGAB25xhGb0LNp/OlRtpltpbfjroJwAspizBub?= =?us-ascii?Q?k0PZs1rB4Z2sjgM/eFX9TMLOhkn/5dK7Q0cpBTCLrpzocsd54SF0WCGg1yTg?= =?us-ascii?Q?lh8t3ZHR0azki4YDmQz3ii5JO5FjVsH4vTmgdO2V3W/Yh+Sn18DF2+nifwnm?= =?us-ascii?Q?M09t1IpOBuTZlG7uNuUO1/gAjQqYXbK7HwNi2A1JmeUpIHKfWMS+e00Y/qNl?= =?us-ascii?Q?CiN4SE8fLFYYxcuGM0Z5Xia70ma0tUnuWPdHe47J/jxJvppN6A5CCkGQq01X?= =?us-ascii?Q?ngk7J0nSqtFGsY5/VZsKidppNYqjkQMFjIW2iXW/R6umxMZlViocj+stMAb1?= =?us-ascii?Q?wrwbE788AdTBZ82mlGtCIqr9gXhlZ+PfZ+0o2jya7dWXT0gPrOzeNC/c5sfp?= =?us-ascii?Q?/YtGN76nOTki+wbpH7/NFNcArkh67oIiB76dSsEx3jxJQ571I7Twwi5Swo/9?= =?us-ascii?Q?R/Smb6CPvJy+tow4EDHyxfMCndw5TYNlQtNj4yLBNkE3feSFXpMN5LpFd8dQ?= =?us-ascii?Q?OoXivteFrHwVz6ayavggOs6Y0iZsN1PtXpGi8WXnvx30VZeozgm4gDRbueEf?= =?us-ascii?Q?6XMxIjFRfzBIVmwOuHC8Ldy6yRmhZU7NsX3eqmHjI1vXt06HbD3u0ChUTnLR?= =?us-ascii?Q?+7MfXLGCvHFGgn+xDhbhGFcSCng2aS/Ezi7uVOCT/DS11JevvPimWId/mrY3?= =?us-ascii?Q?8iEKD5dvsY6d95OiNz5QKBz5JTFfAS9qWfqDZ2XAeuEy7iZSQiwnB0BP2CBr?= =?us-ascii?Q?OGcM9hx+LSibgg7Ahd/6tbdfL8kpUetyU9ZMxtd0IwjiEdgTS2GQ7dyXejvr?= =?us-ascii?Q?khwHivn0nCpbrEb0afU0920CH7e4P1JBFGNlT6odIJFQOxHNYnSHMnEgEMC7?= =?us-ascii?Q?N5hwHDmFxkyFNa/mE4gowMhcox65q4EEyTG0tSnOxh6yUx9fnM3Qk/kHzI3/?= =?us-ascii?Q?AybcKwrioGu+SyczbqasjfaPd084shmwi/Xaf+so0Vk2jYqfshkwIw5oai20?= =?us-ascii?Q?UU9LNdBvYHFwUBDlEGwbIx0KST9tQkTYusUP?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2025 09:21:08.4122 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f65b6794-0013-425f-48b4-08dde938e29e X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E2.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB5191 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add helper functions, register read, register write functions and update platform data structures for supporting High Performance Architecture (HPA) PCIe controllers from Cadence. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../controller/cadence/pcie-cadence-plat.c | 4 - drivers/pci/controller/cadence/pcie-cadence.h | 111 ++++++++++++++++-- 2 files changed, 103 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index ebd5c3afdfcd..b067a3296dd3 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -22,10 +22,6 @@ struct cdns_plat_pcie { struct cdns_pcie *pcie; }; =20 -struct cdns_plat_pcie_of_data { - bool is_rc; -}; - static const struct of_device_id cdns_plat_pcie_of_match[]; =20 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index ddfc44f8d3ef..1174cf597bb0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -26,6 +26,20 @@ struct cdns_pcie_rp_ib_bar { }; =20 struct cdns_pcie; +struct cdns_pcie_rc; + +enum cdns_pcie_reg_bank { + REG_BANK_RP, + REG_BANK_IP_REG, + REG_BANK_IP_CFG_CTRL_REG, + REG_BANK_AXI_MASTER_COMMON, + REG_BANK_AXI_MASTER, + REG_BANK_AXI_SLAVE, + REG_BANK_AXI_HLS, + REG_BANK_AXI_RAS, + REG_BANK_AXI_DTI, + REG_BANKS_MAX, +}; =20 struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); @@ -34,6 +48,30 @@ struct cdns_pcie_ops { u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 +/** + * struct cdns_plat_pcie_of_data - Register bank offset for a platform + * @is_rc: controller is a RC + * @ip_reg_bank_offset: ip register bank start offset + * @ip_cfg_ctrl_reg_offset: ip config control register start offset + * @axi_mstr_common_offset: AXI master common register start offset + * @axi_slave_offset: AXI slave start offset + * @axi_master_offset: AXI master start offset + * @axi_hls_offset: AXI HLS offset start + * @axi_ras_offset: AXI RAS offset + * @axi_dti_offset: AXI DTI offset + */ +struct cdns_plat_pcie_of_data { + u32 is_rc:1; + u32 ip_reg_bank_offset; + u32 ip_cfg_ctrl_reg_offset; + u32 axi_mstr_common_offset; + u32 axi_slave_offset; + u32 axi_master_offset; + u32 axi_hls_offset; + u32 axi_ras_offset; + u32 axi_dti_offset; +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base @@ -45,16 +83,18 @@ struct cdns_pcie_ops { * @link: list of pointers to corresponding device link representations * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper + * @cdns_pcie_reg_offsets: Register bank offsets for different SoC */ struct cdns_pcie { - void __iomem *reg_base; - struct resource *mem_res; - struct device *dev; - bool is_rc; - int phy_count; - struct phy **phy; - struct device_link **link; - const struct cdns_pcie_ops *ops; + void __iomem *reg_base; + struct resource *mem_res; + struct device *dev; + bool is_rc; + int phy_count; + struct phy **phy; + struct device_link **link; + const struct cdns_pcie_ops *ops; + const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; }; =20 /** @@ -132,6 +172,40 @@ struct cdns_pcie_ep { unsigned int quirk_disable_flr:1; }; =20 +static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_p= cie_reg_bank bank) +{ + u32 offset =3D 0x0; + + switch (bank) { + case REG_BANK_IP_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; + break; + case REG_BANK_IP_CFG_CTRL_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; + break; + case REG_BANK_AXI_MASTER_COMMON: + offset =3D pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; + break; + case REG_BANK_AXI_MASTER: + offset =3D pcie->cdns_pcie_reg_offsets->axi_master_offset; + break; + case REG_BANK_AXI_SLAVE: + offset =3D pcie->cdns_pcie_reg_offsets->axi_slave_offset; + break; + case REG_BANK_AXI_HLS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_hls_offset; + break; + case REG_BANK_AXI_RAS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_ras_offset; + break; + case REG_BANK_AXI_DTI: + offset =3D pcie->cdns_pcie_reg_offsets->axi_dti_offset; + break; + default: + break; + }; + return offset; +} =20 /* Register access */ static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 v= alue) @@ -144,6 +218,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg, + u32 value) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + writel(value, pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + return readl(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); --=20 2.49.0