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Signed-off-by: Adrian Barna=C5=9B --- .../pci/hive_isp_css_common/host/vmem.c | 42 +++++++++---------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vme= m.c b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c index 722b684fbc37..fd640e100591 100644 --- a/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c +++ b/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c @@ -13,35 +13,33 @@ #endif #include "assert_support.h" =20 -typedef unsigned long long hive_uedge; -typedef hive_uedge *hive_wide; =20 /* Copied from SDK: sim_semantics.c */ =20 /* subword bits move like this: MSB[____xxxx____]LSB -> MSB[000000= 00xxxx]LSB */ -static inline hive_uedge -subword(hive_uedge w, unsigned int start, unsigned int end) +static inline unsigned long long +subword(unsigned long long w, unsigned int start, unsigned int end) { return (w & (((1ULL << (end - 1)) - 1) << 1 | 1)) >> start; } =20 /* inverse subword bits move like this: MSB[xxxx____xxxx]LSB -> MSB[xxxx00= 00xxxx]LSB */ -static inline hive_uedge -inv_subword(hive_uedge w, unsigned int start, unsigned int end) +static inline unsigned long long +inv_subword(unsigned long long w, unsigned int start, unsigned int end) { return w & (~(((1ULL << (end - 1)) - 1) << 1 | 1) | ((1ULL << start) - 1)= ); } =20 -#define uedge_bits (8 * sizeof(hive_uedge)) +#define uedge_bits (8 * sizeof(unsigned long long)) #define move_lower_bits(target, target_bit, src, src_bit) move_subword(tar= get, target_bit, src, 0, src_bit) #define move_upper_bits(target, target_bit, src, src_bit) move_subword(tar= get, target_bit, src, src_bit, uedge_bits) #define move_word(target, target_bit, src) move_subword(target, target_bit= , src, 0, uedge_bits) =20 static void move_subword( - hive_uedge *target, + unsigned long long *target, unsigned int target_bit, - hive_uedge src, + unsigned long long src, unsigned int src_start, unsigned int src_end) { @@ -49,18 +47,18 @@ move_subword( unsigned int start_bit =3D target_bit % uedge_bits; unsigned int subword_width =3D src_end - src_start; =20 - hive_uedge src_subword =3D subword(src, src_start, src_end); + unsigned long long src_subword =3D subword(src, src_start, src_end); =20 if (subword_width + start_bit > uedge_bits) { /* overlap */ - hive_uedge old_val1; - hive_uedge old_val0 =3D inv_subword(target[start_elem], start_bit, uedge= _bits); + unsigned long long old_val1; + unsigned long long old_val0 =3D inv_subword(target[start_elem], start_bi= t, uedge_bits); =20 target[start_elem] =3D old_val0 | (src_subword << start_bit); old_val1 =3D inv_subword(target[start_elem + 1], 0, subword_width + start_bit - uedge_bits); target[start_elem + 1] =3D old_val1 | (src_subword >> (uedge_bits - star= t_bit)); } else { - hive_uedge old_val =3D inv_subword(target[start_elem], start_bit, + unsigned long long old_val =3D inv_subword(target[start_elem], start_bit, start_bit + subword_width); =20 target[start_elem] =3D old_val | (src_subword << start_bit); @@ -69,8 +67,8 @@ move_subword( =20 static void hive_sim_wide_unpack( - hive_wide vector, - hive_wide elem, + unsigned long long *vector, + unsigned long long *elem, hive_uint elem_bits, hive_uint index) { @@ -103,8 +101,8 @@ hive_sim_wide_unpack( =20 static void hive_sim_wide_pack( - hive_wide vector, - hive_wide elem, + unsigned long long *vector, + unsigned long long *elem, hive_uint elem_bits, hive_uint index) { @@ -136,7 +134,7 @@ static void load_vector( const t_vmem_elem *from) { unsigned int i; - hive_uedge *data; + unsigned long long *data; unsigned int size =3D sizeof(short) * ISP_NWAY; =20 VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bu= g */ @@ -146,9 +144,9 @@ static void load_vector( #else hrt_master_port_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], = size); #endif - data =3D (hive_uedge *)v; + data =3D (unsigned long long *)v; for (i =3D 0; i < ISP_NWAY; i++) { - hive_uedge elem =3D 0; + unsigned long long elem =3D 0; =20 hive_sim_wide_unpack(data, &elem, ISP_VEC_ELEMBITS, i); to[i] =3D elem; @@ -166,10 +164,10 @@ static void store_vector( =20 VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bu= g */ //load_vector (&v[1][0], &to[ISP_NWAY]); /* Fetch the next vector, since = it will be overwritten. */ - hive_uedge *data =3D (hive_uedge *)v; + unsigned long long *data =3D (unsigned long long *)v; =20 for (i =3D 0; i < ISP_NWAY; i++) { - hive_sim_wide_pack(data, (hive_wide)&from[i], ISP_VEC_ELEMBITS, i); + hive_sim_wide_pack(data, (unsigned long long *)&from[i], ISP_VEC_ELEMBIT= S, i); } assert(ISP_BAMEM_BASE[ID] !=3D (hrt_address) - 1); #if !defined(HRT_MEMORY_ACCESS) --=20 2.51.0.318.gd7df087d1a-goog