From nobody Fri Oct 3 13:32:06 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9D2D261B83; Mon, 1 Sep 2025 05:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756706379; cv=none; b=u/fNAZuaU0QH9HxxjmQtYymqruw5LsV/bqDBOGDzFDMmoBwIz28j1//Vg8TlP1arjw6OD141sA8baAty/HdQFEtuZLkTm91+xGgWbUHOS5VVraXQWhaO5eOLfv4/O3zjTuQK/VmRuo6kYyTG+qo4zYmjICR2yb8ocUfAJAdBBac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756706379; c=relaxed/simple; bh=WE3oxJhSDkuSNkGWeldGWuoI8/etXYzwCr2Q3E4+cfQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MakQ7osKpwVUA/fZz4aucwShF7WAALoWs1cUJbHynWNG6/wtFsCQju4J3soDXNBES5iqDUxdTnSHtw1Vsz927fmhFXRsa1pHqzm3T6EpoeSX2rQ8D29anfmIz3SXjllLwq7fVDmliBsWI7gCemM2y7O6a3mubetKjsysJ936g70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Sep 2025 13:59:23 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Sep 2025 13:59:23 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 07/10] PHY: aspeed: Add ASPEED PCIe PHY driver Date: Mon, 1 Sep 2025 13:59:19 +0800 Message-ID: <20250901055922.1553550-8-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901055922.1553550-1-jacky_chou@aspeedtech.com> References: <20250901055922.1553550-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Aspeed PCIe PHY controller available in AST2600/2700. Signed-off-by: Jacky Chou --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/aspeed/Kconfig | 15 ++ drivers/phy/aspeed/Makefile | 2 + drivers/phy/aspeed/phy-aspeed-pcie.c | 209 +++++++++++++++++++++++++++ 5 files changed, 228 insertions(+) create mode 100644 drivers/phy/aspeed/Kconfig create mode 100644 drivers/phy/aspeed/Makefile create mode 100644 drivers/phy/aspeed/phy-aspeed-pcie.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 58c911e1b2d2..ac4bf46f24e2 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -103,6 +103,7 @@ config PHY_NXP_PTN3222 =20 source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" +source "drivers/phy/aspeed/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/freescale/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c670a8dac468..12fd50e5ea9b 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o obj-y +=3D allwinner/ \ amlogic/ \ + aspeed/ \ broadcom/ \ cadence/ \ freescale/ \ diff --git a/drivers/phy/aspeed/Kconfig b/drivers/phy/aspeed/Kconfig new file mode 100644 index 000000000000..6aeeca84091f --- /dev/null +++ b/drivers/phy/aspeed/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Aspeed platforms +# +config PHY_ASPEED_PCIE + tristate "ASPEED PCIe PHY driver" + select GENERIC_PHY + depends on ARCH_ASPEED + default y + help + This option enables support for the ASPEED PCIe PHY driver. + The driver provides the necessary interface to control and + configure the PCIe PHY hardware found on ASPEED SoCs. + It is required for proper operation of PCIe devices on + platforms using ASPEED chips. \ No newline at end of file diff --git a/drivers/phy/aspeed/Makefile b/drivers/phy/aspeed/Makefile new file mode 100644 index 000000000000..7203152f44bf --- /dev/null +++ b/drivers/phy/aspeed/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_ASPEED_PCIE) +=3D phy-aspeed-pcie.o \ No newline at end of file diff --git a/drivers/phy/aspeed/phy-aspeed-pcie.c b/drivers/phy/aspeed/phy-= aspeed-pcie.c new file mode 100644 index 000000000000..4b78ceeb5a5e --- /dev/null +++ b/drivers/phy/aspeed/phy-aspeed-pcie.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Aspeed Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* AST2600 PCIe Host Controller Registers */ +#define PEHR_GLOBAL 0x30 +#define AST2600_PORT_TYPE_MASK GENMASK(5, 4) +#define AST2600_PORT_TYPE(x) FIELD_PREP(AST2600_PORT_TYPE_MASK, x) +#define PEHR_LOCK 0x7c +#define PCIE_UNLOCK 0xa8 + +/* AST2700 PEHR */ +#define PEHR_MISC_58 0x58 +#define LOCAL_SCALE_SUP BIT(0) +#define PEHR_MISC_5C 0x5c +#define CONFIG_RC_DEVICE BIT(30) +#define PEHR_MISC_60 0x60 +#define AST2700_PORT_TYPE_MASK GENMASK(7, 4) +#define PORT_TYPE_ROOT BIT(6) +#define PEHR_MISC_70 0x70 +#define POSTED_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x) +#define POSTED_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x) +#define PEHR_MISC_78 0x78 +#define COMPLETION_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x) +#define COMPLETION_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x) + +/** + * struct aspeed_pcie_phy - PCIe PHY information + * @dev: pointer to device structure + * @reg: PCIe host register base address + * @phy: pointer to PHY structure + * @platform: platform specific information + */ +struct aspeed_pcie_phy { + struct device *dev; + void __iomem *reg; + struct phy *phy; + const struct aspeed_pcie_phy_platform *platform; +}; + +/** + * struct aspeed_pcie_phy_platform - Platform information + * @phy_ops: phy operations + */ +struct aspeed_pcie_phy_platform { + const struct phy_ops *phy_ops; +}; + +static int ast2600_phy_init(struct phy *phy) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + + writel(PCIE_UNLOCK, pcie_phy->reg + PEHR_LOCK); + + return 0; +} + +static int ast2600_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + + switch (submode) { + case PHY_MODE_PCIE_RC: + writel(AST2600_PORT_TYPE(0x3), pcie_phy->reg + PEHR_GLOBAL); + break; + default: + dev_err(&phy->dev, "Unsupported submode %d\n", submode); + return -EINVAL; + } + + return 0; +} + +static const struct phy_ops ast2600_phy_ops =3D { + .init =3D ast2600_phy_init, + .set_mode =3D ast2600_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int ast2700_phy_init(struct phy *phy) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + + writel(POSTED_DATA_CREDITS(0xc0) | POSTED_HEADER_CREDITS(0xa), + pcie_phy->reg + PEHR_MISC_70); + writel(COMPLETION_DATA_CREDITS(0x30) | COMPLETION_HEADER_CREDITS(0x8), + pcie_phy->reg + PEHR_MISC_78); + writel(LOCAL_SCALE_SUP, pcie_phy->reg + PEHR_MISC_58); + + return 0; +} + +static int ast2700_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + u32 cfg_val; + + switch (submode) { + case PHY_MODE_PCIE_RC: + writel(CONFIG_RC_DEVICE, pcie_phy->reg + PEHR_MISC_5C); + cfg_val =3D readl(pcie_phy->reg + PEHR_MISC_60); + cfg_val &=3D ~AST2700_PORT_TYPE_MASK; + cfg_val |=3D PORT_TYPE_ROOT; + writel(cfg_val, pcie_phy->reg + PEHR_MISC_60); + break; + default: + dev_err(&phy->dev, "Unsupported submode %d\n", submode); + return -EINVAL; + } + + return 0; +} + +static const struct phy_ops ast2700_phy_ops =3D { + .init =3D ast2700_phy_init, + .set_mode =3D ast2700_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +const struct aspeed_pcie_phy_platform pcie_phy_ast2600 =3D { + .phy_ops =3D &ast2600_phy_ops, +}; + +const struct aspeed_pcie_phy_platform pcie_phy_ast2700 =3D { + .phy_ops =3D &ast2700_phy_ops, +}; + +static int aspeed_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + struct aspeed_pcie_phy *pcie_phy; + const struct aspeed_pcie_phy_platform *md; + + md =3D of_device_get_match_data(dev); + if (!md) + return -ENODEV; + + pcie_phy =3D devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL); + if (!pcie_phy) + return -ENOMEM; + + pcie_phy->reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pcie_phy->reg)) + return PTR_ERR(pcie_phy->reg); + + pcie_phy->dev =3D dev; + pcie_phy->platform =3D md; + + pcie_phy->phy =3D devm_phy_create(dev, dev->of_node, + pcie_phy->platform->phy_ops); + if (IS_ERR(pcie_phy->phy)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy), + "failed to create PHY\n"); + + phy_set_drvdata(pcie_phy->phy, pcie_phy); + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id aspeed_pcie_phy_of_match_table[] =3D { + { + .compatible =3D "aspeed,ast2600-pcie-phy", + .data =3D &pcie_phy_ast2600, + }, + { + .compatible =3D "aspeed,ast2700-pcie-phy", + .data =3D &pcie_phy_ast2700, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, aspeed_pcie_of_match_table); + +static struct platform_driver aspeed_pcie_driver =3D { + .probe =3D aspeed_pcie_phy_probe, + .driver =3D { + .name =3D "aspeed-pcie-phy", + .of_match_table =3D aspeed_pcie_phy_of_match_table, + }, +}; + +module_platform_driver(aspeed_pcie_driver); + +MODULE_AUTHOR("Jacky Chou "); +MODULE_DESCRIPTION("ASPEED PCIe PHY"); +MODULE_LICENSE("GPL"); --=20 2.43.0