From nobody Fri Oct 3 13:32:07 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A93D224DFF3; Mon, 1 Sep 2025 05:59:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756706370; cv=none; b=nJYO+DNVJGO/lqz1pbXbDAM2LC7Z9P86MRRgi3d+0Ett2JSmcGhSglC5rlA+fAiUu6UCGnM5VhJPjj7pDGYukHU5Fsk/rZluY7xfw0wb/0lzvcfD5wZrp3M+CpF3w1ivnMJ/vGacLWku+T1yLJ+gnc8CSUfZqrkCVQ2Xxiko0ZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756706370; c=relaxed/simple; bh=lcRx6zVnZWP5Lc8mK2qRMxScwBz/UAuPlv7DnaKEvgc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oit2R8j2SgY09VwfPcAntvbo63dTnb1nqu7V+LzGg3O8RMSWzN6qZB1DHK7NXuO3bF7lKQGeh5JzL/enJnxTV5YxaqjGjO1gAzvpSlnBiISbGW/6Hnpymj1RZfJbnNRQO5yQ9/M9W+vEtlcclLrdjwv6kdzGrv9QV86QrPq1iw0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Sep 2025 13:59:22 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Sep 2025 13:59:22 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH v3 02/10] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Date: Mon, 1 Sep 2025 13:59:14 +0800 Message-ID: <20250901055922.1553550-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901055922.1553550-1-jacky_chou@aspeedtech.com> References: <20250901055922.1553550-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce device-binding for ASPEED AST2600/2700 PCIe PHY. The PCIe PHY is used for PCIe RC to configure as RC mode. Signed-off-by: Jacky Chou Reviewed-by: Rob Herring (Arm) --- .../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/aspeed,ast2600-pc= ie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.= yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml new file mode 100644 index 000000000000..71a5cd91fb3f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe PHY + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe PHY provides the physical layer functionality for PCIe + controllers in the SoC. + +properties: + compatible: + items: + - enum: + - aspeed,ast2600-pcie-phy + - aspeed,ast2700-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@1e6ed200 { + compatible =3D "aspeed,ast2600-pcie-phy"; + reg =3D <0x1e6ed200 0x100>; + #phy-cells =3D <0>; + }; --=20 2.43.0