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Mon, 1 Sep 2025 05:42:39 +0000 (GMT) From: Ravi Patel To: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de Cc: ksk4725@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, smn1196@coasia.com, shradha.t@samsung.com, ravi.patel@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Priyadarsini G Subject: [PATCH v4 2/6] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration Date: Mon, 1 Sep 2025 10:49:22 +0530 Message-Id: <20250901051926.59970-3-ravi.patel@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250901051926.59970-1-ravi.patel@samsung.com> X-CMS-MailID: 20250901054244epcas5p474b65dbf838296ba3177edaeb2c6ec97 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250901054244epcas5p474b65dbf838296ba3177edaeb2c6ec97 References: <20250901051926.59970-1-ravi.patel@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 From: SeonGu Kang Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang Signed-off-by: Priyadarsini G Signed-off-by: Ravi Patel --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 50 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 10 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 63 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index 5fe7c4b9f7bd..323487dfa8c2 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_ban= k_type_off =3D { .reg_offset =3D { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, }; =20 +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static const struct samsung_pin_bank_type artpec_bank_type_off =3D { + .fld_width =3D { 4, 1, 4, 4, }, + .reg_offset =3D { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; =20 @@ -1816,3 +1825,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_= data __initconst =3D { .ctrl =3D gs101_pin_ctrl, .num_ctrl =3D ARRAY_SIZE(gs101_pin_ctrl), }; + +/* pin banks of artpec8 pin-controller (FSYS0) */ +static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst= =3D { + ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00), + ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08), + ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c), + ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10), + ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14), + ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18), + ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c), + ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20), + ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24), +}; + +/* pin banks of artpec8 pin-controller (PERIC) */ +static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst= =3D { + ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c), +}; + +static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst =3D { + { + /* pin-controller instance 0 FSYS data */ + .pin_banks =3D artpec8_pin_banks0, + .nr_banks =3D ARRAY_SIZE(artpec8_pin_banks0), + .eint_gpio_init =3D exynos_eint_gpio_init, + }, { + /* pin-controller instance 1 PERIC data */ + .pin_banks =3D artpec8_pin_banks1, + .nr_banks =3D ARRAY_SIZE(artpec8_pin_banks1), + .eint_gpio_init =3D exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst =3D= { + .ctrl =3D artpec8_pin_ctrl, + .num_ctrl =3D ARRAY_SIZE(artpec8_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index 362dc533186f..c9c38f8988dd 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -236,6 +236,16 @@ .name =3D id \ } =20 +#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type =3D &artpec_bank_type_off, \ + .pctl_offset =3D reg, \ + .nr_pins =3D pins, \ + .eint_type =3D EINT_TYPE_GPIO, \ + .eint_offset =3D offs, \ + .name =3D id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrup= ts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index 24745e1d78ce..c099195fc464 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1482,6 +1482,8 @@ static const struct of_device_id samsung_pinctrl_dt_m= atch[] =3D { .data =3D &s5pv210_of_data }, #endif #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 + { .compatible =3D "axis,artpec8-pinctrl", + .data =3D &artpec8_of_data }, { .compatible =3D "google,gs101-pinctrl", .data =3D &gs101_of_data }, { .compatible =3D "samsung,exynos2200-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index 1cabcbe1401a..be2dee886d81 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -381,6 +381,7 @@ struct samsung_pmx_func { }; =20 /* list of all exported SoC specific data */ +extern const struct samsung_pinctrl_of_match_data artpec8_of_data; extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; --=20 2.49.0