From nobody Fri Oct 3 13:32:07 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AE45229B2A; Mon, 1 Sep 2025 04:25:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756700703; cv=none; b=HenJ8ZhImpWcM4DVO5LXOS+o4qJgKy5QqNkOq42U6fbksOQwwUOb/6ug3lHJ4DVQ3sBUOBspJrGuM54gAjnmAq0XcEnj147R04Qgg9rhHrm7hKH6z5VCe907YOMUMP9vSXArJWbCAzSpDTV+q6LPokVwg4EMvb1G9oMVdyTwSTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756700703; c=relaxed/simple; bh=IBslNheDZQKi8czdVueADyFl/OhJ12YV0b0a6fTRNBE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BQ41Ef1CB1iNYS9Yr5P8xIgW0OCfOFYZ97xBNixmfRbMwdklNLWJE5P9oEYpXb0ZuSdBQ1Kbjz5Nqk+1sYk77e1hYOWRk0LDsW1IVswSkQl1UkR03lawUL1GRvmwHnqS91RFYPvmxmYwbXBkcZe9WOzlWcxP4KPHz6hZn+bSweE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Yjl+PQAo; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Yjl+PQAo" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 534D020A4A; Mon, 1 Sep 2025 06:25:00 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id xqWkWWlIwsnK; Mon, 1 Sep 2025 06:24:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1756700699; bh=IBslNheDZQKi8czdVueADyFl/OhJ12YV0b0a6fTRNBE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Yjl+PQAo4Sqf4Q068Fp2s12iFBzveSRFGCG/8eZLYHan4kdeB7UwJ50E1UTn6MK22 tfuC3D9JM1NIm+ZA4MLrTNg+32gHm8Zc0uC8p1OIrIcf9yQpBYwq6PyuWaBnRYLYeQ ufBpITelFgBXAguHxkoQrCHI6Zd4qHV2o3H4KChIiifJPywxrMHwiP6d/aLEi7jTjH ZvclS4kk1ql2qypcfKHllsNhvqPJnex01ZvXkL5B2emA9o9K58zo6qulVqgo2x0oo+ e9KDC/x0/xiEmuVkn9IKBk4F4z/QQX+bkCrg7kQ5H86hwftDeN49/kxx1x+Oui13bu xvObz2R0MMlOw== From: Yao Zi To: Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Michal Wilczynski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng , Han Gao , Han Gao , Yao Zi Subject: [PATCH 4/4] riscv: dts: thead: Add reset controllers of more subsystems for TH1520 Date: Mon, 1 Sep 2025 04:23:20 +0000 Message-ID: <20250901042320.22865-5-ziyao@disroot.org> In-Reply-To: <20250901042320.22865-1-ziyao@disroot.org> References: <20250901042320.22865-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The one for AO subsystem is marked as reserved, since it may be used by AON firmware. Signed-off-by: Yao Zi --- arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 03f1d7319049..e9fa0df0b56c 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -270,6 +270,12 @@ clint: timer@ffdc000000 { <&cpu3_intc 3>, <&cpu3_intc 7>; }; =20 + rst_vi: reset-controller@ffe4040100 { + compatible =3D "thead,th1520-reset-vi"; + reg =3D <0xff 0xe4040100 0x0 0x8>; + #reset-cells =3D <1>; + }; + spi0: spi@ffe700c000 { compatible =3D "thead,th1520-spi", "snps,dw-apb-ssi"; reg =3D <0xff 0xe700c000 0x0 0x1000>; @@ -495,6 +501,18 @@ uart2: serial@ffec010000 { status =3D "disabled"; }; =20 + rst_misc: reset-controller@ffec02c000 { + compatible =3D "thead,th1520-reset-misc"; + reg =3D <0xff 0xec02c000 0x0 0x18>; + #reset-cells =3D <1>; + }; + + rst_vp: reset-controller@ffecc30000 { + compatible =3D "thead,th1520-reset-vp"; + reg =3D <0xff 0xecc30000 0x0 0x14>; + #reset-cells =3D <1>; + }; + clk: clock-controller@ffef010000 { compatible =3D "thead,th1520-clk-ap"; reg =3D <0xff 0xef010000 0x0 0x1000>; @@ -502,6 +520,18 @@ clk: clock-controller@ffef010000 { #clock-cells =3D <1>; }; =20 + rst_ap: reset-controller@ffef014000 { + compatible =3D "thead,th1520-reset-ap"; + reg =3D <0xff 0xef014000 0x0 0x1000>; + #reset-cells =3D <1>; + }; + + rst_dsp: reset-controller@ffef040028 { + compatible =3D "thead,th1520-reset-dsp"; + reg =3D <0xff 0xef040028 0x0 0x4>; + #reset-cells =3D <1>; + }; + rst: reset-controller@ffef528000 { compatible =3D "thead,th1520-reset"; reg =3D <0xff 0xef528000 0x0 0x4f>; @@ -660,6 +690,13 @@ aogpio: gpio-controller@0 { }; }; =20 + rst_ao: reset-controller@fffff44000 { + compatible =3D "thead,th1520-reset-ao"; + reg =3D <0xff 0xfff44000 0x0 0x2000>; + #reset-cells =3D <1>; + status =3D "reserved"; + }; + padctrl_aosys: pinctrl@fffff4a000 { compatible =3D "thead,th1520-pinctrl"; reg =3D <0xff 0xfff4a000 0x0 0x2000>; --=20 2.50.1