From nobody Fri Oct 3 13:33:54 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB62A221739; Mon, 1 Sep 2025 03:13:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756696408; cv=none; b=Pds6VmWmhf9UjJaMsQ5F4M5t3U4Wr6HLOoW0zggIjI1tWSMIkfxZMtf0yfjMLnh6GiS3CX6rQaSLOTgyVqVTqdY+mDJoFf4ihSegufnJFuQEay/+AF3cBaCsSM+UmVP0yPGIPYF1tYLCXfwtHSWVBr0nNrkY3SfU0dpW3z7QeaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756696408; c=relaxed/simple; bh=KLervDl/ngiF2hOrIUPtav+GZpCddp07RiWaxHaF414=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R7+0QQAJD2yAdsQw8deyRRcou6Hq9LbmdMaw+p0KAStjbwL0HlWVW2l7ZXKXgXRZnEsADAjWgJ/iG1rZMOy0IsaMpTw14oC8olSFW2mPz9kW5A45xh6KCpvHRHuUD/LmAS2ryPYyzqADBsIbAvHMGl7kUAJeimMz0eNgVs/Zi8M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Sep 2025 11:13:11 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Sep 2025 11:13:11 +0800 From: Ryan Chen To: ryan_chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , , , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , , , , Subject: [PATCH v5 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree Date: Mon, 1 Sep 2025 11:13:09 +0800 Message-ID: <20250901031311.1247805-4-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250901031311.1247805-1-ryan_chen@aspeedtech.com> References: <20250901031311.1247805-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial device tree for the ASPEED 8th BMC SoC family. Signed-off-by: Ryan Chen --- arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 452 ++++++++++++++++++++++ 1 file changed, 452 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dt= s/aspeed/aspeed-g7.dtsi new file mode 100644 index 000000000000..4816b017f987 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include + +/ { + compatible =3D "aspeed,ast2700"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + serial6 =3D &uart6; + serial7 =3D &uart7; + serial8 =3D &uart8; + serial9 =3D &uart9; + serial10 =3D &uart10; + serial11 =3D &uart11; + serial12 =3D &uart12; + serial13 =3D &uart13; + serial14 =3D &uart14; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x2>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x3>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + }; + }; + + firmware { + optee: optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + atf: trusted-firmware-a@430000000 { + reg =3D <0x4 0x30000000 0x0 0x80000>; + no-map; + }; + + optee_core: optee-core@430080000 { + reg =3D <0x4 0x30080000 0x0 0x1000000>; + no-map; + }; + }; + + arm-pmu { + compatible =3D "arm,cortex-a35-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + gic: interrupt-controller@12200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x12200000 0 0x10000>, /* GICD */ + <0 0x12280000 0 0x80000>, /* GICR */ + <0 0x40440000 0 0x1000>; /* GICC */ + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + }; + + soc0: soc@10000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + intc0_11: interrupt-controller@12101b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x12101b00 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + }; + + syscon0: syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg =3D <0x0 0x12c02000 0x0 0x1000>; + ranges =3D <0x0 0x0 0 0x12c02000 0 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + silicon-id@0 { + compatible =3D "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg =3D <0 0x0 0 0x4>; + }; + + }; + + gpio0: gpio@12c11000 { + #gpio-cells =3D <2>; + gpio-controller; + compatible =3D "aspeed,ast2700-gpio"; + reg =3D <0x0 0x12c11000 0x0 0x1000>; + interrupts =3D ; + ngpios =3D <12>; + clocks =3D <&syscon0 SCU0_CLK_APB>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + uart4: serial@12c1a000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x12c1a000 0x0 0x1000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon0 SCU0_CLK_GATE_UART4CLK>; + interrupts =3D ; + no-loopback-test; + status =3D "disabled"; + }; + }; + + soc1: soc@14000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + mdio0: mdio@14040000 { + compatible =3D "aspeed,ast2600-mdio"; + reg =3D <0 0x14040000 0 0x8>; + resets =3D <&syscon1 SCU1_RESET_MII>; + status =3D "disabled"; + }; + + mdio1: mdio@14040008 { + compatible =3D "aspeed,ast2600-mdio"; + reg =3D <0 0x14040008 0 0x8>; + resets =3D <&syscon1 SCU1_RESET_MII>; + status =3D "disabled"; + }; + + mdio2: mdio@14040010 { + compatible =3D "aspeed,ast2600-mdio"; + reg =3D <0 0x14040010 0 0x8>; + resets =3D <&syscon1 SCU1_RESET_MII>; + status =3D "disabled"; + }; + + syscon1: syscon@14c02000 { + compatible =3D "aspeed,ast2700-scu1"; + reg =3D <0x0 0x14c02000 0x0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + intc1_0: interrupt-controller@14c18100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18100 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0>; + }; + + intc1_1: interrupt-controller@14c18110 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18110 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 1>; + }; + + intc1_2: interrupt-controller@14c18120 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18120 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 2>; + }; + + intc1_3: interrupt-controller@14c18130 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18130 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 3>; + }; + + intc1_4: interrupt-controller@14c18140 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18140 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 4>; + }; + + intc1_5: interrupt-controller@14c18150 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x14c18150 0x0 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 5>; + }; + + uart0: serial@14c33000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART0CLK>; + interrupts-extended =3D <&intc1_4 7>; + no-loopback-test; + status =3D "disabled"; + }; + + uart1: serial@14c33100 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33100 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART1CLK>; + interrupts-extended =3D <&intc1_4 8>; + no-loopback-test; + status =3D "disabled"; + }; + + uart2: serial@14c33200 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33200 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART2CLK>; + interrupts-extended =3D <&intc1_4 9>; + no-loopback-test; + status =3D "disabled"; + }; + + uart3: serial@14c33300 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33300 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART3CLK>; + interrupts-extended =3D <&intc1_4 10>; + no-loopback-test; + status =3D "disabled"; + }; + + uart5: serial@14c33400 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33400 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART5CLK>; + interrupts-extended =3D <&intc1_4 11>; + no-loopback-test; + status =3D "disabled"; + }; + + uart6: serial@14c33500 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33500 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART6CLK>; + interrupts-extended =3D <&intc1_4 12>; + no-loopback-test; + status =3D "disabled"; + }; + + uart7: serial@14c33600 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33600 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART7CLK>; + interrupts-extended =3D <&intc1_4 13>; + no-loopback-test; + status =3D "disabled"; + }; + + uart8: serial@14c33700 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33700 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART8CLK>; + interrupts-extended =3D <&intc1_4 14>; + no-loopback-test; + status =3D "disabled"; + }; + + uart9: serial@14c33800 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33800 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART9CLK>; + interrupts-extended =3D <&intc1_4 15>; + no-loopback-test; + status =3D "disabled"; + }; + + uart10: serial@14c33900 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33900 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART10CLK>; + interrupts-extended =3D <&intc1_4 16>; + no-loopback-test; + status =3D "disabled"; + }; + + uart11: serial@14c33a00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33a00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART11CLK>; + interrupts-extended =3D <&intc1_4 17>; + no-loopback-test; + status =3D "disabled"; + }; + + uart12: serial@14c33b00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33b00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART12CLK>; + interrupts-extended =3D <&intc1_4 18>; + no-loopback-test; + status =3D "disabled"; + }; + + uart13: serial@14c33c00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33c00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_UART13>; + interrupts-extended =3D <&intc1_0 23>; + no-loopback-test; + status =3D "disabled"; + }; + + uart14: serial@14c33d00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33d00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_UART14>; + interrupts-extended =3D <&intc1_1 23>; + no-loopback-test; + status =3D "disabled"; + }; + }; +}; --=20 2.34.1