From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F38A6217F55; Mon, 1 Sep 2025 11:04:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724700; cv=none; b=IpaIlRhxRIOyvyB8myWEtwW+NNZLDOi7kZdvXyVquGSEvvurfRu2Cms9iM88qvfqsaTtt7DnzcC9OghVGuRxmx1QtpHHKnNGQfv8eSmvHCAkYoYupu1jxhMZMDem10+RAbH0W3epqaZaROL5ILqB6C2pxcyPgPKXKLEafv137CM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724700; c=relaxed/simple; bh=jECQWUPeqYIp+kYy0qMp+mxlsYrMNhCp3lRCnaD5i0o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N8If7SZMFE7uZ+2a7w9R9sG77TsH+jQZpLDwsNXHtOYkVhdnaXfYtnxeqBNy3KOjmt5b3FtRzRrqGGqsSh3FxVRJfE93Xk9l++5+ExFobcCWnK2Q3IKrY3U6atxQWvARinPU/mUcdqnt5dW44kvEcbhJkdX0MVklUS/kQFAujAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AfWQ9sjz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AfWQ9sjz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF20CC4CEF4; Mon, 1 Sep 2025 11:04:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724699; bh=jECQWUPeqYIp+kYy0qMp+mxlsYrMNhCp3lRCnaD5i0o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AfWQ9sjzOXKkzgqnkTBQAdhVnJYC42z1ZpCbvzM6Ofdj71q+CKR4qzih3qMObRcqK 2EjhcTUaN3J93IPSS1pp1Wi+z88E56LFeyOHwuHMEla8MP7CrWYXoiKlQUL7JGX9GE S0lpQmaavEZpx41L0ByTP8Tz9y5/zHuTQec39Us9ocDGA1Xo5dtFAZArV06AM6IwgS FD02yt4WO/1F7ze2Roly+MB7PVH8vEAvAoC+KgR/PK9TxsWr1u2cdnpFryHEFOB+j0 fBN7IAQ1lQ8DSxOmalTnrt8aK4haCMCerEReBB9dzzHZVnnEt9v0sl6FrrD3cR9BeW 57XhFajTAsWMQ== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ , Krzysztof Kozlowski Subject: [PATCH v4 1/9] dt-bindings: mfd: syscon document the control-scb syscon on PolarFire SoC Date: Mon, 1 Sep 2025 12:04:13 +0100 Message-ID: <20250901-shorten-yahoo-223aeaecd290@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1505; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=5rg4qG6+r0Tz8RYgLEQxmEix629uHarZjM4QelP6QtY=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9ceDjmisSn0m1FVy/3tt/Un8UrKr/j4d4ooV3PWg l+NsyoFOkpZGMS4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjARBm9Ghjcx7eELJzgLlW/+ dJNDVVdPO7D7uZxLxe//VhOnCqVe+szwV/p59wtRNY+mH61y13XP6EtxvSx+WHD2QkxYbdeHhKn WjAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "control-scb" region, contains the "tvs" temperature and voltage sensors and the control/status registers for the system controller's mailbox. The mailbox has a dedicated node, so there's no need for a child node describing it, looking the syscon up by compatible is sufficient. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- v2: add the control-scb syscon here too, since it doesn't have any children. --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 27672adeb1fed..d18be50dd7127 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -90,6 +90,7 @@ select: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy @@ -197,6 +198,7 @@ properties: - mediatek,mt8365-infracfg-nao - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E51C1217F55; Mon, 1 Sep 2025 11:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724704; cv=none; b=A9zS9kLkGT4ItGJbMhx1WYDv/i8HhdxUYNDfNuqvJv0M8+NJ0hyJ/RNDCxMjt4gH+H7OQT/r6ZCB4bu9cMx1nHGbY0t54qLJ2O7yqSItWyF9q+eCFKkYLEc5ByKXqmCWb+sTp7dS4+4TOuGIrN77F85Y394DKJyfoIqsZlYfHRc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724704; c=relaxed/simple; bh=m5ocoAhQ9i2Yxyd23Uis14ToLuXf0jZLSM0DHyjyLJA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aPT47HyorcJ0hShw8ZjDp/Rc+xtY+Y8JGe0mDjVYuCbwf4olkfvtH35mMWMAM7XZbBP4yElwVAdCWthlhzic+jhEGns3QZNBlHKR/aeeRivHcc+qqT91FR9ff27jVBgD0yJvLy+n8t18jnk0Tu0XN/uKF4f9TYME3pSewUZZDJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Bq6Y8EX7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Bq6Y8EX7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8390C4CEF0; Mon, 1 Sep 2025 11:04:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724703; bh=m5ocoAhQ9i2Yxyd23Uis14ToLuXf0jZLSM0DHyjyLJA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bq6Y8EX7ppY3fE5wNtkCzbJNicM5PKEp91aTlMiYjbAboyoWAEzuxiY9IJLz0KRlb A9wL4kRm0TKg40uteBK4RO7HJXqRw5zaiQNNHzWU93qcypItGmQr+X6E7fNRv6yUrP ApbWsR4AyVBjjGdOb9soTx+0d6vWxshEGG+RIJjqV7mw/t4rcu5StTREgBQb268lhY i9mFVs7zDJuaeBr4CG9xDrMYdxh4YBALwZXlmV9YAA8dSeRbupxonBixMTz84KlCzw K9sEuy5Dnc04kp9dpUeQurzsNSwYejCclUJpdz6bdgErQp6ae1UjtPPqkj+jCBNrxE uItuv34qUBjNw== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ , Krzysztof Kozlowski Subject: [PATCH v4 2/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC Date: Mon, 1 Sep 2025 12:04:14 +0100 Message-ID: <20250901-garbage-hardship-027861fb3380@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2943; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=b+aGSGhQUJdmsPs1oLuFh7qLo75fMDz/w1qPMM5tYX0=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9eGXrq6UORSxIapJ96K6FccM8zh8rKbsqHPteSd8 Emb/PnrO0pZGMS4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCR2RqMDPcn6Z0+Ofdaqq6k 6/9Ixpz1y1Tf2TK8O6gc/d9TY+Pdb+YMPxnNP1Q5RN/+LZM06eaRdbGbHrFEex9rmeBlfv7n/XM b8lgB X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley "mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller and more. At this point, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before, so no child is needed. There's also an interrupt multiplexing service provided by this syscon, for which there is work in progress at [1]. Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a= 4fefe@wendy/ [1] Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- v3: - drop simple-mfd at Krzysztof's request since the child nodes do not yet exist. v2: - clean up various minor comments from Rob on mpfs-mss-top-sysreg - remove mpfs-control-scb from this patch --- .../microchip,mpfs-mss-top-sysreg.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-mss-top-sysreg.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 0000000000000..1ab691db87950 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sy= sreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg regis= ter region + +maintainers: + - Conor Dooley + +description: + An wide assortment of registers that control elements of the MSS on Pola= rFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st + of PolarFire clock/reset IDs. + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon"; + reg =3D <0x20002000 0x1000>; + #reset-cells =3D <1>; + }; + --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 268743112DE; Mon, 1 Sep 2025 11:05:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724708; cv=none; b=kBVJTanbXab4suRQVFyso3L6GIsK2y4UdY2w+mkRknkcT9eJRitDo4ZwgvfGkruuzYVNMK7zWSKF3AN8t0Iw+lx78GA6YQaImrXotX+E9gV7OzmF33o/FHaNuMXpbKA+1tFNGy/R31dcK/9gNxRHoH1NyqOQfsujmsxKjUYUccE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724708; c=relaxed/simple; bh=SZ65yBZC7lEGa0Ak3OsvShyUfq6wluR5gsaWqbe1c/Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VtuMYWCy5033txdqNY12tXG8OfTAC7RKsP7JGHMIoCidx+5lVTsu2MPQqg4Tn9NuQl7RHWKo7mv28L3Wg9h1dbOVt2ptjthClkuXoOpvdzlH6VSufyzpED7HCRMxYoYjYzuibpL95MHG3YiGtUhEGjrD8IW7HVDhY5Adn6Kne2A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c+d3JVqR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c+d3JVqR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3668CC4CEF0; Mon, 1 Sep 2025 11:05:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724707; bh=SZ65yBZC7lEGa0Ak3OsvShyUfq6wluR5gsaWqbe1c/Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c+d3JVqRFLTcr+GcqArPycExsPnuBk7OOd/FD14wcF/IffTcuAtRVm9C3zk9knRDX es4eAOokPlSO0PwB8ptjiy3Y6+oxDrruSPXISGnuSc534SCANX5XMgsArmNOXG87Js 3pQCWtAirCdnnuZHagDl3dEuOH5DMbNtpeeFsm2otXRrYl9te1ES4zD9LL5KPc1EvE HeBTmVMsvcmfiIu5zQlJW3wOgBJTakB26RwvEXNzMNm5zOpR8m3XukYahMD3dG4AL9 XYF8G9CMC+puk3/XZTAqNsR1smmwQndbF3FYRDJAVlIA1DL6+6wqyGIHQCP6AYeD6M e0RNSa2ubPTQA== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 3/9] soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC Date: Mon, 1 Sep 2025 12:04:15 +0100 Message-ID: <20250901-contempt-smelting-04aa3b08e112@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4881; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=bgb+aKhoXPSoMWSoLjwng00La7ffwhWTF00zqjwBdl8=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9fO7gh3ddph23c3TfhF/LMFdlOnRJ/9HtMfKXfmQ 6eH/H2ujlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzkfzMjw6mlej66P6O5vr59 MUexuur+synHfecu8biXvJNtkdNj3euMDKfzpZj5JictKlt3JN3k4ce8fwk3lDUi2cQtDj+6evp hGhsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The control-scb and mss-top-sysreg regions on PolarFire SoC both fulfill multiple purposes. The former is used for mailbox functions in addition to the temperature & voltage sensor while the latter is used for clocks, resets, interrupt muxing and pinctrl. Signed-off-by: Conor Dooley --- drivers/soc/microchip/Kconfig | 13 ++++++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-control-scb.c | 45 +++++++++++++++++++ drivers/soc/microchip/mpfs-mss-top-sysreg.c | 48 +++++++++++++++++++++ 4 files changed, 107 insertions(+) create mode 100644 drivers/soc/microchip/mpfs-control-scb.c create mode 100644 drivers/soc/microchip/mpfs-mss-top-sysreg.c diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig index 19f4b576f822b..31d188311e05f 100644 --- a/drivers/soc/microchip/Kconfig +++ b/drivers/soc/microchip/Kconfig @@ -9,3 +9,16 @@ config POLARFIRE_SOC_SYS_CTRL module will be called mpfs_system_controller. =20 If unsure, say N. + +config POLARFIRE_SOC_SYSCONS + bool "PolarFire SoC (MPFS) syscon drivers" + default y + depends on ARCH_MICROCHIP + select MFD_CORE + help + These drivers add support for the syscons on PolarFire SoC (MPFS). + Without these drivers core parts of the kernel such as clocks + and resets will not function correctly. + + If unsure, and on a PolarFire SoC, say y. + diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile index 14489919fe4b3..1a3a1594b089b 100644 --- a/drivers/soc/microchip/Makefile +++ b/drivers/soc/microchip/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) +=3D mpfs-sys-controller.o +obj-$(CONFIG_POLARFIRE_SOC_SYSCONS) +=3D mpfs-control-scb.o mpfs-mss-top-s= ysreg.o diff --git a/drivers/soc/microchip/mpfs-control-scb.c b/drivers/soc/microch= ip/mpfs-control-scb.c new file mode 100644 index 0000000000000..d1a8e79c232e3 --- /dev/null +++ b/drivers/soc/microchip/mpfs-control-scb.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_control_scb_devs[] =3D { + { .name =3D "mpfs-tvs", }, +}; + +static int mpfs_control_scb_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_control_scb_devs, + 1, NULL, 0, NULL); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id mpfs_control_scb_of_match[] =3D { + {.compatible =3D "microchip,mpfs-control-scb", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_control_scb_of_match); + +static struct platform_driver mpfs_control_scb_driver =3D { + .driver =3D { + .name =3D "mpfs-control-scb", + .of_match_table =3D mpfs_control_scb_of_match, + }, + .probe =3D mpfs_control_scb_probe, +}; +module_platform_driver(mpfs_control_scb_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC control scb driver"); diff --git a/drivers/soc/microchip/mpfs-mss-top-sysreg.c b/drivers/soc/micr= ochip/mpfs-mss-top-sysreg.c new file mode 100644 index 0000000000000..9b2e7b84cdba2 --- /dev/null +++ b/drivers/soc/microchip/mpfs-mss-top-sysreg.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_mss_top_sysreg_devs[] =3D { + { .name =3D "mpfs-reset", }, +}; + +static int mpfs_mss_top_sysreg_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_mss_top_sysreg_dev= s, + 1, NULL, 0, NULL); + if (ret) + return ret; + + if (devm_of_platform_populate(dev)) + dev_err(dev, "Error populating children\n"); + + return 0; +} + +static const struct of_device_id mpfs_mss_top_sysreg_of_match[] =3D { + {.compatible =3D "microchip,mpfs-mss-top-sysreg", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_mss_top_sysreg_of_match); + +static struct platform_driver mpfs_mss_top_sysreg_driver =3D { + .driver =3D { + .name =3D "mpfs-mss-top-sysreg", + .of_match_table =3D mpfs_mss_top_sysreg_of_match, + }, + .probe =3D mpfs_mss_top_sysreg_probe, +}; +module_platform_driver(mpfs_mss_top_sysreg_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC mss top sysreg driver"); --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 081DF31159A; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XMaE/q/F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1719CC4CEF8; Mon, 1 Sep 2025 11:05:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724711; bh=2TROKAVh+O1Dt05QQyh+Gi2OcE+j9CQLOVzFASPew6o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XMaE/q/FTisawWhSfXD9A/NfKqja2SmeFmtWkiAaYy4reDbqWqQyztrksGzJ1TNad O3PKf0Qo8FXYTR+Jah26jdMqRsgfX97duCl5/VshAavjEqSocjXxAsQPKfmT2v6hF8 cYrKMqE60vZTBDxAFY9fKdUJoEgS2fjNs1y5jrqnjC5tArVaTLyoIcUpFUp6uF/lDa vFrYLSQLtgozah0XilXx7atYA4n/Tqar8RQrVXNu6/9X5TpA/A+lbZXy7kjmd0qV8r eZxA4OVJx5onktNkZ3gShyYU3Q1L00/XZZvZFg1S/wSmeVsSFci2/KGczILUbdFVnk YDNQP1MHl2EbA== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 4/9] reset: mpfs: add non-auxiliary bus probing Date: Mon, 1 Sep 2025 12:04:16 +0100 Message-ID: <20250901-caption-outsell-d1824ab2485a@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6172; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=xTyhNLzqsskF0DCdmb70oYI71HAtmBHlflGuQWs66HQ=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9dquM9Vib+ZGMoqzRjXrX5azOlZWoyReptC/utfO qcWbN/TUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIlMOM3w3+nfh2MHz7Pcmpl7 xNLC6png3I+V4l0yitZM6z6EaHkuKmdk+Jo4v+GXAu+KfRdKGRY8kfoh0zSpxOdRLPO+c0/u/9n syAEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from an mfd devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley --- v4: - Only use driver specific lock for non-regmap writes v2: - Implement the request to use regmap_update_bits(). I found that I then hated the read/write helpers since they were just bloat, so I ripped them out. I replaced the regular spin_lock_irqsave() stuff with a guard(spinlock_irqsave), since that's a simpler way of handling the two different paths through such a trivial pair of functions. --- drivers/reset/reset-mpfs.c | 83 ++++++++++++++++++++++++++++++-------- 1 file changed, 66 insertions(+), 17 deletions(-) diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index f6fa10e03ea88..8e5ed4deecf37 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -7,13 +7,16 @@ * */ #include +#include #include #include +#include #include #include #include -#include +#include #include +#include #include #include =20 @@ -27,11 +30,14 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 +#define REG_SUBBLK_RESET_CR 0x88u + /* block concurrent access to the soft reset register */ static DEFINE_SPINLOCK(mpfs_reset_lock); =20 struct mpfs_reset { void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 @@ -46,41 +52,50 @@ static inline struct mpfs_reset *to_mpfs_reset(struct r= eset_controller_dev *rcde static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) { + regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), BIT(id)); + return 0; + } + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg |=3D BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + if (rst->regmap) { + regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), 0); + return 0; + } + + guard(spinlock_irqsave)(&mpfs_reset_lock); =20 reg =3D readl(rst->base); reg &=3D ~BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - u32 reg =3D readl(rst->base); + u32 reg; + + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); + else + reg =3D readl(rst->base); =20 /* * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit @@ -130,11 +145,45 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_mfd_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D pdev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + rst->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rst->regmap)) + dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n= "); + + return devm_reset_controller_register(dev, rcdev); +} + +static struct platform_driver mpfs_reset_mfd_driver =3D { + .probe =3D mpfs_reset_mfd_probe, + .driver =3D { + .name =3D "mpfs-reset", + }, +}; +module_platform_driver(mpfs_reset_mfd_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); @@ -145,8 +194,8 @@ static int mpfs_reset_probe(struct auxiliary_device *ad= ev, =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -176,12 +225,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB0B831159A; Mon, 1 Sep 2025 11:05:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724718; cv=none; b=KeegR+pcV9iLxdv++YozCyWJavLr1G7J7BWUf44piTxk0EevXMkFHwtxI4CS0eTeY6bkrj3UwcYPTOvYOyg8tc6aHyW/ybcslGZR4QnWTKZeW0kC+sxlKNYTE3D7KAuPDzwdGy4uJYbBR1Xz9xvBUS9RJZUq1GVTuRfJP40+EAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724718; c=relaxed/simple; bh=fQK9+TNjOMxzSGZmUzRv58YbqcykvxbEivMK+1aMTn0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GdxHhMQebVeA8Mjb7moEdE6tjnnW1KucF9pgHj2Gwtkg+XHiv1VHpTxlc5LVtEMk2FjGov/Br5w0PhdGahFTavAwAyKzyHhY3TX9MwGnUkVZ5xa8jEupcGWavM3WT8GXmuHypkFtt1uUil7al3CoEdlyyPaJKq9ufDD1d9lS0NI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=efgIlOcA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="efgIlOcA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA8F0C4CEF4; Mon, 1 Sep 2025 11:05:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724715; bh=fQK9+TNjOMxzSGZmUzRv58YbqcykvxbEivMK+1aMTn0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=efgIlOcAI2kQOApbNt+qj1Jyf/++Vs+a1C1c4TpD/3JwgkW0e66UnxmhtmkW4Xv4r 8Cy+aBiWGg3flujNmmEJmFSw+VaAyvI1jNH5xT61K3+rJ0s7n/mthq+4V1yziulHpV G3gwbhhlLdVS/39WRhOWcDIFdm6hBUqEPeYnmlHkPgUY7h+ocqHaf7WHNhOisf83rM EUVqMf26lYscHxGuUYpm1tLXDcPHADNam7KBHmdJfRvMYAPDLSq8ypvtUEpapWiGoD KUdrXBHEdXsdDdb5Qs5jaWgtszZyYJpbiNWqwg4FPrVHGMboidxybGP8Ls97ayZW1d t7Q2KPVcINQyQ== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 5/9] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Mon, 1 Sep 2025 12:04:17 +0100 Message-ID: <20250901-properly-banister-ccf27886c8e6@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3161; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=TTW8V6IURt0fNsC7kk6IUVDimqCXtE9Vfhk8Glza/xk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9ex+L08wxr2YGfkncVTAi0qzyT//jbp7zfmvZ/uJ 0zW+mjW0VHKwiDGxSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ1H9mZNi9/5B1//PXk7Tn zmqqmaESb1zmYs0147OXsks07/p8vycM/8ylMv7O/VL/vdvNd3PGkY5Tm2a6VMgc0px1t1lGhbN pMRMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2a..ee4f31596d978 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg =20 reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, = cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and r= eset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of th= e mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for t= he, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable a= nd reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll =20 clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - clkcfg: clock-controller@20002000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + clkcfg: clock-controller@3E001000 { compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0= x1000>; + reg =3D <0x3E001000 0x1000>; clocks =3D <&ref>; #clock-cells =3D <1>; }; --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68D0830F549; Mon, 1 Sep 2025 11:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724719; cv=none; b=W0c2z88S5ZtWwVXd9Omhd4YYQ7U/+Z3zqKzvTpIl0y/dQ2ZDZFjXyrF4xCRQmBAxUnTT17CWgmGtaRt9j2OtX/m0r6xzCXyLUMo75MDr0pprsPf7QW7J7PtaDEZ6SCL+hlpNTrGEHu7YbgClSb/64rSzPFXX7+KsC8GzF8a48VA= ARC-Message-Signature: i=1; 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b=uGScmK/6FpuRVuYSYAd6H6szvYlh2nSs0IA7N+Ncc2fnGUMVkEdTtVjENWPfVGVRS 4qbLR+Le8ZEveB/z70SfVlv9Yy0Ri3HX3v/FAuPFsQKUyKbspxbcwt1hHe0dsQxzq9 nyz8hVihxaZY8TgqG+tttHlyK36S1rHzb4a/dGiMZ3gH593Rqbg2F8sxYf2ULaVMoO 1t6OwdWVto3F1hHV5LyAWyR5Ret/9C7vEmUwsXDeuDcbPIpVhgSxmRPlllrs7uwiph /Z39zX0vrH8NDBqPVMo4SJ8fBNTzQfA9ps1lMcJC7qOVMpRHpYoj1eBCrB7CkeZNtp mBETgy49T7S9A== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 6/9] riscv: dts: microchip: fix mailbox description Date: Mon, 1 Sep 2025 12:04:18 +0100 Message-ID: <20250901-excretion-employed-1e497728e00e@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2050; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=s6ZIEUHnNiMIErq0YtoV3qkwNiLtaSKSNvr8gxSu+hU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9edPD9/Mc+5Kx3zlG/fMfXzPBt6qU8g3awxVilSn HmzQ3FuRykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbiVsfwz/LLfq+Yu9djX4u+ SnzXcbyTXUbauqfk1ze/N/mNDctmzGRk6K3bf/KKB/9OX6cDb0WUms8++7Yqw1br5pOY6QGMjrK rGQE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9883ca3554c50..f9d6bf08e7170 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 { #reset-cells =3D <1>; }; =20 + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,mpfs-sysreg-scb", "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible =3D "microchip,mpfs-ccc"; reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +526,14 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon"; + reg =3D <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x0 0x37020800 0x0 0x1000>; interrupt-parent =3D <&plic>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CFDC313551; Mon, 1 Sep 2025 11:05:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724723; cv=none; b=f7uRzf/58F9Pwj1LDQNEqeTEDoXbSXMmXgsjOzBHY7vvrOFJ+yL6HnGTDpKV5htNNzVi7YcioPKeu1dzmAGkJ71dROW8FLo2NKJukfDienHU9xH6k0yEvco++3altRYwh+FTF4GHv2nJ8Xx4rMAei31ftnk/3M/v4kCfGpYdyvw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724723; c=relaxed/simple; bh=/bWgOgtt0HzeQRBAs3E1w5tDhjdTqd+bV+sPH7F9rBw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rkzyrWgSZc2x5geVfXeDo4tRCPgG85ztnT4hgA4jn7auKWtAQcUj9X7iPT/uczh62q9HqW3BKpNzGr2UcXtQ3c0uNs+aJNq2rmnm+vcqf2YAAjdBsN8k0Dyz4oSFm5NSoFu62iamZlXDqzLUShNRGTFcv7WywrL1ZUNz6zYayjs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eK5Y+H+t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eK5Y+H+t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA85EC4CEF0; Mon, 1 Sep 2025 11:05:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724723; bh=/bWgOgtt0HzeQRBAs3E1w5tDhjdTqd+bV+sPH7F9rBw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eK5Y+H+t1oKMS8lkhYn362IaCBVBAXW1KwIgY0NxRWD/xGfSo3RxuAkHIoRDf6QSm kG3aSPJyIddFeOUkHGdkGXio3b/BGONbeCbVfcjhBepDDQobEsnPg3++184bj9tB4D naR5BrZH+g5vsaioPx3gj07qi/2UeNlXVxvlmF4FDSRX91VB+G44fdyB4FZO3av5Z9 E7WuFwGuz43WTLtjL7tsbp+UVXMyY5CYsEy12fHpQgA7lgoRGvz+YIpN4a/jbVuscu gfmqgTtKmtiYJFgaJ1g3FwLfle7jObCrao37JhApuh1u3yiiBQYQ938+0Wa8mtnFNh pDAu8YRt0R7aA== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 7/9] riscv: dts: microchip: convert clock and reset to use syscon Date: Mon, 1 Sep 2025 12:04:19 +0100 Message-ID: <20250901-famine-turf-deaa34bba81c@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2218; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=N5M81SbyiMqeqad2gOqNt4lbslX9WNFs88VS2tWTGE4=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9eZHj6bnvZS9rhEr1gMx7P8xZ83md5S4IvcsXR6i 6tQbHlNRykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACZyr5zhf8inLLtloRN052jO jDT4Ou36KcYGO5b5l/bta3/0e7LUpwWMDM3HxdZ/NigX+Pq5n9uzQH+6x78+uc0/r53myEyzMDU JZgAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index f9d6bf08e7170..5c2963e269b83 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; #reset-cells =3D <1>; }; =20 @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&mss_top_sysreg CLK_MAC0>; status =3D "disabled"; }; =20 @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&mss_top_sysreg CLK_MAC1>; status =3D "disabled"; }; =20 @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54D6311C2E; Mon, 1 Sep 2025 11:05:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 1 Sep 2025 11:05:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724727; bh=hltaoT0wHq0zJriPTv7PTiClhkzuYwM2fBILZAlFmOs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aD+5LdoM1vve65IH5c/dywswPevCwan9JhyDcWvUx3TWvN1j4Ntwx6hYSgTnhhdaG NXfvLvDEWpD2i4w/NMK0y66V+xMpQRxSpEL4MJ43Ey1efPlSxc5Wv1V5Kou+ugVVzE t23FZvWtGoIqNI27bVUyxd1q6XPmggRPuX1dHLzDDIyJzwAb5CeZvs7G5HPay8oLeI j/MyATL5RR5RHJlZZ2kpTW0FWFTWqcezvQfc9QUfy02bwgxoPFONyGr+paazcncUdc T8iDRtCdSQIuR2Z2/p504UOgANVr/PK8A5pJe52Cg3K6AtzRD0ZntPgl7nHSyoX9s3 Tv9aP9KnsqP6Q== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 8/9] clk: divider, gate: create regmap-backed copies of gate and divider clocks Date: Mon, 1 Sep 2025 12:04:20 +0100 Message-ID: <20250901-yearling-reconcile-99d06fe7868e@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=22552; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=jp0d/OaS25+xc66p1eI+T/kHwdJaF8ouagpJQ63N2gs=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9cxGHdVqWu3OTiqR36U91se4vq7J+ZUxfW/F3zE2 ZI6xO93lLIwiHExyIopsiTe7muRWv/HZYdzz1uYOaxMYEO4OAVgIku+M/yvdauW9a7+EiAk9P3u dEavZlmTvT4R62M/2Z+vOxgT/+gII8O+6X95RTKPl66bo9j5WcOkzZ3XZseXnEY3/xgzqZXH+Fg A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Implement regmap-backed copies of gate and divider clocks by replacing the iomem pointer to the clock registers with a regmap and offset within. Signed-off-by: Conor Dooley Reviewed-by: Gabriel Fernandez --- v4: - increase map_offset to a u32 - use a single Kconfig option for both divider and gate regmap implementations --- drivers/clk/Kconfig | 4 + drivers/clk/Makefile | 2 + drivers/clk/clk-divider-regmap.c | 271 +++++++++++++++++++++++++++++++ drivers/clk/clk-gate-regmap.c | 254 +++++++++++++++++++++++++++++ include/linux/clk-provider.h | 119 ++++++++++++++ 5 files changed, 650 insertions(+) create mode 100644 drivers/clk/clk-divider-regmap.c create mode 100644 drivers/clk/clk-gate-regmap.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4d56475f94fc1..3490b6fe6b9b2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -33,6 +33,10 @@ menuconfig COMMON_CLK =20 if COMMON_CLK =20 +config COMMON_CLK_REGMAP + bool + select REGMAP + config COMMON_CLK_WM831X tristate "Clock driver for WM831x/2x PMICs" depends on MFD_WM831X diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 18ed29cfdc113..b93b9e3e5fc07 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,11 +21,13 @@ clk-test-y :=3D clk_test.o \ kunit_clk_hw_get_dev_of_node.dtbo.o \ kunit_clk_parent_data_test.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-divider.o +obj-$(CONFIG_COMMON_CLK_REGMAP) +=3D clk-divider-regmap.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-rate.o obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) +=3D clk-fixed-rate-test.o clk-fixed-rate-test-y :=3D clk-fixed-rate_test.o kunit_clk_fixed_rate_tes= t.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-gate.o +obj-$(CONFIG_COMMON_CLK_REGMAP) +=3D clk-gate-regmap.o obj-$(CONFIG_CLK_GATE_KUNIT_TEST) +=3D clk-gate_test.o obj-$(CONFIG_COMMON_CLK) +=3D clk-multiplier.o obj-$(CONFIG_COMMON_CLK) +=3D clk-mux.o diff --git a/drivers/clk/clk-divider-regmap.c b/drivers/clk/clk-divider-reg= map.c new file mode 100644 index 0000000000000..e2f9489ad9ef9 --- /dev/null +++ b/drivers/clk/clk-divider-regmap.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include + +static inline u32 clk_div_regmap_readl(struct clk_divider_regmap *divider) +{ + u32 val; + + regmap_read(divider->regmap, divider->map_offset, &val); + + return val; +} + +static inline void clk_div_regmap_writel(struct clk_divider_regmap *divide= r, u32 val) +{ + regmap_write(divider->regmap, divider->map_offset, val); + +} + +static unsigned long clk_divider_regmap_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + unsigned int val; + + val =3D clk_div_regmap_readl(divider) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static long clk_divider_regmap_round_rate(struct clk_hw *hw, unsigned long= rate, + unsigned long *prate) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + val =3D clk_div_regmap_readl(divider) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_ro_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags, + val); + } + + return divider_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags); +} + +static int clk_divider_regmap_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + val =3D clk_div_regmap_readl(divider) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_ro_determine_rate(hw, req, divider->table, + divider->width, + divider->flags, val); + } + + return divider_determine_rate(hw, req, divider->table, divider->width, + divider->flags); +} + +static int clk_divider_regmap_set_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + int value; + unsigned long flags =3D 0; + u32 val; + + value =3D divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + if (value < 0) + return value; + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val =3D clk_div_mask(divider->width) << (divider->shift + 16); + } else { + val =3D clk_div_regmap_readl(divider); + val &=3D ~(clk_div_mask(divider->width) << divider->shift); + } + val |=3D (u32)value << divider->shift; + clk_div_regmap_writel(divider, val); + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + + return 0; +} + +const struct clk_ops clk_divider_regmap_ops =3D { + .recalc_rate =3D clk_divider_regmap_recalc_rate, + .round_rate =3D clk_divider_regmap_round_rate, + .determine_rate =3D clk_divider_regmap_determine_rate, + .set_rate =3D clk_divider_regmap_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_regmap_ops); + +const struct clk_ops clk_divider_regmap_ro_ops =3D { + .recalc_rate =3D clk_divider_regmap_recalc_rate, + .round_rate =3D clk_divider_regmap_round_rate, + .determine_rate =3D clk_divider_regmap_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_regmap_ro_ops); + +struct clk_hw *__clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u32 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_divider_regmap *div; + struct clk_hw *hw; + struct clk_init_data init =3D {}; + int ret; + + if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { + if (width + shift > 16) { + pr_warn("divider value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the divider */ + div =3D kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) + init.ops =3D &clk_divider_regmap_ro_ops; + else + init.ops =3D &clk_divider_regmap_ops; + init.flags =3D flags; + init.parent_names =3D parent_name ? &parent_name : NULL; + init.parent_hws =3D parent_hw ? &parent_hw : NULL; + init.parent_data =3D parent_data; + if (parent_name || parent_hw || parent_data) + init.num_parents =3D 1; + else + init.num_parents =3D 0; + + /* struct clk_divider assignments */ + div->regmap =3D regmap; + div->map_offset =3D map_offset; + div->shift =3D shift; + div->width =3D width; + div->flags =3D clk_divider_flags; + div->lock =3D lock; + div->hw.init =3D &init; + div->table =3D table; + + /* register the clock */ + hw =3D &div->hw; + ret =3D clk_hw_register(dev, hw); + if (ret) { + kfree(div); + hw =3D ERR_PTR(ret); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__clk_hw_register_divider_regmap); + +struct clk *clk_register_divider_regmap_table(struct device *dev, const ch= ar *name, + const char *parent_name, unsigned long flags, + struct regmap *regmap, u32 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_hw *hw; + + hw =3D __clk_hw_register_divider_regmap(dev, NULL, name, parent_name, NU= LL, + NULL, flags, regmap, map_offset, + shift, width, clk_divider_flags, + table, lock); + if (IS_ERR(hw)) + return ERR_CAST(hw); + return hw->clk; +} +EXPORT_SYMBOL_GPL(clk_register_divider_regmap_table); + +void clk_unregister_divider_regmap(struct clk *clk) +{ + struct clk_divider_regmap *div; + struct clk_hw *hw; + + hw =3D __clk_get_hw(clk); + if (!hw) + return; + + div =3D to_clk_divider_regmap(hw); + + clk_unregister(clk); + kfree(div); +} +EXPORT_SYMBOL_GPL(clk_unregister_divider_regmap); + +/** + * clk_hw_unregister_divider_regmap - unregister a clk divider + * @hw: hardware-specific clock data to unregister + */ +void clk_hw_unregister_divider_regmap(struct clk_hw *hw) +{ + struct clk_divider_regmap *div; + + div =3D to_clk_divider_regmap(hw); + + clk_hw_unregister(hw); + kfree(div); +} +EXPORT_SYMBOL_GPL(clk_hw_unregister_divider_regmap); + +static void devm_clk_hw_release_divider_regmap(struct device *dev, void *r= es) +{ + clk_hw_unregister_divider_regmap(*(struct clk_hw **)res); +} + +struct clk_hw *__devm_clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u32 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_hw **ptr, *hw; + + ptr =3D devres_alloc(devm_clk_hw_release_divider_regmap, sizeof(*ptr), GF= P_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + hw =3D __clk_hw_register_divider_regmap(dev, np, name, parent_name, paren= t_hw, + parent_data, flags, regmap, map_offset, + shift, width, clk_divider_flags, table, + lock); + + if (!IS_ERR(hw)) { + *ptr =3D hw; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_divider_regmap); diff --git a/drivers/clk/clk-gate-regmap.c b/drivers/clk/clk-gate-regmap.c new file mode 100644 index 0000000000000..54105738909c7 --- /dev/null +++ b/drivers/clk/clk-gate-regmap.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: basic gatable clock which can gate and ungate its output + * + * Traits of this clock: + * prepare - clk_(un)prepare only ensures parent is (un)prepared + * enable - clk_enable and clk_disable are functional & control gating + * rate - inherits rate from parent. No clk_set_rate support + * parent - fixed parent. No clk_set_parent support + */ + +static inline u32 clk_gate_regmap_readl(struct clk_gate_regmap *gate) +{ + u32 val; + + regmap_read(gate->map, gate->map_offset, &val); + + return val; +} + +static inline void clk_gate_regmap_writel(struct clk_gate_regmap *gate, u3= 2 val) +{ + regmap_write(gate->map, gate->map_offset, val); + +} + +/* + * It works on following logic: + * + * For enabling clock, enable =3D 1 + * set2dis =3D 1 -> clear bit -> set =3D 0 + * set2dis =3D 0 -> set bit -> set =3D 1 + * + * For disabling clock, enable =3D 0 + * set2dis =3D 1 -> set bit -> set =3D 1 + * set2dis =3D 0 -> clear bit -> set =3D 0 + * + * So, result is always: enable xor set2dis. + */ +static void clk_gate_regmap_endisable(struct clk_hw *hw, int enable) +{ + struct clk_gate_regmap *gate =3D to_clk_gate_regmap(hw); + int set =3D gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + unsigned long flags; + u32 reg; + + set ^=3D enable; + + if (gate->lock) + spin_lock_irqsave(gate->lock, flags); + else + __acquire(gate->lock); + + if (gate->flags & CLK_GATE_HIWORD_MASK) { + reg =3D BIT(gate->bit_idx + 16); + if (set) + reg |=3D BIT(gate->bit_idx); + } else { + reg =3D clk_gate_regmap_readl(gate); + + if (set) + reg |=3D BIT(gate->bit_idx); + else + reg &=3D ~BIT(gate->bit_idx); + } + + clk_gate_regmap_writel(gate, reg); + + if (gate->lock) + spin_unlock_irqrestore(gate->lock, flags); + else + __release(gate->lock); +} + +static int clk_gate_regmap_enable(struct clk_hw *hw) +{ + clk_gate_regmap_endisable(hw, 1); + + return 0; +} + +static void clk_gate_regmap_disable(struct clk_hw *hw) +{ + clk_gate_regmap_endisable(hw, 0); +} + +int clk_gate_regmap_is_enabled(struct clk_hw *hw) +{ + u32 reg; + struct clk_gate_regmap *gate =3D to_clk_gate_regmap(hw); + + reg =3D clk_gate_regmap_readl(gate); + + /* if a set bit disables this clk, flip it before masking */ + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + reg ^=3D BIT(gate->bit_idx); + + reg &=3D BIT(gate->bit_idx); + + return reg ? 1 : 0; +} +EXPORT_SYMBOL_GPL(clk_gate_regmap_is_enabled); + +const struct clk_ops clk_gate_regmap_ops =3D { + .enable =3D clk_gate_regmap_enable, + .disable =3D clk_gate_regmap_disable, + .is_enabled =3D clk_gate_regmap_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_gate_regmap_ops); + +struct clk_hw *__clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + struct regmap *map, u32 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_gate_regmap *gate; + struct clk_hw *hw; + struct clk_init_data init =3D {}; + int ret =3D -EINVAL; + + if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { + if (bit_idx > 15) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the gate */ + gate =3D kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &clk_gate_regmap_ops; + init.flags =3D flags; + init.parent_names =3D parent_name ? &parent_name : NULL; + init.parent_hws =3D parent_hw ? &parent_hw : NULL; + init.parent_data =3D parent_data; + if (parent_name || parent_hw || parent_data) + init.num_parents =3D 1; + else + init.num_parents =3D 0; + + /* struct clk_gate_regmap assignments */ + gate->map =3D map; + gate->map_offset =3D map_offset; + gate->bit_idx =3D bit_idx; + gate->flags =3D clk_gate_flags; + gate->lock =3D lock; + gate->hw.init =3D &init; + + hw =3D &gate->hw; + if (dev || !np) + ret =3D clk_hw_register(dev, hw); + else if (np) + ret =3D of_clk_hw_register(np, hw); + if (ret) { + kfree(gate); + hw =3D ERR_PTR(ret); + } + + return hw; + +} +EXPORT_SYMBOL_GPL(__clk_hw_register_gate_regmap); + +struct clk *clk_register_gate_regmap(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, struct regmap *map, + u32 map_offset, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_hw *hw; + + hw =3D __clk_hw_register_gate_regmap(dev, NULL, name, parent_name, NULL, + NULL, flags, map, map_offset, bit_idx, + clk_gate_flags, lock); + if (IS_ERR(hw)) + return ERR_CAST(hw); + return hw->clk; +} +EXPORT_SYMBOL_GPL(clk_register_gate_regmap); + +void clk_unregister_gate_regmap(struct clk *clk) +{ + struct clk_gate_regmap *gate; + struct clk_hw *hw; + + hw =3D __clk_get_hw(clk); + if (!hw) + return; + + gate =3D to_clk_gate_regmap(hw); + + clk_unregister(clk); + kfree(gate); +} +EXPORT_SYMBOL_GPL(clk_unregister_gate_regmap); + +void clk_hw_unregister_gate_regmap(struct clk_hw *hw) +{ + struct clk_gate_regmap *gate; + + gate =3D to_clk_gate_regmap(hw); + + clk_hw_unregister(hw); + kfree(gate); +} +EXPORT_SYMBOL_GPL(clk_hw_unregister_gate_regmap); + +static void devm_clk_hw_release_gate_regmap(struct device *dev, void *res) +{ + clk_hw_unregister_gate_regmap(*(struct clk_hw **)res); +} + +struct clk_hw *__devm_clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, struct regmap *map, + u32 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_hw **ptr, *hw; + + ptr =3D devres_alloc(devm_clk_hw_release_gate_regmap, sizeof(*ptr), GFP_K= ERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + hw =3D __clk_hw_register_gate_regmap(dev, np, name, parent_name, parent_h= w, + parent_data, flags, map, map_offset, + bit_idx, clk_gate_flags, lock); + + if (!IS_ERR(hw)) { + *ptr =3D hw; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate_regmap); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 630705a471294..0d9ef5c8bf960 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -8,6 +8,7 @@ =20 #include #include +#include =20 /* * flags used across common struct clk. these flags should only affect the @@ -538,6 +539,37 @@ struct clk_gate { #define CLK_GATE_BIG_ENDIAN BIT(2) =20 extern const struct clk_ops clk_gate_ops; + +#ifdef CONFIG_COMMON_CLK_REGMAP +/** + * struct clk_gate_regmap - gating clock via regmap + * + * @hw: handle between common and hardware-specific interfaces + * @map: regmap controlling gate + * @map_offset: register offset within the regmap controlling gate + * @bit_idx: single bit controlling gate + * @flags: hardware-specific flags + * @lock: register lock + * + * Clock which can gate its output. Implements .enable & .disable + * + * Flags: + * See clk_gate + */ +struct clk_gate_regmap { + struct clk_hw hw; + struct regmap *map; + u32 map_offset; + u8 bit_idx; + u8 flags; + spinlock_t *lock; +}; + +#define to_clk_gate_regmap(_hw) container_of(_hw, struct clk_gate_regmap, = hw) + +extern const struct clk_ops clk_gate_regmap_ops; +#endif + struct clk_hw *__clk_hw_register_gate(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, @@ -663,6 +695,31 @@ void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); =20 +#ifdef CONFIG_COMMON_CLK_REGMAP +struct clk_hw *__clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + struct regmap *map, u32 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); +struct clk_hw *__devm_clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + struct regmap *map, u32 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); +struct clk *clk_register_gate_regmap(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + struct regmap *map, u32 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); + +void clk_unregister_gate_regmap(struct clk *clk); +void clk_hw_unregister_gate_regmap(struct clk_hw *hw); +int clk_gate_regmap_is_enabled(struct clk_hw *hw); +#endif + struct clk_div_table { unsigned int val; unsigned int div; @@ -736,6 +793,41 @@ struct clk_divider { extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; =20 +#ifdef CONFIG_COMMON_CLK_REGMAP +/** + * struct clk_divider_regmap - adjustable divider clock via regmap + * + * @hw: handle between common and hardware-specific interfaces + * @map: regmap containing the divider + * @map_offset: register offset within the regmap containing the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @table: array of value/divider pairs, last entry should have div =3D 0 + * @lock: register lock + * + * Clock with an adjustable divider affecting its output frequency. Imple= ments + * .recalc_rate, .set_rate and .round_rate + * + * @flags: + * See clk_divider + */ +struct clk_divider_regmap { + struct clk_hw hw; + struct regmap *regmap; + u32 map_offset; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; + spinlock_t *lock; +}; + +#define to_clk_divider_regmap(_hw) container_of(_hw, struct clk_divider_re= gmap, hw) + +extern const struct clk_ops clk_divider_regmap_ops; +extern const struct clk_ops clk_divider_regmap_ro_ops; +#endif + unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_= rate, unsigned int val, const struct clk_div_table *table, unsigned long flags, unsigned long width); @@ -972,6 +1064,33 @@ struct clk *clk_register_divider_table(struct device = *dev, const char *name, void clk_unregister_divider(struct clk *clk); void clk_hw_unregister_divider(struct clk_hw *hw); =20 +#ifdef CONFIG_COMMON_CLK_REGMAP +struct clk_hw *__clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u32 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); + +struct clk_hw *__devm_clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u32 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); + +struct clk *clk_register_divider_regmap_table(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *regmap, u32 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); + +void clk_unregister_divider_regmap(struct clk *clk); +void clk_hw_unregister_divider_regmap(struct clk_hw *hw); +#endif + /** * struct clk_mux - multiplexer clock * --=20 2.47.2 From nobody Sun Dec 14 07:59:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D108311C35; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WDain+GJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6AAB5C4CEF4; Mon, 1 Sep 2025 11:05:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724730; bh=HrI7jlnnPgcTQ8EFovqHABHWUVM0AiXHJCDj0x1/d0c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WDain+GJsLHIWLqaWLpD7Er34lV33PKPhRkXcL9lh8qg063wxXLjlybC9l+OO2Oie FDNjZ/AMbnDUnB+Wjjcec6yBpxvgkwFfXOGzHL3nyhLoo1LPej1IMrZaAT7h5WU6rO KLfE8vCM5B3VOeQlIJYCPQoIUGmPZOXlXAkMazpaMz3PndOfCvd/4Bz/HvzrwoWm7o cYmYRWcfbj+ZdrTxrE0elQiU4rR1GDdxBsGUaa9XIS2CQvdwrsGVZqLThj/S4atcIR By8kSJtuv/N247zdFdSLag7MHKTJ35rRHdHBKkXE7UGGFHltXyLRF00EW2AM4JQSRd 8z3dgFRjWalrg== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 9/9] clk: microchip: mpfs: use regmap clock types Date: Mon, 1 Sep 2025 12:04:21 +0100 Message-ID: <20250901-handful-cardinal-c988f42ac8d9@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9989; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=0M+Pbcg7JV32uK4PkGDNKNBis48Qjna+wJfnLP00JjM=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9efS38iUBgj9j8xiXGXkWP0AqNYeZMrPy7uXLK0c LbZdG2tjlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEykxY3hn5r5r9W8PUvu5xfy xK64YP8qa5/vB4c7LflrGs+zflf9H8LIsNd1goPoi5wdt9c9ehcZof9qMXsQ0zGpwpV9Rx84cG6 YxgQA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Convert the PolarFire SoC clock driver to use regmap clock types as a preparatory work for supporting the new binding for this device that will only provide the second of the two register regions, and will require the use of syscon regmap to access the "cfg" and "periph" clocks currently supported by the driver. Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 3 + drivers/clk/microchip/clk-mpfs.c | 151 ++++++++++++++++++++----------- 2 files changed, 100 insertions(+), 54 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 0724ce65898f3..72da1e0f437d9 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -7,6 +7,9 @@ config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST default ARCH_MICROCHIP_POLARFIRE + depends on MFD_SYSCON select AUXILIARY_BUS + select COMMON_CLK_REGMAP + select REGMAP_MMIO help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index c22632a7439c5..c7fec0fcbe379 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -6,8 +6,10 @@ */ #include #include +#include #include #include +#include #include #include =20 @@ -30,6 +32,14 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u =20 +static const struct regmap_config clk_mpfs_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D REG_SUBBLK_CLOCK_CR, +}; + /* * This clock ID is defined here, rather than the binding headers, as it i= s an * internal clock only, and therefore has no consumers in other peripheral @@ -39,6 +49,7 @@ =20 struct mpfs_clock_data { struct device *dev; + struct regmap *regmap; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -68,14 +79,12 @@ struct mpfs_msspll_out_hw_clock { #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_o= ut_hw_clock, hw) =20 struct mpfs_cfg_hw_clock { - struct clk_divider cfg; - struct clk_init_data init; + struct clk_divider_regmap divider; unsigned int id; - u32 reg_offset; }; =20 struct mpfs_periph_hw_clock { - struct clk_gate periph; + struct clk_gate_regmap gate; unsigned int id; }; =20 @@ -172,15 +181,15 @@ static int mpfs_clk_register_mssplls(struct device *d= ev, struct mpfs_msspll_hw_c * MSS PLL output clocks */ =20 -#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) = { \ - .id =3D _id, \ - .output.shift =3D _shift, \ - .output.width =3D _width, \ - .output.table =3D NULL, \ - .reg_offset =3D _offset, \ - .output.flags =3D _flags, \ - .output.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .output.lock =3D &mpfs_clk_lock, \ +#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) = { \ + .id =3D _id, \ + .output.shift =3D _shift, \ + .output.width =3D _width, \ + .output.table =3D NULL, \ + .reg_offset =3D _offset, \ + .output.flags =3D _flags, \ + .output.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_regmap_ops, = 0), \ + .output.lock =3D &mpfs_clk_lock, \ } =20 static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] =3D { @@ -220,15 +229,14 @@ static int mpfs_clk_register_msspll_outs(struct devic= e *dev, * "CFG" clocks */ =20 -#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ - .id =3D _id, \ - .cfg.shift =3D _shift, \ - .cfg.width =3D _width, \ - .cfg.table =3D _table, \ - .reg_offset =3D _offset, \ - .cfg.flags =3D _flags, \ - .cfg.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .cfg.lock =3D &mpfs_clk_lock, \ +#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ + .id =3D _id, \ + .divider.shift =3D _shift, \ + .divider.width =3D _width, \ + .divider.table =3D _table, \ + .divider.map_offset =3D _offset, \ + .divider.flags =3D _flags, \ + .divider.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_regmap_ops,= 0), \ } =20 #define CLK_CPU_OFFSET 0u @@ -245,13 +253,13 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { REG_CLOCK_CONFIG_CR), { .id =3D CLK_RTCREF, - .cfg.shift =3D 0, - .cfg.width =3D 12, - .cfg.table =3D mpfs_div_rtcref_table, - .reg_offset =3D REG_RTC_CLOCK_CR, - .cfg.flags =3D CLK_DIVIDER_ONE_BASED, - .cfg.hw.init =3D - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, = 0), + .divider.shift =3D 0, + .divider.width =3D 12, + .divider.table =3D mpfs_div_rtcref_table, + .divider.map_offset =3D REG_RTC_CLOCK_CR, + .divider.flags =3D CLK_DIVIDER_ONE_BASED, + .divider.hw.init =3D + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_regma= p_ops, 0), } }; =20 @@ -264,14 +272,14 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; - ret =3D devm_clk_hw_register(dev, &cfg_hw->cfg.hw); + cfg_hw->divider.regmap =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &cfg_hw->divider.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); =20 id =3D cfg_hw->id; - data->hw_data.hws[id] =3D &cfg_hw->cfg.hw; + data->hw_data.hws[id] =3D &cfg_hw->divider.hw; } =20 return 0; @@ -281,15 +289,14 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ =20 -#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .periph.bit_idx =3D _shift, \ - .periph.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ - _flags), \ - .periph.lock =3D &mpfs_clk_lock, \ +#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ + .id =3D _id, \ + .gate.map_offset =3D REG_SUBBLK_CLOCK_CR, \ + .gate.bit_idx =3D _shift, \ + .gate.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_regmap_ops, _f= lags), \ } =20 -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].divider.= hw) =20 /* * Critical clocks: @@ -346,19 +353,60 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; - ret =3D devm_clk_hw_register(dev, &periph_hw->periph.hw); + periph_hw->gate.map =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &periph_hw->gate.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); =20 id =3D periph_hws[i].id; - data->hw_data.hws[id] =3D &periph_hw->periph.hw; + data->hw_data.hws[id] =3D &periph_hw->gate.hw; } =20 return 0; } =20 +static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data, + struct platform_device *pdev) +{ + clk_data->regmap =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-m= ss-top-sysreg"); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + return 0; +} + +static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_da= ta, + struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + dev_warn(&pdev->dev, "falling back to old devicetree format"); + + clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->base)) + return PTR_ERR(clk_data->base); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + clk_data->regmap =3D devm_regmap_init_mmio(dev, clk_data->base, &clk_mpfs= _regmap_config); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + ret =3D mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_R= ESET_CR); + if (ret) + return ret; + + return 0; +} + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -374,13 +422,12 @@ static int mpfs_clk_probe(struct platform_device *pde= v) if (!clk_data) return -ENOMEM; =20 - clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(clk_data->base)) - return PTR_ERR(clk_data->base); - - clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(clk_data->msspll_base)) - return PTR_ERR(clk_data->msspll_base); + ret =3D mpfs_clk_syscon_probe(clk_data, pdev); + if (ret) { + ret =3D mpfs_clk_old_format_probe(clk_data, pdev); + if (ret) + return ret; + } =20 clk_data->hw_data.num =3D num_clks; clk_data->dev =3D dev; @@ -406,11 +453,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 - ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data= ->hw_data); - if (ret) - return ret; - - return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RE= SET_CR); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data-= >hw_data); } =20 static const struct of_device_id mpfs_clk_of_match_table[] =3D { --=20 2.47.2