From nobody Sat Oct 4 19:17:49 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4422E3375BE for ; Mon, 1 Sep 2025 12:42:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756730525; cv=none; b=JsSscDyhH3EuQCagoPtXmDpVxkAGgJSQ360Ela0vp6nF3tz192pRbrAdJwuUJAIGoWkv8scEHSkQ5ao9h8VWTlTSizVhrVWeQbPQF5e+RJEqRCjE1Lv5OTc28mk95XECmgehITqv/XF5TjwgS5hKKvHfjALrbIJjksMj9t6B5e4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756730525; c=relaxed/simple; bh=RVZayCp5OixCPVRZdJVQFNOqw4c7KtixASsd5Xntv6I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IBqJHWmjHHenh4r4rru/1we+NR5Ppv1gEvZ2xEtoGsnVk1Yz/pW01Ukb7S2Pk9Neew1X0HRXsUx9BLr0LLH+bqXJ01ybR5EHkw7ku2VHNgsEG6tRFh5LR0dKDAvn+6CEXFsVDjiFJYDCO7e8R3GW+xqRx1RZLfICKD9VpFPjsnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JGg6Dgzr; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JGg6Dgzr" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-45b89147cfbso12304015e9.3 for ; Mon, 01 Sep 2025 05:42:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756730521; x=1757335321; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0gYBkgwI12gbrT5fDRBP0jl2MaqA4H2/njWa7gROlbw=; b=JGg6Dgzr8QenlZQaXSCa3yYHRp2AaPCAzXqBuifGfnEnjcwuxnzCH2wtdJnGwRxMbT Jy/i0Qwc3wGpMuGnWpBIRbOblBHLie4crYsxwEotQEvryGXDMWmhzF/jJtUD+2k2d/RH tESdSYU6XNs5TJTMnmsVKT8pvQAiqXrXHqfnmrNAj8AlEzovL3/k1oS0tTuEJfJnMv4l cdB0FkV9XQcT+ngfFE93TWbyQcU1Srgcu7u0Cqgq5qnUzVLQkotc9EHrhmKiQW6Ea0k4 n7rvAbzM1oDqDZvE1j5UomXp8/hl/xULe53bRlLy07rePqAvhJZLbS2yvTUob3ackGlC CEPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756730521; x=1757335321; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0gYBkgwI12gbrT5fDRBP0jl2MaqA4H2/njWa7gROlbw=; b=Cxdkcf09C12FRRew+wcR97fsw61jSCiEmlxJhXuZehQ+KakC+OobH4Lwu7ouZBDoXR cwFSpMM1WBpP+h02xg013OV4UwejUYWGLY0Ua7VnXj4tVpVZwPGZs8rY++iD2oUe6j8C LgToQhz9+N1s3GUhSbwN7GtbWe3P8YsiswW18OszmfBJ17IXset10yv76j7MnkxQYwhM 5i0D7MkhhBkCiGKIKZa1f01YBhm+Txrny+uM7BMURxMakQJEopANKxj3PpNmt/dKCESO RcP7BeMeff/7TjhWGuDFWT5vwiujPL4oGnraL5jB3Obyh55liKiVkrgi+f9d8fhk5tVs a+tA== X-Forwarded-Encrypted: i=1; AJvYcCUwPVj0SDXco2BeTXQu/5KEKkQQheG61dpuI9a4KHAK/oILYBD45h+bSYJD31tD4mx6pN1vyUZBLNfy514=@vger.kernel.org X-Gm-Message-State: AOJu0YzbJrtHu6S8RyySk8Kb8IWELTI6pU/ZYOCjsLxyjBKsR/eZpZe0 dpPG6AtnQ6wT/uETBZuH84S/UOJ48ehZMufjVb/rZ9YQocD2CYj7btnsB9+19aiKrzc= X-Gm-Gg: ASbGncslRhmEMk7XoGi7I9gkR9bKvY1a9Mr68nPFDzUt1cs9nwU0fw2tmvfsKpJsukc TFR9p1TkQGQwMHAzVxnswPZ641xCPxeYXz3+x/Ni4ViusTYQdnhlXLQDeFFjZPgAw+KwKrGMIUC dwam0mKcBr5evpFvcJYeCoSABOBCE/E2zz/aHyr9if379yUJg25SuNDHa/oPzOZrelf0Zc5EGs8 Xf6BcEHZLoPjkrMwPHgdNI5MShNhtdRrLtiAVFtfrm+Jj6xJXeswKCBrdPMNjCZTvcmm+YMMB4A a0kr8wgzEBW2DyU5f4TBaaB3iBuLHLQH5l46zbpXmHyTGsEj03IAh9HVBqYQT+A3L1O9zP9KkDw HJ6+BUQ7NBw0GY3qKFbFZhTw8N9XTBGl3+KSCAk4fIA== X-Google-Smtp-Source: AGHT+IGtybtA43LzaX+nZGwbXW5Im33x1sTdapVn9uZpGYduxlJ52+DycNYLVsJKQ1mPUhW2aRJdHA== X-Received: by 2002:a05:600c:1d24:b0:45b:581c:ad0d with SMTP id 5b1f17b1804b1-45b85550679mr68872005e9.8.1756730521322; Mon, 01 Sep 2025 05:42:01 -0700 (PDT) Received: from ho-tower-lan.lan ([185.48.76.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b7e898b99sm154946315e9.19.2025.09.01.05.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Sep 2025 05:42:00 -0700 (PDT) From: James Clark Date: Mon, 01 Sep 2025 13:40:38 +0100 Subject: [PATCH v8 09/12] perf: arm_spe: Add support for filtering on data source Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250901-james-perf-feat_spe_eft-v8-9-2e2738f24559@linaro.org> References: <20250901-james-perf-feat_spe_eft-v8-0-2e2738f24559@linaro.org> In-Reply-To: <20250901-james-perf-feat_spe_eft-v8-0-2e2738f24559@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Leo Yan , Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 SPE_FEAT_FDS adds the ability to filter on the data source of packets. Like the other existing filters, enable filtering with PMSFCR_EL1.FDS when any of the filter bits are set. Each bit maps to data sources 0-63 described by bits[0:5] in the data source packet (although the full range of data source is 16 bits so higher value data sources can't be filtered on). The filter is an OR of all the bits, so for example clearing bits 0 and 3 only includes packets from data sources 0 OR 3. Invert the filter given by userspace so that the default value of 0 is equivalent to including all values (no filtering). This allows us to skip adding a new format bit to enable filtering and still support excluding all data sources which would have been a filter value of 0 if not for the inversion. Tested-by: Leo Yan Reviewed-by: Leo Yan Signed-off-by: James Clark --- drivers/perf/arm_spe_pmu.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 591f72fa0327..e5b36ab90786 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -87,6 +87,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DISCARD (1UL << 7) #define SPE_PMU_FEAT_EFT (1UL << 8) +#define SPE_PMU_FEAT_FDS (1UL << 9) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; =20 @@ -251,6 +252,10 @@ static const struct attribute_group arm_spe_pmu_cap_gr= oup =3D { #define ATTR_CFG_FLD_inv_event_filter_LO 0 #define ATTR_CFG_FLD_inv_event_filter_HI 63 =20 +#define ATTR_CFG_FLD_inv_data_src_filter_CFG config4 /* inverse of PMSDSFR= _EL1 */ +#define ATTR_CFG_FLD_inv_data_src_filter_LO 0 +#define ATTR_CFG_FLD_inv_data_src_filter_HI 63 + GEN_PMU_FORMAT_ATTR(ts_enable); GEN_PMU_FORMAT_ATTR(pa_enable); GEN_PMU_FORMAT_ATTR(pct_enable); @@ -267,6 +272,7 @@ GEN_PMU_FORMAT_ATTR(float_filter); GEN_PMU_FORMAT_ATTR(float_filter_mask); GEN_PMU_FORMAT_ATTR(event_filter); GEN_PMU_FORMAT_ATTR(inv_event_filter); +GEN_PMU_FORMAT_ATTR(inv_data_src_filter); GEN_PMU_FORMAT_ATTR(min_latency); GEN_PMU_FORMAT_ATTR(discard); =20 @@ -287,6 +293,7 @@ static struct attribute *arm_spe_pmu_formats_attr[] =3D= { &format_attr_float_filter_mask.attr, &format_attr_event_filter.attr, &format_attr_inv_event_filter.attr, + &format_attr_inv_data_src_filter.attr, &format_attr_min_latency.attr, &format_attr_discard.attr, NULL, @@ -305,6 +312,10 @@ static umode_t arm_spe_pmu_format_attr_is_visible(stru= ct kobject *kobj, if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) return 0; =20 + if (attr =3D=3D &format_attr_inv_data_src_filter.attr && + !(spe_pmu->features & SPE_PMU_FEAT_FDS)) + return 0; + if ((attr =3D=3D &format_attr_branch_filter_mask.attr || attr =3D=3D &format_attr_load_filter_mask.attr || attr =3D=3D &format_attr_store_filter_mask.attr || @@ -429,6 +440,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *e= vent) if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) reg |=3D PMSFCR_EL1_FnE; =20 + if (ATTR_CFG_GET_FLD(attr, inv_data_src_filter)) + reg |=3D PMSFCR_EL1_FDS; + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |=3D PMSFCR_EL1_FL; =20 @@ -453,6 +467,17 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event= *event) return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency= )); } =20 +static u64 arm_spe_event_to_pmsdsfr(struct perf_event *event) +{ + struct perf_event_attr *attr =3D &event->attr; + + /* + * Data src filter is inverted so that the default value of 0 is + * equivalent to no filtering. + */ + return ~ATTR_CFG_GET_FLD(attr, inv_data_src_filter); +} + static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) { struct arm_spe_pmu_buf *buf =3D perf_get_aux(handle); @@ -790,6 +815,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) if (arm_spe_event_to_pmsnevfr(event) & spe_pmu->pmsevfr_res0) return -EOPNOTSUPP; =20 + if (arm_spe_event_to_pmsdsfr(event) !=3D U64_MAX && + !(spe_pmu->features & SPE_PMU_FEAT_FDS)) + return -EOPNOTSUPP; + if (attr->exclude_idle) return -EOPNOTSUPP; =20 @@ -865,6 +894,11 @@ static void arm_spe_pmu_start(struct perf_event *event= , int flags) write_sysreg_s(reg, SYS_PMSNEVFR_EL1); } =20 + if (spe_pmu->features & SPE_PMU_FEAT_FDS) { + reg =3D arm_spe_event_to_pmsdsfr(event); + write_sysreg_s(reg, SYS_PMSDSFR_EL1); + } + reg =3D arm_spe_event_to_pmslatfr(event); write_sysreg_s(reg, SYS_PMSLATFR_EL1); =20 @@ -1124,6 +1158,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (FIELD_GET(PMSIDR_EL1_EFT, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_EFT; =20 + if (FIELD_GET(PMSIDR_EL1_FDS, reg)) + spe_pmu->features |=3D SPE_PMU_FEAT_FDS; + /* This field has a spaced out encoding, so just use a look-up */ fld =3D FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { --=20 2.34.1