From nobody Sun Dec 14 13:54:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CFDC313551; Mon, 1 Sep 2025 11:05:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724723; cv=none; b=f7uRzf/58F9Pwj1LDQNEqeTEDoXbSXMmXgsjOzBHY7vvrOFJ+yL6HnGTDpKV5htNNzVi7YcioPKeu1dzmAGkJ71dROW8FLo2NKJukfDienHU9xH6k0yEvco++3altRYwh+FTF4GHv2nJ8Xx4rMAei31ftnk/3M/v4kCfGpYdyvw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756724723; c=relaxed/simple; bh=/bWgOgtt0HzeQRBAs3E1w5tDhjdTqd+bV+sPH7F9rBw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rkzyrWgSZc2x5geVfXeDo4tRCPgG85ztnT4hgA4jn7auKWtAQcUj9X7iPT/uczh62q9HqW3BKpNzGr2UcXtQ3c0uNs+aJNq2rmnm+vcqf2YAAjdBsN8k0Dyz4oSFm5NSoFu62iamZlXDqzLUShNRGTFcv7WywrL1ZUNz6zYayjs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eK5Y+H+t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eK5Y+H+t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA85EC4CEF0; Mon, 1 Sep 2025 11:05:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756724723; bh=/bWgOgtt0HzeQRBAs3E1w5tDhjdTqd+bV+sPH7F9rBw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eK5Y+H+t1oKMS8lkhYn362IaCBVBAXW1KwIgY0NxRWD/xGfSo3RxuAkHIoRDf6QSm kG3aSPJyIddFeOUkHGdkGXio3b/BGONbeCbVfcjhBepDDQobEsnPg3++184bj9tB4D naR5BrZH+g5vsaioPx3gj07qi/2UeNlXVxvlmF4FDSRX91VB+G44fdyB4FZO3av5Z9 E7WuFwGuz43WTLtjL7tsbp+UVXMyY5CYsEy12fHpQgA7lgoRGvz+YIpN4a/jbVuscu gfmqgTtKmtiYJFgaJ1g3FwLfle7jObCrao37JhApuh1u3yiiBQYQ938+0Wa8mtnFNh pDAu8YRt0R7aA== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel FERNANDEZ Subject: [PATCH v4 7/9] riscv: dts: microchip: convert clock and reset to use syscon Date: Mon, 1 Sep 2025 12:04:19 +0100 Message-ID: <20250901-famine-turf-deaa34bba81c@spud> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250901-rigid-sacrifice-0039c6e6234e@spud> References: <20250901-rigid-sacrifice-0039c6e6234e@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2218; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=N5M81SbyiMqeqad2gOqNt4lbslX9WNFs88VS2tWTGE4=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBlba9eZHj6bnvZS9rhEr1gMx7P8xZ83md5S4IvcsXR6i 6tQbHlNRykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACZyr5zhf8inLLtloRN052jO jDT4Ou36KcYGO5b5l/bta3/0e7LUpwWMDM3HxdZ/NigX+Pq5n9uzQH+6x78+uc0/r53myEyzMDU JZgAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index f9d6bf08e7170..5c2963e269b83 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; #reset-cells =3D <1>; }; =20 @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&mss_top_sysreg CLK_MAC0>; status =3D "disabled"; }; =20 @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&mss_top_sysreg CLK_MAC1>; status =3D "disabled"; }; =20 @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.47.2