From nobody Fri Oct 3 13:32:16 2025 Received: from mail.netcube.li (mail.netcube.li [173.249.15.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08C62257828; Sun, 31 Aug 2025 16:26:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=173.249.15.149 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756657612; cv=none; b=oKFGMd6j5yPVzs18fO9HbUNSqRfAymOWKdDcvYYvuE1Xf8HT6MSeM5SZXXaSDusCVHqtEPaJKID0wegHNkzeLETDvmkURekScb0RePByfL1mTvir/jrOExzJOTWjzmQgHRBDTLCTk+dq8wwSKTmnV9AxlhxHiS3AKhEGKoW9w8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756657612; c=relaxed/simple; bh=cwSjbjBO6SYU1Ptj+td0gwtsSLd5BT7MQ5CmF96HWnY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NMVO4bMBC4pdStCGFo+s+yOptOpaFYZuWaE/2bZxiWJrFoQf9INout8BmhoPLsQ4cSqbBZZmVFoWis4Xu15voYddZe0Gq1mOu9vMFkXakct9QGClHmoz6kXCOa1LJwoQu7bqmZx06cmXFNbbl5sjAfozDAgj7qd10EhqiMGh+v4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=netcube.li; spf=pass smtp.mailfrom=netcube.li; dkim=pass (1024-bit key) header.d=netcube.li header.i=@netcube.li header.b=lDuKufd1; arc=none smtp.client-ip=173.249.15.149 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=netcube.li Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=netcube.li Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=netcube.li header.i=@netcube.li header.b="lDuKufd1" dkim-signature: v=1; a=rsa-sha256; d=netcube.li; s=s1; c=relaxed/relaxed; q=dns/txt; h=From:Subject:Date:Message-ID:To:CC:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References; bh=EtwHbiHCZ/Y1VDCe5yIgMYAjwsADjnQ7s3CSUt3glQ8=; b=lDuKufd1Dg1hozfjvX2mL3jWONjZJsZU28JIP4fcpMn4pAfQpko4u7ePXKvNnHYQcuViWemhL+4Na8jkxhdof9suGSzb8f3kVDU7V7Q5k17HZK9e3uG/emQnScqiV03Sx6tCp4CG2or/ogk0mwhWcQbjRs1oXMa3sk+f6YyLN4k= Received: from lukas-hpz440workstation.lan.sk100508.local (cm70-231.liwest.at [212.241.70.231]) by mail.netcube.li with ESMTPA ; Sun, 31 Aug 2025 18:26:44 +0200 From: Lukas Schmid To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Maxime Ripard Cc: Lukas Schmid , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v8 3/5] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM Date: Sun, 31 Aug 2025 18:25:32 +0200 Message-Id: <20250831162536.2380589-4-lukas.schmid@netcube.li> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250831162536.2380589-1-lukas.schmid@netcube.li> References: <20250831162536.2380589-1-lukas.schmid@netcube.li> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NetCube Systems Nagami SoM is a module based around the Allwinner T113s SoC. It includes the following features and interfaces: - 128MB DDR3 included in SoC - 10/100 Mbps Ethernet using LAN8720A phy - One USB-OTG interface - One USB-Host interface - One I2S interface with in and output support - Two CAN interfaces - ESP32 over SDIO - One SPI interface - I2C EEPROM for MAC address - One QWIIC I2C Interface with dedicated interrupt pin shared with EEPROM - One external I2C interface - SD interface for external SD-Card Signed-off-by: Lukas Schmid --- .../allwinner/sun8i-t113s-netcube-nagami.dtsi | 250 ++++++++++++++++++ 1 file changed, 250 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.= dtsi diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi b/= arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi new file mode 100644 index 0000000000000..4d3627f6d58d2 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s.dtsi" + +#include +#include + +/ { + model =3D "NetCube Systems Nagami SoM"; + compatible =3D "netcube,nagami", "allwinner,sun8i-t113s"; + + aliases { + serial1 =3D &uart1; // ESP32 Bootloader UART + serial3 =3D &uart3; // Console UART on Card Edge + ethernet0 =3D &emac; + }; + + chosen { + stdout-path =3D "serial3:115200n8"; + }; + + /* module wide 3.3V supply directly from the card edge */ + reg_vcc3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-core"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + vin-supply =3D <®_vcc3v3>; + }; + + /* USB0 MUX to switch connect to Card-Edge only after BootROM */ + usb0_sec_mux: mux-controller{ + compatible =3D "gpio-mux"; + #mux-control-cells =3D <0>; + mux-gpios =3D <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */ + idle-state =3D <1>; /* USB connected to Card-Edge by default */ + }; + + /* Reset of ESP32 */ + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pio 6 9 GPIO_ACTIVE_LOW>; /* PG9 */ + post-power-on-delay-ms =3D <1500>; + power-off-delay-us =3D <200>; + }; +}; + +&cpu0 { + cpu-supply =3D <®_vcc_core>; +}; + +&cpu1 { + cpu-supply =3D <®_vcc_core>; +}; + +&dcxo { + clock-frequency =3D <24000000>; +}; + +&emac { + nvmem-cells =3D <ð0_macaddress>; + nvmem-cell-names =3D "mac-address"; + phy-handle =3D <&lan8720a>; + phy-mode =3D "rmii"; + pinctrl-0 =3D <&rmii_pe_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* Default I2C Interface on Card-Edge */ +&i2c2 { + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-names =3D "default"; + status =3D "disabled"; +}; + +/* Exposed as the QWIIC connector and used by the internal EEPROM */ +&i2c3 { + pinctrl-0 =3D <&i2c3_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + eeprom0: eeprom@50 { + compatible =3D "atmel,24c02"; /* actually it's a 24AA02E48 */ + reg =3D <0x50>; + pagesize =3D <16>; + read-only; + vcc-supply =3D <®_vcc3v3>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + eth0_macaddress: macaddress@fa { + reg =3D <0xfa 0x06>; + }; + }; +}; + +/* Default I2S Interface on Card-Edge */ +&i2s1 { + pinctrl-0 =3D <&i2s1_pins>, <&i2s1_din_pins>, <&i2s1_dout_pins>; + pinctrl-names =3D "default"; + status =3D "disabled"; +}; + +/* Phy is on SoM. MDI signals pre-magentics are on the card edge */ +&mdio { + lan8720a: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + }; +}; + +/* Default SD Interface on Card-Edge */ +&mmc0 { + pinctrl-0 =3D <&mmc0_pins>; + pinctrl-names =3D "default"; + status =3D "disabled"; +}; + +/* Connected to the on-board ESP32 */ +&mmc1 { + pinctrl-0 =3D <&mmc1_pins>; + pinctrl-names =3D "default"; + vmmc-supply =3D <®_vcc3v3>; + bus-width =3D <4>; + non-removable; + mmc-pwrseq =3D <&wifi_pwrseq>; + status =3D "okay"; +}; + +/* Connected to the on-board eMMC */ +&mmc2 { + pinctrl-0 =3D <&mmc2_pins>; + pinctrl-names =3D "default"; + vmmc-supply =3D <®_vcc3v3>; + vqmmc-supply =3D <®_vcc3v3>; + bus-width =3D <4>; + non-removable; + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_vcc3v3>; + vcc-pc-supply =3D <®_vcc3v3>; + vcc-pd-supply =3D <®_vcc3v3>; + vcc-pe-supply =3D <®_vcc3v3>; + vcc-pf-supply =3D <®_vcc3v3>; + vcc-pg-supply =3D <®_vcc3v3>; + + gpio-line-names =3D "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "CAN0_TX", "CAN0_RX", // PB + "CAN1_TX", "CAN1_RX", "UART3_TX", "UART3_RX", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "eMMC_CLK", "eMMC_CMD", // PC + "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "USB_SEC_EN", "SPI1_CS", "SPI1_CLK", + "SPI1_MOSI", "SPI1_MISO", "SPI1_HOLD", "SPI1_WP", + "PD16", "", "", "", + "I2C2_SCL", "I2C2_SDA", "PD22", "", + "", "", "", "", + "", "", "", "", + "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE + "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "", + "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "SD_D1", "SD_D0", "SD_CLK", "SD_CLK", // PF + "SD_D3", "SD_D2", "PF6", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD", + "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA", + "I2S1_WS", "I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* Remove the unused CK pin from the pinctl as it is unconnected */ +&rmii_pe_pins { + pins =3D "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE8", "PE9"; +}; + +/* Default SPI Interface on Card-Edge */ +&spi1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&spi1_pins>, <&spi1_hold_pin>, <&spi1_wp_pin>; + pinctrl-names =3D "default"; + cs-gpios =3D <0>; + status =3D "disabled"; +}; + +/* Connected to the Bootloader/Console of the ESP32 */ +&uart1 { + pinctrl-0 =3D <&uart1_pg6_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* Console/Debug UART on Card-Edge */ +&uart3 { + pinctrl-0 =3D <&uart3_pb_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.39.5