From nobody Fri Oct 3 13:30:15 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 604EA45029; Sun, 31 Aug 2025 12:46:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756644397; cv=none; b=Ddg4HCx4+OOxg2sNR++bw7qSyq7mzXbY/3lTJ2vqEBp6Lj6/Wmt1wqYjPmf6FBNbpBupTj5J5DMDAyx1WxSY/RRLjd9WtfCSQqERYpLEEfeh+pjublfaEP1t3+3iwNnr5utiFAcyEtZGqmaTU4pvvJtICtc4WMTMM5KcdRDwPdE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756644397; c=relaxed/simple; bh=wtKe9H6U+LhS2f603AlELwNS+homIUhNUwT6Z3ZM8hU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KT75Bo32SAagUiSKNdQPh1IrnAKA+lv3zVShqgY7Co9eVSZu1oGtkQSVrHQK2oI3EHGY1jd51E/l6R6QURyOjXYfYRGVfw6EW2S/hYMlgvsGQsksMf9JjBX0oL4hSoq6jPoape5ucUPLSCmJGbHqYSSkaNPZzRlxNz21daMgReA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=ov45dU1p; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=CY413ftE; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="ov45dU1p"; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="CY413ftE" DKIM-Signature: v=1; a=rsa-sha256; s=202507r; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1756643370; bh=75jbWC6rzZi0qzMwWHXrcn6 GuZQp+Mi+3zTPjxiaEug=; b=ov45dU1pyTfipssKly3Wo6HbmoEqklclEB3vjkStFPKI58m3it QPsXzjObrVkcLwcTPvx9Dt8ZpN988GzeuDWt5BeW8pR2u4M49+5qfriEBYq1xmx0R/5QMmKBXUN joZGv864Z8/DUTevIQHGcN6eApnuwSi/SpPx79B7Hg5kOvLwlugCvivmIxAAVXN3Yw1bp18XPEK 16X8gQ+6ztoEbP83iQ2kEVi8Si5IhV80FxFj3Wpap3LEftWYB2Vrel7gkzNoxmAP7zxuVdYC8y+ yLcbRcscOkoWjSnKg1Q+kka74uSeoiLEmEE8NMsACoPy2Y/3PgRXMWJzwBPKsxJXOkw==; DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1756643370; bh=75jbWC6rzZi0qzMwWHXrcn6 GuZQp+Mi+3zTPjxiaEug=; b=CY413ftEpGdrGc2YR6hmicv9wenoD8tTx2JNk+uUbeD87xHQoq k+3tVuf8rj38idhohfVVs7VIZ71p6ssBpYDQ==; From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sun, 31 Aug 2025 14:29:24 +0200 Subject: [PATCH v8 1/7] dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250831-msm8937-v8-1-b7dcd63caaac@mainlining.org> References: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> In-Reply-To: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756643366; l=3026; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=wtKe9H6U+LhS2f603AlELwNS+homIUhNUwT6Z3ZM8hU=; b=92EZ3ek69QF+JXNJZCUMqPFNCG6oXM9SrVT2zRtD0aMPiUxLAZRvLj5NOikGsXngeEbqQ6BwU cYc1zpaEDA0Cvuij6vhSyCDbdNQoTYDaq9GH2mp/A6Oa2mDKZ+edRmN X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add device tree bindings for the global clock controller on Qualcomm MSM8937 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- .../devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 11 ++++++++--- include/dt-bindings/clock/qcom,gcc-msm8917.h | 19 +++++++++++++++= ++++ 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml = b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml index fe1f5f3ed992453a347062a556b1ddb2a011db6f..f2e37f439d28b3ec066f4079279= 55b3b82b5c10a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953 maintainers: - Adam Skladowski - Sireesh Kodali + - Barnabas Czeman =20 description: | Qualcomm global clock control module provides the clocks, resets and pow= er - domains on MSM8953. + domains on MSM8937 or MSM8953. =20 - See also: include/dt-bindings/clock/qcom,gcc-msm8953.h + See also:: + include/dt-bindings/clock/qcom,gcc-msm8917.h + include/dt-bindings/clock/qcom,gcc-msm8953.h =20 properties: compatible: - const: qcom,gcc-msm8953 + enum: + - qcom,gcc-msm8937 + - qcom,gcc-msm8953 =20 clocks: items: diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bind= ings/clock/qcom,gcc-msm8917.h index 4b421e7414b50bef2e2400f868ae5b7212a427bb..4e3897b3669d9149b61a6feec31= ca35e2058dcb9 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8917.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -170,6 +170,23 @@ #define VFE1_CLK_SRC 163 #define VSYNC_CLK_SRC 164 #define GPLL0_SLEEP_CLK_SRC 165 +/* Addtional MSM8937-specific clocks */ +#define MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC 166 +#define MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC 167 +#define MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC 168 +#define MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC 169 +#define MSM8937_BYTE1_CLK_SRC 170 +#define MSM8937_ESC1_CLK_SRC 171 +#define MSM8937_PCLK1_CLK_SRC 172 +#define MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK 173 +#define MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK 174 +#define MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK 175 +#define MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK 176 +#define MSM8937_GCC_MDSS_BYTE1_CLK 177 +#define MSM8937_GCC_MDSS_ESC1_CLK 178 +#define MSM8937_GCC_MDSS_PCLK1_CLK 179 +#define MSM8937_GCC_OXILI_AON_CLK 180 +#define MSM8937_GCC_OXILI_TIMER_CLK 181 =20 /* GCC block resets */ #define GCC_CAMSS_MICRO_BCR 0 @@ -187,5 +204,7 @@ #define VENUS_GDSC 5 #define VFE0_GDSC 6 #define VFE1_GDSC 7 +/* Additional MSM8937-specific GDSCs */ +#define MSM8937_OXILI_CX_GDSC 8 =20 #endif --=20 2.51.0 From nobody Fri Oct 3 13:30:15 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D49791E766E; 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DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1756643372; bh=Xsd7+bBBC8QfJD56Rt5bDFh lGwWmileHCwDuLOnT9k8=; b=gJvJ0iOePFD9nmD+izMXezFPPRknVw6h3YVyTsw6LXFY1HlfHW B3u+oVaWkXLpy3sQJl4rW4LOqGvmIBOefCAw==; From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sun, 31 Aug 2025 14:29:25 +0200 Subject: [PATCH v8 2/7] clk: qcom: gcc: Add support for Global Clock controller found on MSM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250831-msm8937-v8-2-b7dcd63caaac@mainlining.org> References: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> In-Reply-To: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Daniil Titov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756643366; l=30637; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=6PPGqcunREI/Dc6bwQw/3mJ+6PxNgSLlxJYGDC1bq+c=; b=hw2WN9ImYlhMAbsIhtXZUAORIfQgLx8L0Eq0VTXjI1G9ZjmNEbaVtBiTC2Yg/ZM+7B2CSprbC o9otT3wWLqHBqCWpkVorEoF/RTL/F0B/y/kndpaVsB6n9GqqDrCYLG7 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Daniil Titov Modify existing MSM8917 driver to support MSM8937 SoC. Override frequencies which are different in this chip. Register all the clocks to the framework for the clients to be able to request for them. Add new variant of GDSC for new chip. Signed-off-by: Daniil Titov Reviewed-by: Dmitry Baryshkov Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- drivers/clk/qcom/Kconfig | 6 +- drivers/clk/qcom/gcc-msm8917.c | 617 +++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 616 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index aeb6197d7c902098459c9b2cba75072bd519b0f3..e5de50354125445edcfdcfa03aa= 218ee66859b9a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -332,12 +332,12 @@ config MSM_GCC_8916 SD/eMMC, display, graphics, camera etc. =20 config MSM_GCC_8917 - tristate "MSM8917/QM215 Global Clock Controller" + tristate "MSM89(17/37)/QM215 Global Clock Controller" depends on ARM64 || COMPILE_TEST select QCOM_GDSC help - Support for the global clock controller on msm8917 and qm215 - devices. + Support for the global clock controller on msm8917, msm8937 + and qm215 devices. Say Y if you want to use devices such as UART, SPI i2c, USB, SD/eMMC, display, graphics, camera etc. =20 diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c index 3e2a2ae2ee6e9e647fb68c493ae7b0e49af79968..0a1aa623cd49af55d9d81148df7= 809b170fea60b 100644 --- a/drivers/clk/qcom/gcc-msm8917.c +++ b/drivers/clk/qcom/gcc-msm8917.c @@ -37,6 +37,8 @@ enum { DT_SLEEP_CLK, DT_DSI0PLL, DT_DSI0PLL_BYTE, + DT_DSI1PLL, + DT_DSI1PLL_BYTE, }; =20 enum { @@ -48,6 +50,8 @@ enum { P_GPLL6, P_DSI0PLL, P_DSI0PLL_BYTE, + P_DSI1PLL, + P_DSI1PLL_BYTE, }; =20 static struct clk_alpha_pll gpll0_sleep_clk_src =3D { @@ -102,7 +106,11 @@ static const struct pll_vco gpll3_p_vco[] =3D { { 700000000, 1400000000, 0 }, }; =20 -static const struct alpha_pll_config gpll3_early_config =3D { +static const struct pll_vco gpll3_p_vco_msm8937[] =3D { + { 525000000, 1066000000, 0 }, +}; + +static struct alpha_pll_config gpll3_early_config =3D { .l =3D 63, .config_ctl_val =3D 0x4001055b, .early_output_mask =3D 0, @@ -273,6 +281,19 @@ static const struct freq_tbl ftbl_blsp_i2c_apps_clk_sr= c[] =3D { { } }; =20 +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x0200c, + .hid_width =3D 5, + .freq_tbl =3D ftbl_blsp_i2c_apps_clk_src, + .parent_map =3D gcc_xo_gpll0_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup1_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_data), + .ops =3D &clk_rcg2_ops, + }, +}; + static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src =3D { .cmd_rcgr =3D 0x03000, .hid_width =3D 5, @@ -351,6 +372,19 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src =3D= { } }; =20 +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src =3D { + .cmd_rcgr =3D 0x18000, + .hid_width =3D 5, + .freq_tbl =3D ftbl_blsp_i2c_apps_clk_src, + .parent_map =3D gcc_xo_gpll0_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup4_i2c_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_data), + .ops =3D &clk_rcg2_ops, + }, +}; + static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] =3D { F(960000, P_XO, 10, 1, 2), F(4800000, P_XO, 4, 0, 0), @@ -362,6 +396,20 @@ static const struct freq_tbl ftbl_blsp_spi_apps_clk_sr= c[] =3D { { } }; =20 +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x02024, + .mnd_width =3D 8, + .hid_width =3D 5, + .freq_tbl =3D ftbl_blsp_spi_apps_clk_src, + .parent_map =3D gcc_xo_gpll0_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp1_qup1_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_data), + .ops =3D &clk_rcg2_ops, + }, +}; + static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src =3D { .cmd_rcgr =3D 0x03014, .hid_width =3D 5, @@ -446,6 +494,20 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src =3D= { } }; =20 +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src =3D { + .cmd_rcgr =3D 0x18024, + .mnd_width =3D 8, + .hid_width =3D 5, + .freq_tbl =3D ftbl_blsp_spi_apps_clk_src, + .parent_map =3D gcc_xo_gpll0_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "blsp2_qup4_spi_apps_clk_src", + .parent_data =3D gcc_xo_gpll0_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_data), + .ops =3D &clk_rcg2_ops, + }, +}; + static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] =3D { F(3686400, P_GPLL0, 1, 72, 15625), F(7372800, P_GPLL0, 1, 144, 15625), @@ -525,11 +587,19 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src =3D { static const struct parent_map gcc_byte0_map[] =3D { { P_XO, 0 }, { P_DSI0PLL_BYTE, 1 }, + { P_DSI1PLL_BYTE, 3 }, +}; + +static const struct parent_map gcc_byte1_map[] =3D { + { P_XO, 0 }, + { P_DSI0PLL_BYTE, 3 }, + { P_DSI1PLL_BYTE, 1 }, }; =20 static const struct clk_parent_data gcc_byte_data[] =3D { { .index =3D DT_XO }, { .index =3D DT_DSI0PLL_BYTE }, + { .index =3D DT_DSI1PLL_BYTE }, }; =20 static struct clk_rcg2 byte0_clk_src =3D { @@ -545,6 +615,19 @@ static struct clk_rcg2 byte0_clk_src =3D { } }; =20 +static struct clk_rcg2 byte1_clk_src =3D { + .cmd_rcgr =3D 0x4d0b0, + .hid_width =3D 5, + .parent_map =3D gcc_byte1_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "byte1_clk_src", + .parent_data =3D gcc_byte_data, + .num_parents =3D ARRAY_SIZE(gcc_byte_data), + .ops =3D &clk_byte2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static const struct freq_tbl ftbl_camss_gp_clk_src[] =3D { F(100000000, P_GPLL0, 8, 0, 0), F(160000000, P_GPLL0, 5, 0, 0), @@ -642,6 +725,17 @@ static const struct freq_tbl ftbl_cpp_clk_src[] =3D { { } }; =20 +static const struct freq_tbl ftbl_cpp_clk_src_msm8937[] =3D { + F(133330000, P_GPLL0, 6, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 5, 0, 0), + F(266666667, P_GPLL0, 3, 0, 0), + F(308570000, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + { } +}; + static struct clk_rcg2 cpp_clk_src =3D { .cmd_rcgr =3D 0x58018, .hid_width =3D 5, @@ -655,6 +749,13 @@ static struct clk_rcg2 cpp_clk_src =3D { } }; =20 +static struct clk_init_data vcodec0_clk_src_init_msm8937 =3D { + .name =3D "vcodec0_clk_src", + .parent_data =3D gcc_cpp_data, + .num_parents =3D ARRAY_SIZE(gcc_cpp_data), + .ops =3D &clk_rcg2_ops, +}; + static const struct freq_tbl ftbl_crypto_clk_src[] =3D { F(50000000, P_GPLL0, 16, 0, 0), F(80000000, P_GPLL0, 10, 0, 0), @@ -730,6 +831,13 @@ static const struct freq_tbl ftbl_csi_phytimer_clk_src= [] =3D { { } }; =20 +static const struct freq_tbl ftbl_csi_phytimer_clk_src_msm8937[] =3D { + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + { } +}; + static struct clk_rcg2 csi0phytimer_clk_src =3D { .cmd_rcgr =3D 0x4e000, .hid_width =3D 5, @@ -774,6 +882,19 @@ static struct clk_rcg2 esc0_clk_src =3D { } }; =20 +static struct clk_rcg2 esc1_clk_src =3D { + .cmd_rcgr =3D 0x4d0a8, + .hid_width =3D 5, + .freq_tbl =3D ftbl_esc0_1_clk_src, + .parent_map =3D gcc_xo_gpll0_out_aux_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "esc1_clk_src", + .parent_data =3D gcc_xo_gpll0_data, + .num_parents =3D ARRAY_SIZE(gcc_xo_gpll0_data), + .ops =3D &clk_rcg2_ops, + }, +}; + static const struct parent_map gcc_gfx3d_map[] =3D { { P_XO, 0 }, { P_GPLL0, 1 }, @@ -817,6 +938,25 @@ static const struct freq_tbl ftbl_gfx3d_clk_src[] =3D { { } }; =20 +static const struct freq_tbl ftbl_gfx3d_clk_src_msm8937[] =3D { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(216000000, P_GPLL6, 5, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(240000000, P_GPLL6, 4.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), + F(300000000, P_GPLL3, 1, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(375000000, P_GPLL3, 1, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(450000000, P_GPLL3, 1, 0, 0), + { } +}; + static struct clk_rcg2 gfx3d_clk_src =3D { .cmd_rcgr =3D 0x59000, .hid_width =3D 5, @@ -973,21 +1113,29 @@ static struct clk_rcg2 mdp_clk_src =3D { } }; =20 -static const struct parent_map gcc_pclk_map[] =3D { +static const struct parent_map gcc_pclk0_map[] =3D { { P_XO, 0 }, { P_DSI0PLL, 1 }, + { P_DSI1PLL, 3 }, +}; + +static const struct parent_map gcc_pclk1_map[] =3D { + { P_XO, 0 }, + { P_DSI0PLL, 3 }, + { P_DSI1PLL, 1 }, }; =20 static const struct clk_parent_data gcc_pclk_data[] =3D { { .index =3D DT_XO }, { .index =3D DT_DSI0PLL }, + { .index =3D DT_DSI1PLL }, }; =20 static struct clk_rcg2 pclk0_clk_src =3D { .cmd_rcgr =3D 0x4d000, .hid_width =3D 5, .mnd_width =3D 8, - .parent_map =3D gcc_pclk_map, + .parent_map =3D gcc_pclk0_map, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "pclk0_clk_src", .parent_data =3D gcc_pclk_data, @@ -997,6 +1145,20 @@ static struct clk_rcg2 pclk0_clk_src =3D { } }; =20 +static struct clk_rcg2 pclk1_clk_src =3D { + .cmd_rcgr =3D 0x4d0b8, + .hid_width =3D 5, + .mnd_width =3D 8, + .parent_map =3D gcc_pclk1_map, + .clkr.hw.init =3D &(struct clk_init_data){ + .name =3D "pclk1_clk_src", + .parent_data =3D gcc_pclk_data, + .num_parents =3D ARRAY_SIZE(gcc_pclk_data), + .ops =3D &clk_pixel_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static const struct freq_tbl ftbl_pdm2_clk_src[] =3D { F(64000000, P_GPLL0, 12.5, 0, 0), { } @@ -1108,6 +1270,14 @@ static const struct freq_tbl ftbl_usb_hs_system_clk_= src[] =3D { { } }; =20 +static const struct freq_tbl ftbl_usb_hs_system_clk_src_msm8937[] =3D { + F(57142857, P_GPLL0, 14, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133333333, P_GPLL0, 6, 0, 0), + F(177777778, P_GPLL0, 4.5, 0, 0), + { } +}; + static struct clk_rcg2 usb_hs_system_clk_src =3D { .cmd_rcgr =3D 0x41010, .hid_width =3D 5, @@ -1132,6 +1302,15 @@ static const struct freq_tbl ftbl_vcodec0_clk_src[] = =3D { { } }; =20 +static const struct freq_tbl ftbl_vcodec0_clk_src_msm8937[] =3D { + F(166150000, P_GPLL6, 6.5, 0, 0), + F(240000000, P_GPLL6, 4.5, 0, 0), + F(308571428, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + { } +}; + static struct clk_rcg2 vcodec0_clk_src =3D { .cmd_rcgr =3D 0x4c000, .hid_width =3D 5, @@ -1160,6 +1339,23 @@ static const struct freq_tbl ftbl_vfe_clk_src[] =3D { { } }; =20 +static const struct freq_tbl ftbl_vfe_clk_src_msm8937[] =3D { + F(50000000, P_GPLL0, 16, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(133333333, P_GPLL0, 6, 0, 0), + F(160000000, P_GPLL0, 5, 0, 0), + F(177777778, P_GPLL0, 4.5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266666667, P_GPLL0, 3, 0, 0), + F(308571428, P_GPLL6, 3.5, 0, 0), + F(320000000, P_GPLL0, 2.5, 0, 0), + F(360000000, P_GPLL6, 3, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(432000000, P_GPLL6, 2.5, 0, 0), + { } +}; + static struct clk_rcg2 vfe0_clk_src =3D { .cmd_rcgr =3D 0x58000, .hid_width =3D 5, @@ -1269,6 +1465,24 @@ static struct clk_branch gcc_blsp2_ahb_clk =3D { } }; =20 +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk =3D { + .halt_reg =3D 0x02008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x02008, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk =3D { .halt_reg =3D 0x03010, .halt_check =3D BRANCH_HALT, @@ -1377,6 +1591,42 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk= =3D { } }; =20 +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk =3D { + .halt_reg =3D 0x18020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x18020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup4_i2c_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk =3D { + .halt_reg =3D 0x02004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x02004, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_blsp1_qup2_spi_apps_clk =3D { .halt_reg =3D 0x0300c, .halt_check =3D BRANCH_HALT, @@ -1485,6 +1735,24 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk= =3D { } }; =20 +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk =3D { + .halt_reg =3D 0x1801c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1801c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_blsp2_qup4_spi_apps_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &blsp2_qup4_spi_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_blsp1_uart1_apps_clk =3D { .halt_reg =3D 0x0203c, .halt_check =3D BRANCH_HALT, @@ -2521,6 +2789,24 @@ static struct clk_branch gcc_mdss_byte0_clk =3D { } }; =20 +static struct clk_branch gcc_mdss_byte1_clk =3D { + .halt_reg =3D 0x4d0a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4d0a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_byte1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_mdss_esc0_clk =3D { .halt_reg =3D 0x4d098, .halt_check =3D BRANCH_HALT, @@ -2539,6 +2825,24 @@ static struct clk_branch gcc_mdss_esc0_clk =3D { } }; =20 +static struct clk_branch gcc_mdss_esc1_clk =3D { + .halt_reg =3D 0x4d09c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4d09c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_esc1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &esc1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_mdss_mdp_clk =3D { .halt_reg =3D 0x4d088, .halt_check =3D BRANCH_HALT, @@ -2575,6 +2879,24 @@ static struct clk_branch gcc_mdss_pclk0_clk =3D { } }; =20 +static struct clk_branch gcc_mdss_pclk1_clk =3D { + .halt_reg =3D 0x4d0a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4d0a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_mdss_pclk1_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &pclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_mdss_vsync_clk =3D { .halt_reg =3D 0x4d090, .halt_check =3D BRANCH_HALT, @@ -2632,6 +2954,24 @@ static struct clk_branch gcc_oxili_ahb_clk =3D { } }; =20 +static struct clk_branch gcc_oxili_aon_clk =3D { + .halt_reg =3D 0x5904c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x5904c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_aon_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gfx3d_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gcc_oxili_gfx3d_clk =3D { .halt_reg =3D 0x59020, .halt_check =3D BRANCH_HALT, @@ -2650,6 +2990,19 @@ static struct clk_branch gcc_oxili_gfx3d_clk =3D { } }; =20 +static struct clk_branch gcc_oxili_timer_clk =3D { + .halt_reg =3D 0x59040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x59040, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_oxili_timer_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pdm2_clk =3D { .halt_reg =3D 0x4400c, .halt_check =3D BRANCH_HALT, @@ -3027,6 +3380,28 @@ static struct gdsc oxili_gx_gdsc =3D { .flags =3D CLAMP_IO, }; =20 +static struct gdsc oxili_gx_gdsc_msm8937 =3D { + .gdscr =3D 0x5901c, + .clamp_io_ctrl =3D 0x5b00c, + .cxcs =3D (unsigned int []){ 0x59000 }, + .cxc_count =3D 1, + .pd =3D { + .name =3D "oxili_gx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D CLAMP_IO, +}; + +static struct gdsc oxili_cx_gdsc =3D { + .gdscr =3D 0x59044, + .cxcs =3D (unsigned int []){ 0x59020 }, + .cxc_count =3D 1, + .pd =3D { + .name =3D "oxili_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + static struct gdsc cpp_gdsc =3D { .gdscr =3D 0x58078, .cxcs =3D (unsigned int []){ 0x5803c, 0x58064 }, @@ -3207,6 +3582,188 @@ static struct clk_regmap *gcc_msm8917_clocks[] =3D { [GCC_VFE_TBU_CLK] =3D &gcc_vfe_tbu_clk.clkr, }; =20 +static struct clk_regmap *gcc_msm8937_clocks[] =3D { + [GPLL0] =3D &gpll0.clkr, + [GPLL0_EARLY] =3D &gpll0_early.clkr, + [GPLL0_SLEEP_CLK_SRC] =3D &gpll0_sleep_clk_src.clkr, + [GPLL3] =3D &gpll3.clkr, + [GPLL3_EARLY] =3D &gpll3_early.clkr, + [GPLL4] =3D &gpll4.clkr, + [GPLL4_EARLY] =3D &gpll4_early.clkr, + [GPLL6] =3D &gpll6, + [GPLL6_EARLY] =3D &gpll6_early.clkr, + [APSS_AHB_CLK_SRC] =3D &apss_ahb_clk_src.clkr, + [MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC] =3D &blsp1_qup1_i2c_apps_clk_src.cl= kr, + [MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC] =3D &blsp1_qup1_spi_apps_clk_src.cl= kr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] =3D &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] =3D &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] =3D &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] =3D &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] =3D &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] =3D &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] =3D &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] =3D &blsp1_uart2_apps_clk_src.clkr, + [BLSP2_QUP1_I2C_APPS_CLK_SRC] =3D &blsp2_qup1_i2c_apps_clk_src.clkr, + [BLSP2_QUP1_SPI_APPS_CLK_SRC] =3D &blsp2_qup1_spi_apps_clk_src.clkr, + [BLSP2_QUP2_I2C_APPS_CLK_SRC] =3D &blsp2_qup2_i2c_apps_clk_src.clkr, + [BLSP2_QUP2_SPI_APPS_CLK_SRC] =3D &blsp2_qup2_spi_apps_clk_src.clkr, + [BLSP2_QUP3_I2C_APPS_CLK_SRC] =3D &blsp2_qup3_i2c_apps_clk_src.clkr, + [BLSP2_QUP3_SPI_APPS_CLK_SRC] =3D &blsp2_qup3_spi_apps_clk_src.clkr, + [MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC] =3D &blsp2_qup4_i2c_apps_clk_src.cl= kr, + [MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC] =3D &blsp2_qup4_spi_apps_clk_src.cl= kr, + [BLSP2_UART1_APPS_CLK_SRC] =3D &blsp2_uart1_apps_clk_src.clkr, + [BLSP2_UART2_APPS_CLK_SRC] =3D &blsp2_uart2_apps_clk_src.clkr, + [BYTE0_CLK_SRC] =3D &byte0_clk_src.clkr, + [MSM8937_BYTE1_CLK_SRC] =3D &byte1_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] =3D &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] =3D &camss_gp1_clk_src.clkr, + [CAMSS_TOP_AHB_CLK_SRC] =3D &camss_top_ahb_clk_src.clkr, + [CCI_CLK_SRC] =3D &cci_clk_src.clkr, + [CPP_CLK_SRC] =3D &cpp_clk_src.clkr, + [CRYPTO_CLK_SRC] =3D &crypto_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] =3D &csi0phytimer_clk_src.clkr, + [CSI0_CLK_SRC] =3D &csi0_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] =3D &csi1phytimer_clk_src.clkr, + [CSI1_CLK_SRC] =3D &csi1_clk_src.clkr, + [CSI2_CLK_SRC] =3D &csi2_clk_src.clkr, + [ESC0_CLK_SRC] =3D &esc0_clk_src.clkr, + [MSM8937_ESC1_CLK_SRC] =3D &esc1_clk_src.clkr, + [GFX3D_CLK_SRC] =3D &gfx3d_clk_src.clkr, + [GP1_CLK_SRC] =3D &gp1_clk_src.clkr, + [GP2_CLK_SRC] =3D &gp2_clk_src.clkr, + [GP3_CLK_SRC] =3D &gp3_clk_src.clkr, + [JPEG0_CLK_SRC] =3D &jpeg0_clk_src.clkr, + [MCLK0_CLK_SRC] =3D &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] =3D &mclk1_clk_src.clkr, + [MCLK2_CLK_SRC] =3D &mclk2_clk_src.clkr, + [MDP_CLK_SRC] =3D &mdp_clk_src.clkr, + [PCLK0_CLK_SRC] =3D &pclk0_clk_src.clkr, + [MSM8937_PCLK1_CLK_SRC] =3D &pclk1_clk_src.clkr, + [PDM2_CLK_SRC] =3D &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] =3D &sdcc1_apps_clk_src.clkr, + [SDCC1_ICE_CORE_CLK_SRC] =3D &sdcc1_ice_core_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] =3D &sdcc2_apps_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] =3D &usb_hs_system_clk_src.clkr, + [VCODEC0_CLK_SRC] =3D &vcodec0_clk_src.clkr, + [VFE0_CLK_SRC] =3D &vfe0_clk_src.clkr, + [VFE1_CLK_SRC] =3D &vfe1_clk_src.clkr, + [VSYNC_CLK_SRC] =3D &vsync_clk_src.clkr, + [GCC_APSS_TCU_CLK] =3D &gcc_apss_tcu_clk.clkr, + [GCC_BIMC_GFX_CLK] =3D &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] =3D &gcc_bimc_gpu_clk.clkr, + [GCC_BLSP1_AHB_CLK] =3D &gcc_blsp1_ahb_clk.clkr, + [MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK] =3D &gcc_blsp1_qup1_i2c_apps_clk.cl= kr, + [MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK] =3D &gcc_blsp1_qup1_spi_apps_clk.cl= kr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] =3D &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] =3D &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] =3D &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] =3D &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] =3D &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] =3D &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] =3D &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] =3D &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP2_AHB_CLK] =3D &gcc_blsp2_ahb_clk.clkr, + [GCC_BLSP2_QUP1_I2C_APPS_CLK] =3D &gcc_blsp2_qup1_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP1_SPI_APPS_CLK] =3D &gcc_blsp2_qup1_spi_apps_clk.clkr, + [GCC_BLSP2_QUP2_I2C_APPS_CLK] =3D &gcc_blsp2_qup2_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP2_SPI_APPS_CLK] =3D &gcc_blsp2_qup2_spi_apps_clk.clkr, + [GCC_BLSP2_QUP3_I2C_APPS_CLK] =3D &gcc_blsp2_qup3_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP3_SPI_APPS_CLK] =3D &gcc_blsp2_qup3_spi_apps_clk.clkr, + [MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK] =3D &gcc_blsp2_qup4_i2c_apps_clk.cl= kr, + [MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK] =3D &gcc_blsp2_qup4_spi_apps_clk.cl= kr, + [GCC_BLSP2_UART1_APPS_CLK] =3D &gcc_blsp2_uart1_apps_clk.clkr, + [GCC_BLSP2_UART2_APPS_CLK] =3D &gcc_blsp2_uart2_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMSS_AHB_CLK] =3D &gcc_camss_ahb_clk.clkr, + [GCC_CAMSS_CCI_AHB_CLK] =3D &gcc_camss_cci_ahb_clk.clkr, + [GCC_CAMSS_CCI_CLK] =3D &gcc_camss_cci_clk.clkr, + [GCC_CAMSS_CPP_AHB_CLK] =3D &gcc_camss_cpp_ahb_clk.clkr, + [GCC_CAMSS_CPP_CLK] =3D &gcc_camss_cpp_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] =3D &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI0PHY_CLK] =3D &gcc_camss_csi0phy_clk.clkr, + [GCC_CAMSS_CSI0PIX_CLK] =3D &gcc_camss_csi0pix_clk.clkr, + [GCC_CAMSS_CSI0RDI_CLK] =3D &gcc_camss_csi0rdi_clk.clkr, + [GCC_CAMSS_CSI0_AHB_CLK] =3D &gcc_camss_csi0_ahb_clk.clkr, + [GCC_CAMSS_CSI0_CLK] =3D &gcc_camss_csi0_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] =3D &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHY_CLK] =3D &gcc_camss_csi1phy_clk.clkr, + [GCC_CAMSS_CSI1PIX_CLK] =3D &gcc_camss_csi1pix_clk.clkr, + [GCC_CAMSS_CSI1RDI_CLK] =3D &gcc_camss_csi1rdi_clk.clkr, + [GCC_CAMSS_CSI1_AHB_CLK] =3D &gcc_camss_csi1_ahb_clk.clkr, + [GCC_CAMSS_CSI1_CLK] =3D &gcc_camss_csi1_clk.clkr, + [GCC_CAMSS_CSI2PHY_CLK] =3D &gcc_camss_csi2phy_clk.clkr, + [GCC_CAMSS_CSI2PIX_CLK] =3D &gcc_camss_csi2pix_clk.clkr, + [GCC_CAMSS_CSI2RDI_CLK] =3D &gcc_camss_csi2rdi_clk.clkr, + [GCC_CAMSS_CSI2_AHB_CLK] =3D &gcc_camss_csi2_ahb_clk.clkr, + [GCC_CAMSS_CSI2_CLK] =3D &gcc_camss_csi2_clk.clkr, + [GCC_CAMSS_CSI_VFE0_CLK] =3D &gcc_camss_csi_vfe0_clk.clkr, + [GCC_CAMSS_CSI_VFE1_CLK] =3D &gcc_camss_csi_vfe1_clk.clkr, + [GCC_CAMSS_GP0_CLK] =3D &gcc_camss_gp0_clk.clkr, + [GCC_CAMSS_GP1_CLK] =3D &gcc_camss_gp1_clk.clkr, + [GCC_CAMSS_ISPIF_AHB_CLK] =3D &gcc_camss_ispif_ahb_clk.clkr, + [GCC_CAMSS_JPEG0_CLK] =3D &gcc_camss_jpeg0_clk.clkr, + [GCC_CAMSS_JPEG_AHB_CLK] =3D &gcc_camss_jpeg_ahb_clk.clkr, + [GCC_CAMSS_JPEG_AXI_CLK] =3D &gcc_camss_jpeg_axi_clk.clkr, + [GCC_CAMSS_MCLK0_CLK] =3D &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK1_CLK] =3D &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MCLK2_CLK] =3D &gcc_camss_mclk2_clk.clkr, + [GCC_CAMSS_MICRO_AHB_CLK] =3D &gcc_camss_micro_ahb_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK] =3D &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AHB_CLK] =3D &gcc_camss_vfe0_ahb_clk.clkr, + [GCC_CAMSS_VFE0_AXI_CLK] =3D &gcc_camss_vfe0_axi_clk.clkr, + [GCC_CAMSS_VFE0_CLK] =3D &gcc_camss_vfe0_clk.clkr, + [GCC_CAMSS_VFE1_AHB_CLK] =3D &gcc_camss_vfe1_ahb_clk.clkr, + [GCC_CAMSS_VFE1_AXI_CLK] =3D &gcc_camss_vfe1_axi_clk.clkr, + [GCC_CAMSS_VFE1_CLK] =3D &gcc_camss_vfe1_clk.clkr, + [GCC_CPP_TBU_CLK] =3D &gcc_cpp_tbu_clk.clkr, + [GCC_CRYPTO_AHB_CLK] =3D &gcc_crypto_ahb_clk.clkr, + [GCC_CRYPTO_AXI_CLK] =3D &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_CLK] =3D &gcc_crypto_clk.clkr, + [GCC_DCC_CLK] =3D &gcc_dcc_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_JPEG_TBU_CLK] =3D &gcc_jpeg_tbu_clk.clkr, + [GCC_MDP_TBU_CLK] =3D &gcc_mdp_tbu_clk.clkr, + [GCC_MDSS_AHB_CLK] =3D &gcc_mdss_ahb_clk.clkr, + [GCC_MDSS_AXI_CLK] =3D &gcc_mdss_axi_clk.clkr, + [GCC_MDSS_BYTE0_CLK] =3D &gcc_mdss_byte0_clk.clkr, + [MSM8937_GCC_MDSS_BYTE1_CLK] =3D &gcc_mdss_byte1_clk.clkr, + [GCC_MDSS_ESC0_CLK] =3D &gcc_mdss_esc0_clk.clkr, + [MSM8937_GCC_MDSS_ESC1_CLK] =3D &gcc_mdss_esc1_clk.clkr, + [GCC_MDSS_MDP_CLK] =3D &gcc_mdss_mdp_clk.clkr, + [GCC_MDSS_PCLK0_CLK] =3D &gcc_mdss_pclk0_clk.clkr, + [MSM8937_GCC_MDSS_PCLK1_CLK] =3D &gcc_mdss_pclk1_clk.clkr, + [GCC_MDSS_VSYNC_CLK] =3D &gcc_mdss_vsync_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] =3D &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] =3D &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_OXILI_AHB_CLK] =3D &gcc_oxili_ahb_clk.clkr, + [MSM8937_GCC_OXILI_AON_CLK] =3D &gcc_oxili_aon_clk.clkr, + [GCC_OXILI_GFX3D_CLK] =3D &gcc_oxili_gfx3d_clk.clkr, + [MSM8937_GCC_OXILI_TIMER_CLK] =3D &gcc_oxili_timer_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] =3D &gcc_prng_ahb_clk.clkr, + [GCC_QDSS_DAP_CLK] =3D &gcc_qdss_dap_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK] =3D &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_SMMU_CFG_CLK] =3D &gcc_smmu_cfg_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] =3D &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_AHB_CLK] =3D &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_PHY_CFG_AHB_CLK] =3D &gcc_usb_hs_phy_cfg_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] =3D &gcc_usb_hs_system_clk.clkr, + [GCC_VENUS0_AHB_CLK] =3D &gcc_venus0_ahb_clk.clkr, + [GCC_VENUS0_AXI_CLK] =3D &gcc_venus0_axi_clk.clkr, + [GCC_VENUS0_CORE0_VCODEC0_CLK] =3D &gcc_venus0_core0_vcodec0_clk.clkr, + [GCC_VENUS0_VCODEC0_CLK] =3D &gcc_venus0_vcodec0_clk.clkr, + [GCC_VENUS_TBU_CLK] =3D &gcc_venus_tbu_clk.clkr, + [GCC_VFE1_TBU_CLK] =3D &gcc_vfe1_tbu_clk.clkr, + [GCC_VFE_TBU_CLK] =3D &gcc_vfe_tbu_clk.clkr, +}; + static const struct qcom_reset_map gcc_msm8917_resets[] =3D { [GCC_CAMSS_MICRO_BCR] =3D { 0x56008 }, [GCC_MSS_BCR] =3D { 0x71000 }, @@ -3234,6 +3791,18 @@ static struct gdsc *gcc_msm8917_gdscs[] =3D { [VFE1_GDSC] =3D &vfe1_gdsc, }; =20 +static struct gdsc *gcc_msm8937_gdscs[] =3D { + [CPP_GDSC] =3D &cpp_gdsc, + [JPEG_GDSC] =3D &jpeg_gdsc, + [MDSS_GDSC] =3D &mdss_gdsc, + [OXILI_GX_GDSC] =3D &oxili_gx_gdsc_msm8937, + [MSM8937_OXILI_CX_GDSC] =3D &oxili_cx_gdsc, + [VENUS_CORE0_GDSC] =3D &venus_core0_gdsc, + [VENUS_GDSC] =3D &venus_gdsc, + [VFE0_GDSC] =3D &vfe0_gdsc, + [VFE1_GDSC] =3D &vfe1_gdsc, +}; + static const struct qcom_cc_desc gcc_msm8917_desc =3D { .config =3D &gcc_msm8917_regmap_config, .clks =3D gcc_msm8917_clocks, @@ -3254,6 +3823,41 @@ static const struct qcom_cc_desc gcc_qm215_desc =3D { .num_gdscs =3D ARRAY_SIZE(gcc_msm8917_gdscs), }; =20 +static const struct qcom_cc_desc gcc_msm8937_desc =3D { + .config =3D &gcc_msm8917_regmap_config, + .clks =3D gcc_msm8937_clocks, + .num_clks =3D ARRAY_SIZE(gcc_msm8937_clocks), + .resets =3D gcc_msm8917_resets, + .num_resets =3D ARRAY_SIZE(gcc_msm8917_resets), + .gdscs =3D gcc_msm8937_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_msm8937_gdscs), +}; + +static void msm8937_clock_override(void) +{ + /* GPLL3 750MHz configuration */ + gpll3_early_config.l =3D 47; + gpll3_early.vco_table =3D gpll3_p_vco_msm8937; + gpll3_early.num_vco =3D ARRAY_SIZE(gpll3_p_vco_msm8937); + + /* + * Set below clocks for use specific msm8937 parent map. + */ + vcodec0_clk_src.parent_map =3D gcc_cpp_map; + vcodec0_clk_src.clkr.hw.init =3D &vcodec0_clk_src_init_msm8937; + + /* + * Set below clocks for use specific msm8937 freq table. + */ + vfe0_clk_src.freq_tbl =3D ftbl_vfe_clk_src_msm8937; + vfe1_clk_src.freq_tbl =3D ftbl_vfe_clk_src_msm8937; + cpp_clk_src.freq_tbl =3D ftbl_cpp_clk_src_msm8937; + vcodec0_clk_src.freq_tbl =3D ftbl_vcodec0_clk_src_msm8937; + csi0phytimer_clk_src.freq_tbl =3D ftbl_csi_phytimer_clk_src_msm8937; + csi1phytimer_clk_src.freq_tbl =3D ftbl_csi_phytimer_clk_src_msm8937; + usb_hs_system_clk_src.freq_tbl =3D ftbl_usb_hs_system_clk_src_msm8937; +} + static int gcc_msm8917_probe(struct platform_device *pdev) { struct regmap *regmap; @@ -3261,8 +3865,12 @@ static int gcc_msm8917_probe(struct platform_device = *pdev) =20 gcc_desc =3D of_device_get_match_data(&pdev->dev); =20 - if (gcc_desc =3D=3D &gcc_qm215_desc) + if (gcc_desc =3D=3D &gcc_qm215_desc) { gfx3d_clk_src.parent_map =3D gcc_gfx3d_map_qm215; + } else if (gcc_desc =3D=3D &gcc_msm8937_desc) { + msm8937_clock_override(); + gfx3d_clk_src.freq_tbl =3D ftbl_gfx3d_clk_src_msm8937; + } =20 regmap =3D qcom_cc_map(pdev, gcc_desc); if (IS_ERR(regmap)) @@ -3276,6 +3884,7 @@ static int gcc_msm8917_probe(struct platform_device *= pdev) static const struct of_device_id gcc_msm8917_match_table[] =3D { { .compatible =3D "qcom,gcc-msm8917", .data =3D &gcc_msm8917_desc }, { .compatible =3D "qcom,gcc-qm215", .data =3D &gcc_qm215_desc }, + { .compatible =3D "qcom,gcc-msm8937", .data =3D &gcc_msm8937_desc }, {}, }; MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table); --=20 2.51.0 From nobody Fri Oct 3 13:30:15 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54CF23505E; Sun, 31 Aug 2025 12:34:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756643674; cv=none; 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, Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756643366; l=1371; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=PqGAymhItUAgrgLZjol3iWiJiDIeiqJdNfuxcC9G7II=; b=icUF8qZT338mue8tXjQf6slJOUElsNDHI/eMCObmeOE38Do4iEb8qUs6DP3NlV1T691XnIetW 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Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index b913192219e40324c03f4ff1dce955881e7fb3d2..ef97faac7e47c1483f9758d2bb2= a13f9c3664177 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -36,6 +36,7 @@ properties: - qcom,scm-msm8226 - qcom,scm-msm8660 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -134,6 +135,7 @@ allOf: - qcom,scm-msm8226 - qcom,scm-msm8660 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -177,6 +179,7 @@ allOf: - qcom,scm-mdm9607 - qcom,scm-msm8226 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8974 - qcom,scm-msm8976 --=20 2.51.0 From nobody Fri Oct 3 13:30:15 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B2851E766E; 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a=ed25519-sha256; t=1756643366; l=919; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=wmw2TX8XeI2jwe+eIPMA5Br3dVaIT7iuD5zo+71Kf2U=; b=RbPShjv5MKWNvSkEm+xPfDJeWQqTzNuY4hV+79/V/xWYs26D9HDtKUgaPKzP624mKYnEXNw8a cCz0frRxlS4BxqoYqpuVnZwHdlG5sNSTTUviMcNsuUefS5MGzmPEmBj X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Descirbe A505 clocks it is using same clocks like A506. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 7ef80f9fac8b2927b2a69100a7f6c729d9d188ab..3696b083e353031a496a1f299d8= f373270ca562d 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -252,7 +252,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-506\.[0-9]+$' + pattern: '^qcom,adreno-50[56]\.[0-9]+$' then: properties: clocks: --=20 2.51.0 From nobody Fri Oct 3 13:30:15 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8682225D1E6; Sun, 31 Aug 2025 12:37:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1756643379; bh=l6+MemH1Zc+F/c08V1C041o kOXvFiCq4qTFjf2CEIo4=; b=8aSGHtY13nvImg8BtPf0A5qqBdZMeCW0L24lWSSMQV7RMFt4J9 Euembogm3gbLzFsxb20JBzxYZz6GSs+BFcDA==; From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sun, 31 Aug 2025 14:29:28 +0200 Subject: [PATCH v8 5/7] arm64: dts: qcom: Add initial support for MSM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250831-msm8937-v8-5-b7dcd63caaac@mainlining.org> References: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> In-Reply-To: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756643366; l=50007; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=80jdLXefa7Px0v2qEB+k2eFk6D4nwLqIqUWKrhptW0M=; b=rLQnHk8mgZhMYclJ/eYlUJ5CFR4+ELopktR9+Eugy8jetVQvV4sG9XSO1iX4IH6TwXV91VGDU IzgqP7AY5QhDABtE/Pjl0UUx/9M4/oIBYFy3/aGzGnq7MbY2X2tNgVT X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dang Huynh Add initial support for MSM8937 SoC. Signed-off-by: Dang Huynh Co-developed-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8937.dtsi | 2134 +++++++++++++++++++++++++++++= ++++ 1 file changed, 2134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qc= om/msm8937.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..c3d7a8b455899fb46e442713537= 7980a294833dc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi @@ -0,0 +1,2134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Dang Huynh + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + device_type =3D "cpu"; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c0>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@100 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <0x100000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@102 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@103 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + device_type =3D "cpu"; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu_opp_table_c1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8937", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", + "bus", + "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + device_type =3D "memory"; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + qseecom_mem: reserved@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + rmtfs@92100000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x92100000 0x0 0x180000>; + no-map; + + qcom,client-id =3D <1>; + }; + + adsp_mem: adsp { + size =3D <0x0 0x1100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + wcnss_mem: wcnss { + size =3D <0x0 0x700000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x400000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz =3D /bits/ 64 <768000000>; + }; + + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8937-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs1 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8937", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8937", "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8937-rpmpd", "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apcs1 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + mboxes =3D <&apcs1 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <451>, <431>; + + interrupts =3D ; + + mboxes =3D <&apcs1 18>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mboxes =3D <0>, <&apcs1 13>, <0>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0xffffffff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qfprom: qfprom@a4000 { + compatible =3D "qcom,msm8937-qfprom", "qcom,qfprom"; + reg =3D <0x000a4000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_base1: base1@1d8 { + reg =3D <0x1d8 0x1>; + bits =3D <0 8>; + }; + + tsens_s5_p1: s5-p1@1d9 { + reg =3D <0x1d9 0x1>; + bits =3D <0 6>; + }; + + tsens_s5_p2: s5-p2@1d9 { + reg =3D <0x1d9 0x2>; + bits =3D <6 6>; + }; + + tsens_s6_p1: s6-p1@1da { + reg =3D <0x1da 0x2>; + bits =3D <4 6>; + }; + + tsens_s6_p2: s6-p2@1db { + reg =3D <0x1db 0x1>; + bits =3D <2 6>; + }; + + tsens_s7_p1: s7-p1@1dc { + reg =3D <0x1dc 0x1>; + bits =3D <0 6>; + }; + + tsens_s7_p2: s7-p2@1dc { + reg =3D <0x1dc 0x2>; + bits =3D <6 6>; + }; + + tsens_s8_p1: s8-p1@1dd { + reg =3D <0x1dd 0x2>; + bits =3D <4 6>; + }; + + tsens_s8_p2: s8-p2@1de { + reg =3D <0x1de 0x1>; + bits =3D <2 6>; + }; + + tsens_base2: base2@1df { + reg =3D <0x1df 0x1>; + bits =3D <0 8>; + }; + + tsens_mode: mode@210 { + reg =3D <0x210 0x1>; + bits =3D <0 3>; + }; + + tsens_s0_p1: s0-p1@210 { + reg =3D <0x210 0x2>; + bits =3D <3 6>; + }; + + tsens_s0_p2: s0-p2@211 { + reg =3D <0x211 0x1>; + bits =3D <1 6>; + }; + + tsens_s1_p1: s1-p1@211 { + reg =3D <0x211 0x2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@212 { + reg =3D <0x212 0x2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@213 { + reg =3D <0x213 0x2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@214 { + reg =3D <0x214 0x1>; + bits =3D <1 6>; + }; + + tsens_s3_p1: s3-p1@214 { + reg =3D <0x214 0x2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@215 { + reg =3D <0x215 0x2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@216 { + reg =3D <0x216 0x2>; + bits =3D <3 6>; + }; + + tsens_s4_p2: s4-p2@217 { + reg =3D <0x217 0x1>; + bits =3D <1 6>; + }; + + tsens_s9_p1: s9-p1@230 { + reg =3D <0x230 0x1>; + bits =3D <0 6>; + }; + + tsens_s9_p2: s9-p2@230 { + reg =3D <0x230 0x2>; + bits =3D <6 6>; + }; + + tsens_s10_p1: s10-p1@231 { + reg =3D <0x231 0x2>; + bits =3D <4 6>; + }; + + tsens_s10_p2: s10-p2@232 { + reg =3D <0x232 0x1>; + bits =3D <2 6>; + }; + + gpu_speed_bin: gpu-speed-bin@601b { + reg =3D <0x601b 0x1>; + bits =3D <7 1>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x0006c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", + "ahb", + "sleep"; + resets =3D <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", + "por"; + status =3D "disabled"; + }; + + rng@e3000 { + compatible =3D "qcom,prng"; + reg =3D <0x000e3000 0x1000>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8937-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts =3D ; + interrupt-names =3D "uplow"; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names =3D "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + #qcom,sensors =3D <11>; + #thermal-sensor-cells =3D <1>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8917-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + cs-pins { + pins =3D "gpio10"; + function =3D "blsp_spi3"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "blsp_spi3"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + blsp1_spi3_sleep: blsp1-spi3-sleep-state { + cs-pins { + pins =3D "gpio10"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + }; + + blsp2_spi2_sleep: blsp2-spi2-sleep-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_cmd_default: cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <16>; + bias-pull-up; + }; + + sdc2_data_default: data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan-pins { + pins =3D "gpio79", "gpio80"; + function =3D "wcss_wlan"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan0-pins { + pins =3D "gpio78"; + function =3D "wcss_wlan0"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan1-pins { + pins =3D "gpio77"; + function =3D "wcss_wlan1"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan2-pins { + pins =3D "gpio76"; + function =3D "wcss_wlan2"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8937"; + reg =3D <0x01800000 0x80000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; + clock-names =3D "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8937", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ab0000 0x1040>; + reg-names =3D "mdss_phys", + "vbif_phys"; + ranges; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + status =3D "disabled"; + + mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8937-mdp5", "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + iommus =3D <&apps_iommu 0x15>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdp5_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + mdp5_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a94000 0x300>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&mdss_dsi0_opp_table>; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94400 { + compatible =3D "qcom,dsi-phy-28nm-8937"; + reg =3D <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "ref"; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@1a96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a96000 0x300>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc MSM8937_BYTE1_CLK_SRC>, + <&gcc MSM8937_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc MSM8937_GCC_MDSS_BYTE1_CLK>, + <&gcc MSM8937_GCC_MDSS_PCLK1_CLK>, + <&gcc MSM8937_GCC_MDSS_ESC1_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi1_phy>; + + operating-points-v2 =3D <&mdss_dsi1_opp_table>; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + + mdss_dsi1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible =3D "qcom,dsi-phy-28nm-8937"; + reg =3D <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a94b80 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "ref"; + + status =3D "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-505.0", "qcom,adreno"; + reg =3D <0x01c00000 0x40000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + #cooling-cells =3D <2>; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc MSM8937_GCC_OXILI_TIMER_CLK>, + <&gcc MSM8937_GCC_OXILI_AON_CLK>; + clock-names =3D "core", + "iface", + "mem_iface", + "alt_mem_iface", + "rbbmtimer", + "alwayson"; + operating-points-v2 =3D <&gpu_opp_table>; + power-domains =3D <&gcc OXILI_GX_GDSC>; + + iommus =3D <&adreno_smmu 0>; + + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_min_svs>; + }; + + opp-216000000 { + opp-hz =3D /bits/ 64 <216000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_nom>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_nom_plus>; + }; + + opp-450000000 { + opp-hz =3D /bits/ 64 <450000000>; + opp-supported-hw =3D <0xff>; + required-opps =3D <&rpmpd_opp_turbo>; + }; + }; + }; + + adreno_smmu: iommu@1c40000 { + compatible =3D "qcom,msm8996-smmu-v2", + "qcom,adreno-smmu", + "qcom,smmu-v2"; + reg =3D <0x01c40000 0x10000>; + + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + ; + #iommu-cells =3D <1>; + + clocks =3D <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_OXILI_AHB_CLK>; + clock-names =3D "bus", + "iface"; + + power-domains =3D <&gcc MSM8937_OXILI_CX_GDSC>; + }; + + apps_iommu: iommu@1e20000 { + compatible =3D "qcom,msm8937-iommu", "qcom,msm-iommu-v1"; + ranges =3D <0 0x01e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", + "bus"; + + qcom,iommu-secure-id =3D <17>; + + #address-cells =3D <1>; + #iommu-cells =3D <1>; + #size-cells =3D <1>; + + /* VFE */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x14000 0x1000>; + interrupts =3D ; + }; + + /* MDP_0 */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x15000 0x1000>; + interrupts =3D ; + }; + + /* VENUS_NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x16000 0x1000>; + interrupts =3D ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x04044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + + num-channels =3D <6>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, + <0x07824000 0x800>; + reg-names =3D "hc", + "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "core", + "xo"; + pinctrl-0 =3D <&sdc1_default>; + pinctrl-1 =3D <&sdc1_sleep>; + pinctrl-names =3D "default", + "sleep"; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x500>, + <0x07864000 0x800>; + reg-names =3D "hc", + "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "core", + "xo"; + pinctrl-0 =3D <&sdc2_default>; + pinctrl-1 =3D <&sdc2_sleep>; + pinctrl-names =3D "default", + "sleep"; + power-domains =3D <&rpmpd MSM8937_VDDCX>; + bus-width =3D <4>; + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 2>, + <&blsp1_dma 3>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + pinctrl-names =3D "default", + "sleep"; + status =3D "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 6>, + <&blsp1_dma 7>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_i2c2_default>; + pinctrl-1 =3D <&blsp1_i2c2_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_i2c3_default>; + pinctrl-1 =3D <&blsp1_i2c3_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_spi3_default>; + pinctrl-1 =3D <&blsp1_spi3_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp1_dma 10>, + <&blsp1_dma 11>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp1_i2c4_default>; + pinctrl-1 =3D <&blsp1_i2c4_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1d000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <10>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp2_dma 4>, + <&blsp2_dma 5>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp2_i2c1_default>; + pinctrl-1 =3D <&blsp2_i2c1_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp2_spi2: spi@7af6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", + "iface"; + dmas =3D <&blsp2_dma 6>, + <&blsp2_dma 7>; + dma-names =3D "tx", + "rx"; + pinctrl-0 =3D <&blsp2_spi2_default>; + pinctrl-1 =3D <&blsp2_spi2_sleep>; + pinctrl-names =3D "default", + "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", + "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + phy_type =3D "ulpi"; + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + status =3D "disabled"; + #reset-cells =3D <1>; + }; + + wcnss: remoteproc@a204000 { + compatible =3D "qcom,pronto-v3-pil", "qcom,pronto"; + reg =3D <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names =3D "ccu", + "dxe", + "pmu"; + + memory-region =3D <&wcnss_mem>; + + interrupts-extended =3D <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + power-domains =3D <&rpmpd MSM8937_VDDCX>, + <&rpmpd MSM8937_VDDMX>; + power-domain-names =3D "cx", + "mx"; + + qcom,smem-states =3D <&wcnss_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + pinctrl-0 =3D <&wcnss_pin_a>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + + wcnss_iris: iris { + clocks =3D <&rpmcc RPM_SMD_RF_CLK2>; + clock-names =3D "xo"; + }; + + smd-edge { + interrupts =3D ; + + mboxes =3D <&apcs1 17>; + qcom,smd-edge =3D <6>; + qcom,remote-pid =3D <4>; + + label =3D "pronto"; + + wcnss_ctrl: wcnss { + compatible =3D "qcom,wcnss"; + qcom,smd-channels =3D "WCNSS_CTRL"; + + qcom,mmio =3D <&wcnss>; + + wcnss_bt: bluetooth { + compatible =3D "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible =3D "qcom,wcnss-wlan"; + + interrupts =3D , + ; + interrupt-names =3D "tx", + "rx"; + + qcom,smem-states =3D <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names =3D "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs1: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + #mbox-cells =3D <1>; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0x0b017000 0x1000>; + clocks =3D <&sleep_clk>; + }; + + timer@b120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@b121000 { + reg =3D <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@b123000 { + reg =3D <0x0b123000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b124000 { + reg =3D <0x0b124000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b125000 { + reg =3D <0x0b125000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b126000 { + reg =3D <0x0b126000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b127000 { + reg =3D <0x0b127000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@b128000 { + reg =3D <0x0b128000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + }; + + thermal_zones: thermal-zones { + aoss-thermal { + thermal-sensors =3D <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + mdm-core-thermal { + thermal-sensors =3D <&tsens 1>; + + trips { + mdm_core_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + q6-thermal { + thermal-sensors =3D <&tsens 2>; + + trips { + q6_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors =3D <&tsens 4>; + + cooling-maps { + map0 { + trip =3D <&cpuss1_alert0>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpuss1_crit: cpuss1-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + thermal-sensors =3D <&tsens 5>; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu4_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + thermal-sensors =3D <&tsens 6>; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu5_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + thermal-sensors =3D <&tsens 7>; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu6_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + thermal-sensors =3D <&tsens 8>; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert1>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu7_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors =3D <&tsens 9>; + + cooling-maps { + map0 { + trip =3D <&cpuss0_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpuss0_crit: cpuss0-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 10>; + + cooling-maps { + map0 { + trip =3D <&gpu_alert>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert: trip-point0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_crit: gpu-crit { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; + --=20 2.51.0 From nobody Fri Oct 3 13:30:15 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F4B3263892; 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Add qcom,msm8937 for msm-id, board-id allow-list. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 55e5eb75af8905c93e6604d54d516585f70a8e29..16e003ef0e1892cf8b1d2e5c581= 358e344b46349 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -191,6 +191,11 @@ properties: - xiaomi,riva - const: qcom,msm8917 =20 + - items: + - enum: + - xiaomi,land + - const: qcom,msm8937 + - items: - enum: - motorola,potter @@ -1153,6 +1158,7 @@ allOf: - qcom,apq8094 - qcom,apq8096 - qcom,msm8917 + - qcom,msm8937 - qcom,msm8939 - qcom,msm8953 - qcom,msm8956 --=20 2.51.0 From nobody Fri Oct 3 13:30:15 2025 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0966625EF9C; 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DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=To:Message-Id:Subject:Date:From; t=1756643383; bh=PhlYyLCSQI1w4nlhX5YFydD ascZlczZAAO/YONVQlCY=; b=ioQgVFhDYQ+ZB+HQP2yAjfw9O1oPxc/OzKLNJfkwOouUYt2w11 remniCsci6dHMiP/i/AhGMsoEqZUdw8QOLDQ==; From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sun, 31 Aug 2025 14:29:30 +0200 Subject: [PATCH v8 7/7] arm64: dts: qcom: Add Xiaomi Redmi 3S Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250831-msm8937-v8-7-b7dcd63caaac@mainlining.org> References: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> In-Reply-To: <20250831-msm8937-v8-0-b7dcd63caaac@mainlining.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephan Gerhold , =?utf-8?q?Otto_Pfl=C3=BCger?= , Linus Walleij , Lee Jones , Joerg Roedel , Will Deacon , Robin Murphy , Konrad Dybcio , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Jessica Zhang , Robert Marko , Das Srinagesh , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux@mainlining.org, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756643366; l=9618; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=k9YfYoLnWgowizoNFCgdYGssyc1KlF97HQd/e1o9DWU=; b=hisi954ptrX31vJkEQccti1zAm7jKjEIiBu1CChOhRxA1ps3UKBBNHKE0tZsSvH3mv1rDY691 dXzxl/kjcAhAgP40rhhPVWwcnlcKT5WP7B/pMiYsr6WXzNtSb0cqr+w X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add initial support for Xiaomi Redmi 3S (land). Reviewed-by: Konrad Dybcio Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts | 381 +++++++++++++++++++= ++++ 2 files changed, 382 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 94a84770b0802a9dc0c56ce6c59eea20967a5d89..0476a87636584216ba359714ab4= 6a6f085620286 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8917-xiaomi-riva.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8929-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8937-xiaomi-land.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-huawei-kiwi.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-longcheer-l9100.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-samsung-a7.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts b/arch/arm64/= boot/dts/qcom/msm8937-xiaomi-land.dts new file mode 100644 index 0000000000000000000000000000000000000000..91837ff940f1b6b13a9ef519519= f471a7a4cdac0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Barnabas Czeman + */ +/dts-v1/; + +#include +#include +#include + +#include "msm8937.dtsi" +#include "pm8937.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model =3D "Xiaomi Redmi 3S (land)"; + compatible =3D "xiaomi,land", "qcom,msm8937"; + chassis-type =3D "handset"; + + qcom,msm-id =3D ; + qcom,board-id =3D <0x1000b 1>, <0x2000b 1>; + + aliases { + mmc0 =3D &sdhc_1; + mmc1 =3D &sdhc_2; + }; + + battery: battery { + compatible =3D "simple-battery"; + + charge-full-design-microamp-hours =3D <4100000>; + constant-charge-current-max-microamp =3D <1000000>; + voltage-min-design-microvolt =3D <3400000>; + voltage-max-design-microvolt =3D <4400000>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "framebuffer0"; + + framebuffer0: framebuffer@8dd01000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + width =3D <720>; + height =3D <1280>; + stride =3D <(720 * 3)>; + format =3D "r8g8b8"; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains =3D <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&gpio_keys_default>; + pinctrl-names =3D "default"; + + key-volup { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + irled { + compatible =3D "gpio-ir-tx"; + gpios =3D <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; + + reserved-memory { + reserved@84a00000 { + reg =3D <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer: memory@8dd01000 { + reg =3D <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c2 { + status =3D "okay"; + + led-controller@45 { + compatible =3D "awinic,aw2013"; + reg =3D <0x45>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + vcc-supply =3D <&pm8937_l10>; + vio-supply =3D <&pm8937_l5>; + + led@0 { + reg =3D <0>; + function =3D LED_FUNCTION_STATUS; + led-max-microamp =3D <5000>; + color =3D ; + }; + + led@1 { + reg =3D <1>; + function =3D LED_FUNCTION_STATUS; + led-max-microamp =3D <5000>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + function =3D LED_FUNCTION_STATUS; + led-max-microamp =3D <5000>; + color =3D ; + }; + }; +}; + +&blsp1_i2c3 { + status =3D "okay"; + + touchscreen@3e { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x3e>; + + interrupts-extended =3D <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&pm8937_l10>; + iovcc-supply =3D <&pm8937_l5>; + + pinctrl-0 =3D <&tsp_int_rst_default>; + pinctrl-names =3D "default"; + + touchscreen-size-x =3D <720>; + touchscreen-size-y =3D <1280>; + }; +}; + +&pm8937_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pm8937_spmi_regulators { + /* APC */ + pm8937_s5: s5 { + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pmi8950_wled { + qcom,num-strings =3D <2>; + qcom,external-pfet; + qcom,current-limit-microamp =3D <20000>; + qcom,ovp-millivolt =3D <29600>; + + status =3D "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible =3D "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + + vdd_l1_l19-supply =3D <&pm8937_s3>; + vdd_l2_l23-supply =3D <&pm8937_s3>; + vdd_l3-supply =3D <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply =3D <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply =3D <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + regulator-allow-set-load; + regulator-system-load =3D <200000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt =3D <1225000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; +}; + +&sdc2_cmd_default { + drive-strength =3D <12>; +}; + +&sdc2_data_default { + drive-strength =3D <12>; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8937_l8>; + vqmmc-supply =3D <&pm8937_l5>; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&pm8937_l11>; + vqmmc-supply =3D <&pm8937_l12>; + pinctrl-0 =3D <&sdc2_default &sdc2_cd_default>; + pinctrl-1 =3D <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>, <20 4>; + + gpio_keys_default: gpio-keys-default-state { + pins =3D "gpio91"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins =3D "gpio64", "gpio65"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; +}; + +&wcnss { + vddpx-supply =3D <&pm8937_l5>; + + status =3D "okay"; +}; + +&wcnss_iris { + compatible =3D "qcom,wcn3620"; + vddxo-supply =3D <&pm8937_l7>; + vddrfa-supply =3D <&pm8937_l19>; + vddpa-supply =3D <&pm8937_l9>; + vdddig-supply =3D <&pm8937_l5>; +}; + +&wcnss_mem { + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <19200000>; +}; --=20 2.51.0