From nobody Fri Oct 3 14:42:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FF002D6406; Sat, 30 Aug 2025 17:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; cv=none; b=er8lLiGO3ET4gDXWXetN3Sgl0bSF3fqhlVFR1o0MIBf+OOJkDe/BVH6behHsuI25hEYvOqPrqrLNCwb+bQo0av23Oir7KkFbmIAcHsTZvrSnu9JliMWaVd5rjBcEoLS5q5BoBYosR1ZSVzwzuX6C/qhHIJcQ29xZ1y34fgRbuzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; c=relaxed/simple; bh=X9UravRZTkYO/S1t31DyRCOSep0v8TZbjoIrBK1EKNA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NzP0q4eJPn42+F8X/8O0wvkeh4/Odjs9JnY+Il498DokVmJ2id7GAfGDe4j9NTJj+Cx7b01OclVvDj0zzTi9nS0BO7iADToHCLp70DIhFr6rc+Xd9ANjvU6QUqPNk+uZ0xpvAO1LKSjAjHyMNLVizJAoECSo8XZbiWeKmuiNUWE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iwFLUfxl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iwFLUfxl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E84C8C4CEF8; Sat, 30 Aug 2025 17:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756573762; bh=X9UravRZTkYO/S1t31DyRCOSep0v8TZbjoIrBK1EKNA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iwFLUfxlJFRuEDCHufRML+UIZZxkrkNLuW9Jorcc8xsw9v1WoDX0KJAJ8NHXNMfk+ yh/ifCmuennI9zj0KjV/5voVETLt/qc+ZxPVJ5xAZ2vSPBfijwsMjXdF8p9agJMWpD k2nwhPQEotMppPXpGxzPrFxKQmaEoTvdbZq6DFEFbQIwvI7PIpEshjdgXOsI7CHavy YUhA2F4y1pxYWGxRhGNu8u5b5aSp/NhW8ib3aRF/FZDXZHJrel6uweKlQtTXbsJJmf avfDBFenDBvxkH7gnmYNXvNWFt5CmAb3+SLuz8cv2PTAe/B/3noF205eW3jxwRoJuz KlphCMUjLomaA== Received: by wens.tw (Postfix, from userid 1000) id 78ADF5FF44; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] arm64: dts: allwinner: a523: Add NPU device node Date: Sun, 31 Aug 2025 01:09:01 +0800 Message-Id: <20250830170901.1996227-9-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner T527 SoC has an NPU built in. Based on identifiers found in the BSP, it is a Vivante IP block. After enabling it, the etnaviv driver reports it as a GC9000 revision 9003. The standard bindings are used as everything matches directly. There is no option for DVFS at the moment. That might require some more work, perhaps on the efuse side to map speed bins. It is unclear whether the NPU block is fused out at the hardware level or the BSP limits use of the NPU through software, as the author only has boards with the T527. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index b6e82d53af54..1ab5b87ec78e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -850,6 +850,18 @@ mcu_ccu: clock-controller@7102000 { #clock-cells =3D <1>; #reset-cells =3D <1>; }; + + npu: npu@7122000 { + compatible =3D "vivante,gc"; + reg =3D <0x07122000 0x1000>; + interrupts =3D ; + clocks =3D <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, + <&ccu CLK_NPU>, + <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; + clock-names =3D "bus", "core", "reg"; + resets =3D <&mcu_ccu RST_BUS_MCU_NPU>; + power-domains =3D <&ppu PD_NPU>; + }; }; =20 thermal-zones { --=20 2.39.5