From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 241B32D027E; Sat, 30 Aug 2025 17:09:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573760; cv=none; b=KWpQnNctJ8wNzHdnLhn+Ta2E/jlNCJD5HRXotIb8r742dkRk7xV0mH9TBS6buTzYo8gZovhwUacOAcAZkD+rK22DsAFibRhHcoyxN3/JbxFENTaHFv+4S2D1BxoNs0MgBazPq+hQ0eQgPSSkjh90L2lYwfOLLjOkFTFQicfxP2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573760; c=relaxed/simple; bh=u+4gHkt5DXNrjLXkvTpfwwb6DKaKcxGOlqkLQ/0Gubc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lghQ5Va4iSZuREctEt8HgBuyVq3GGlnkI9aNfLCC+ivwvBkc/b+wxB28SqcttLVK/4cxwa2sv/yJsSIzW1u/Yu769KzobIksMs/q3QCQ7e30S8tCZibYnFKFm8SbZwdPV01ece2NybgOUBTtDy1rJse+vHpATs0eggYkpafRb2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I4ferjS0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I4ferjS0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A0378C4CEEB; Sat, 30 Aug 2025 17:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756573759; bh=u+4gHkt5DXNrjLXkvTpfwwb6DKaKcxGOlqkLQ/0Gubc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I4ferjS0lWDaRDEPSigpfpZXcn1ecAQ4cv3cFgwhBBCG2vX1kOc45QAnqBpUwdVq9 c3v44Y514Aw0hG7KECWZeN6eT4E2F65t7NZ+0tnWQkbD/ZDqHM7HibVSUasgoadxa/ uxHudqTidIvqbjllVV4lP0TOZRN8YZHXkDSUnRxNBCZ+TX5xilo9HoBYy76ii41tCu KbP5/fRr1EDXUInEbNNKJBUTbPPgfAu7ENnVUUFNfLKAFwPVHUxW/Pg5lPwlkOqZAE vrNi0me373DjR7oHTJUqmLTEgRr7GT/uMoikO86PZ0bYpnWKqMD4vfp0UYFgmobLMw fnUkdpeZUMxaw== Received: by wens.tw (Postfix, from userid 1000) id 2686B5FA73; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock Date: Sun, 31 Aug 2025 01:08:54 +0800 Message-Id: <20250830170901.1996227-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring (Arm) Reviewed-by: Andre Przywara --- include/dt-bindings/clock/sun55i-a523-ccu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindi= ngs/clock/sun55i-a523-ccu.h index c8259ac5ada7..54808fcfd556 100644 --- a/include/dt-bindings/clock/sun55i-a523-ccu.h +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -185,5 +185,6 @@ #define CLK_FANOUT0 176 #define CLK_FANOUT1 177 #define CLK_FANOUT2 178 +#define CLK_NPU 179 =20 #endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ --=20 2.39.5 From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2421E2D060D; Sat, 30 Aug 2025 17:09:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573760; cv=none; b=CUyjHf0NYaJduxpnhUGD+fhJuZPYvqd+bwGCz1+3+vlcBjMdpdf9OmlBCyD949LcThhycgrZ0G+0NA4fx0482E8FZeCTIHLS0MKcXoHUojW5aH+BTtwonL9MnWLx1W1CADgB//FbYJrdXCmNYjyidsvA7mt7FQOu8ABJ3/OSo8E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573760; c=relaxed/simple; bh=2D4JpcfBxGUxLuSlwCEqmVQw8YDexdFZl9b/63oO114=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n1YmHYNsHi5BHjwFA8Ti9a0yb4nmzbTIudhbs020HhKDouMxWraie01vYcTpsbmByvT1nT66i7F+9wmmcKMGXTvOgpD1CY8hWdnue7alx5zTVe9UqSV0x+pS+9EW8+Si9bX6sfnc4v5/meB+zGmv6CPQh+L7LHkQo9JR0DFJCFY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TFywBZj6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TFywBZj6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A21DFC4CEF1; Sat, 30 Aug 2025 17:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756573759; bh=2D4JpcfBxGUxLuSlwCEqmVQw8YDexdFZl9b/63oO114=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TFywBZj6Tmfjggcn4jcDCinw54P3REEoPmefMj2Vq9QQT+Yjyd5XZHo3GWBzl7SnE qq5YRSDIhC2iX3xXlIufp/do1mDtA9BQH43mFH9X9LAPrSRFDjMDBpPLQ0A+dUZbjX LRCt42TMJXRp325d0CWUAWR4yjLn7lW8vWxm7ADj4YhEc/abCaaII5qE2h3dR2/lAF SvWQsF6eldWAyQRFh5n8nzt7yy0kejonLJxS/8f9Pe80U34kUTBxN/kjpvnz+ELzDM oP6dUNwo7NgvXeLbg6X29/TP5Zv91+Fr6Hr8pUcTZkPSGnh1RKBrnk875F0Pwncwme g2n0WxZoCB1/A== Received: by wens.tw (Postfix, from userid 1000) id 356675FD50; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller Date: Sun, 31 Aug 2025 01:08:55 +0800 Message-Id: <20250830170901.1996227-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Signed-off-by: Chen-Yu Tsai Reviewed-by: Rob Herring (Arm) --- .../clock/allwinner,sun55i-a523-ccu.yaml | 35 +++++++++++- .../dt-bindings/clock/sun55i-a523-mcu-ccu.h | 54 +++++++++++++++++++ .../dt-bindings/reset/sun55i-a523-mcu-ccu.h | 30 +++++++++++ 3 files changed, 117 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/sun55i-a523-mcu-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-mcu-ccu.h diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-= ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-cc= u.yaml index f5f62e9a10a1..1dbd92febc47 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-mcu-ccu - allwinner,sun55i-a523-r-ccu =20 reg: @@ -26,11 +27,11 @@ properties: =20 clocks: minItems: 4 - maxItems: 5 + maxItems: 8 =20 clock-names: minItems: 4 - maxItems: 5 + maxItems: 8 =20 required: - "#clock-cells" @@ -63,6 +64,36 @@ allOf: - const: iosc - const: losc-fanout =20 + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-mcu-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Audio PLL (4x) + - description: Peripherals PLL 0 (300 MHz output) + - description: DSP module clock + - description: PRCM AHB clock + - description: MBUS clock + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-audio0-4x + - const: pll-periph0-300m + - const: dsp + - const: r-ahb + - const: mbus + - if: properties: compatible: diff --git a/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h b/include/dt-b= indings/clock/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..6efc6bc7e11a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ + +#define CLK_MCU_PLL_AUDIO1 0 +#define CLK_MCU_PLL_AUDIO1_DIV2 1 +#define CLK_MCU_PLL_AUDIO1_DIV5 2 +#define CLK_MCU_AUDIO_OUT 3 +#define CLK_MCU_DSP 4 +#define CLK_MCU_I2S0 5 +#define CLK_MCU_I2S1 6 +#define CLK_MCU_I2S2 7 +#define CLK_MCU_I2S3 8 +#define CLK_MCU_I2S3_ASRC 9 +#define CLK_BUS_MCU_I2S0 10 +#define CLK_BUS_MCU_I2S1 11 +#define CLK_BUS_MCU_I2S2 12 +#define CLK_BUS_MCU_I2S3 13 +#define CLK_MCU_SPDIF_TX 14 +#define CLK_MCU_SPDIF_RX 15 +#define CLK_BUS_MCU_SPDIF 16 +#define CLK_MCU_DMIC 17 +#define CLK_BUS_MCU_DMIC 18 +#define CLK_MCU_AUDIO_CODEC_DAC 19 +#define CLK_MCU_AUDIO_CODEC_ADC 20 +#define CLK_BUS_MCU_AUDIO_CODEC 21 +#define CLK_BUS_MCU_DSP_MSGBOX 22 +#define CLK_BUS_MCU_DSP_CFG 23 +#define CLK_BUS_MCU_NPU_HCLK 24 +#define CLK_BUS_MCU_NPU_ACLK 25 +#define CLK_MCU_TIMER0 26 +#define CLK_MCU_TIMER1 27 +#define CLK_MCU_TIMER2 28 +#define CLK_MCU_TIMER3 29 +#define CLK_MCU_TIMER4 30 +#define CLK_MCU_TIMER5 31 +#define CLK_BUS_MCU_TIMER 32 +#define CLK_BUS_MCU_DMA 33 +#define CLK_MCU_TZMA0 34 +#define CLK_MCU_TZMA1 35 +#define CLK_BUS_MCU_PUBSRAM 36 +#define CLK_MCU_MBUS_DMA 37 +#define CLK_MCU_MBUS 38 +#define CLK_MCU_RISCV 39 +#define CLK_BUS_MCU_RISCV_CFG 40 +#define CLK_BUS_MCU_RISCV_MSGBOX 41 +#define CLK_MCU_PWM0 42 +#define CLK_BUS_MCU_PWM0 43 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h b/include/dt-b= indings/reset/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..a89a0b44f08b --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ + +#define RST_BUS_MCU_I2S0 0 +#define RST_BUS_MCU_I2S1 1 +#define RST_BUS_MCU_I2S2 2 +#define RST_BUS_MCU_I2S3 3 +#define RST_BUS_MCU_SPDIF 4 +#define RST_BUS_MCU_DMIC 5 +#define RST_BUS_MCU_AUDIO_CODEC 6 +#define RST_BUS_MCU_DSP_MSGBOX 7 +#define RST_BUS_MCU_DSP_CFG 8 +#define RST_BUS_MCU_NPU 9 +#define RST_BUS_MCU_TIMER 10 +#define RST_BUS_MCU_DSP_DEBUG 11 +#define RST_BUS_MCU_DSP 12 +#define RST_BUS_MCU_DMA 13 +#define RST_BUS_MCU_PUBSRAM 14 +#define RST_BUS_MCU_RISCV_CFG 15 +#define RST_BUS_MCU_RISCV_DEBUG 16 +#define RST_BUS_MCU_RISCV_CORE 17 +#define RST_BUS_MCU_RISCV_MSGBOX 18 +#define RST_BUS_MCU_PWM0 19 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ */ --=20 2.39.5 From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No 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Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/8] clk: sunxi-ng: mp: Fix dual-divider clock rate readback Date: Sun, 31 Aug 2025 01:08:56 +0800 Message-Id: <20250830170901.1996227-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai When dual-divider clock support was introduced, the P divider offset was left out of the .recalc_rate readback function. This causes the clock rate to become bogus or even zero (possibly due to the P divider being 1, leading to a divide-by-zero). Fix this by incorporating the P divider offset into the calculation. Fixes: 45717804b75e ("clk: sunxi-ng: mp: introduce dual-divider clock") Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu_mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c index 354c981943b6..4221b1888b38 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.c +++ b/drivers/clk/sunxi-ng/ccu_mp.c @@ -185,7 +185,7 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *= hw, p &=3D (1 << cmp->p.width) - 1; =20 if (cmp->common.features & CCU_FEATURE_DUAL_DIV) - rate =3D (parent_rate / p) / m; + rate =3D (parent_rate / (p + cmp->p.offset)) / m; else rate =3D (parent_rate >> p) / m; =20 --=20 2.39.5 From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42B692D063B; Sat, 30 Aug 2025 17:09:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573760; cv=none; b=DrmZCSqDHtBPjedvpBdeF2OSHJgdyTJKHD6z7BjC8KBXJAn9ioOQylS41Lew3UghTzip+K65NdiDEhf8WT0p3tXVLJCle+E52T4sJKX3b6Ja5Uln1wtoUF7yLuZUMzJgu4cIlEv0nBmSLtLPjtj5rbvksyRysSEPj+M4/ax/YmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573760; c=relaxed/simple; bh=4OLevTh3b36nlwjrJIA5aTqk2G4cIdcN5We4TCuVE+w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Wmsxp9ANtBM8qs9I9xLGe4YMKwL1mfpDiQ1VhCPm4zF5WYyaaLdMmtISnhkWa/Mb7eJEEqeoawTONGEIIbBWwaVbRBQwHPxqol/4cPOlpD+ryNx7q1ThB4X3D1qiaKW/foYM0LBWoIrfp/OVw/AlU9XjKfhr6T/dWbZLkqt2n9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ADz7qX1H; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ADz7qX1H" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ABF3FC4CEF7; Sat, 30 Aug 2025 17:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756573759; bh=4OLevTh3b36nlwjrJIA5aTqk2G4cIdcN5We4TCuVE+w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ADz7qX1HOjj4VOTKZPo4teWE33XK3WTl1vO6KNwr1cBCxvr+seHz8DnXJl4MkXDKk jqW2I37Pfmj2GdypwtLGPj7gORCCqzEHwlgMvyRI7h8ocNjZAuprP+RsP3cq+z8OYb 3SlPfqH0yZVY3+uOvNK7G9qYylSsVaX0y9Wh1ktILv90gY98Ef98+IjxMlAM3SFUia xxB04Boc7KyZm9CUjUIDmKnZ+vJaQ/MPof/zglnGp9SfwwQFip29IUYt7mvoWbd2uQ /3k3DqVkDgT7T8MDFe+YHtlLxN/7OAT72xdSAJ+1EOoOvkm9g3AU0NUOjARDcuAQDN 4K/nqAjoNW7+Q== Received: by wens.tw (Postfix, from userid 1000) id 4EFF15FD53; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock Date: Sun, 31 Aug 2025 01:08:57 +0800 Message-Id: <20250830170901.1996227-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Also, merge the private header back into the driver code itself. The header only contains a macro containing the total number of clocks. This has to be updated every time a missing clock gets added. Having it in a separate file doesn't help the process. Instead just drop the macro, and thus the header no longer has any reason to exist. Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 21 ++++++++++++++++++--- drivers/clk/sunxi-ng/ccu-sun55i-a523.h | 14 -------------- 2 files changed, 18 insertions(+), 17 deletions(-) delete mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523.h diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 1a9a1cb869e2..88405b624dc5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -11,6 +11,9 @@ #include #include =20 +#include +#include + #include "../clk.h" =20 #include "ccu_common.h" @@ -25,8 +28,6 @@ #include "ccu_nkmp.h" #include "ccu_nm.h" =20 -#include "ccu-sun55i-a523.h" - /* * The 24 MHz oscillator, the root of most of the clock tree. * .fw_name is the string used in the DT "clock-names" property, used to @@ -486,6 +487,18 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_p= arents, 0x690, =20 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0); =20 +static const struct clk_hw *npu_parents[] =3D { + &pll_periph0_480M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_800M_clk.common.hw, + &pll_npu_2x_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), = 0); =20 static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c, @@ -1217,6 +1230,7 @@ static struct ccu_common *sun55i_a523_ccu_clks[] =3D { &bus_ce_sys_clk.common, &ve_clk.common, &bus_ve_clk.common, + &npu_clk.common, &bus_dma_clk.common, &bus_msgbox_clk.common, &bus_spinlock_clk.common, @@ -1343,7 +1357,7 @@ static struct ccu_common *sun55i_a523_ccu_clks[] =3D { }; =20 static struct clk_hw_onecell_data sun55i_a523_hw_clks =3D { - .num =3D CLK_NUMBER, + .num =3D CLK_NPU + 1, .hws =3D { [CLK_PLL_DDR0] =3D &pll_ddr_clk.common.hw, [CLK_PLL_PERIPH0_4X] =3D &pll_periph0_4x_clk.common.hw, @@ -1524,6 +1538,7 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks= =3D { [CLK_FANOUT0] =3D &fanout0_clk.common.hw, [CLK_FANOUT1] =3D &fanout1_clk.common.hw, [CLK_FANOUT2] =3D &fanout2_clk.common.hw, + [CLK_NPU] =3D &npu_clk.common.hw, }, }; =20 diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.h deleted file mode 100644 index fc8dd42f1b47..000000000000 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2024 Arm Ltd. - */ - -#ifndef _CCU_SUN55I_A523_H -#define _CCU_SUN55I_A523_H - -#include -#include - -#define CLK_NUMBER (CLK_FANOUT2 + 1) - -#endif /* _CCU_SUN55I_A523_H */ --=20 2.39.5 From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA7BF2D7813; Sat, 30 Aug 2025 17:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573763; cv=none; b=tyZux9xXh6dkF8379UQbaKiEl/JSxA27UzV2cbqsgpaDmCi6/Hdoq72ufAF7dP8mi4vbcxwuzM7cSogK+Q7pjoV0L6LCjEiptu4ujA5n04snBG5x4l9yml33d3U+zNUT8SZrX8+7MDf1HFrqXp4rzCfCJ0D+Y2CtN7rBdR4DFF0= ARC-Message-Signature: i=1; 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b=vI83iiQZBW4XV+q5tHTOwmQ1UKfYiLXsk0MMtdOuCQ9ZbneFFI3fw89x+rrjWm42X QxJVdB+b/kND+DX3O/zobvZZ6DgTCvc5nqw7dRXvYknALf8gHzwb8b0KDAM9oRbXp8 DTM8frvOfBj+awY3OsDoQZjOJeQDbnTxXIpbco6C3SrQtYEcAsNXwzLiVIQHV6VcWl B3qDoc+ODPjbq/o6YT4lG+uj2LNChj9BCdBR5I8IZPHNT4BFZpC2vEUPdZyrHGX2/h vgJ23Gx71wOtQK5AphGRUjaFMkE9RjX0/eztrdX79rkAD9Y4RHtXX8nE6c8o4lHtvc rNCtz6f+mL0TQ== Received: by wens.tw (Postfix, from userid 1000) id 6AA495FDD4; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/8] clk: sunxi-ng: div: support power-of-two dividers Date: Sun, 31 Aug 2025 01:08:58 +0800 Message-Id: <20250830170901.1996227-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai Some clocks (for timers) on the A523 are mux-divider-gate types with the divider being values of power-of-two. Add a macro for these types of clocks so that we can use the divider types instead of the M-P types without an M divider. Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu_div.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 90d49ee8e0cc..be00b3277e97 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -274,6 +274,24 @@ struct ccu_div { SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \ _mshift, _mwidth, 0, _flags) =20 +#define SUNXI_CCU_P_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_div _struct =3D { \ + .enable =3D _gate, \ + .div =3D _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth, \ + CLK_DIVIDER_POWER_OF_TWO), \ + .mux =3D _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ + .common =3D { \ + .reg =3D _reg, \ + .hw.init =3D CLK_HW_INIT_PARENTS_DATA(_name, \ + _parents, \ + &ccu_div_ops, \ + _flags), \ + }, \ + } + static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) { struct ccu_common *common =3D hw_to_ccu_common(hw); --=20 2.39.5 From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 873062D6E60; Sat, 30 Aug 2025 17:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; cv=none; b=YAU1FV7AbcoQFUVSlJ21tSB9q7g4aE/MfmdV3EAr6EHUlCx4ARX7QmT0mM9DZh6ssVaw6Yn/e2AWkAEXrx6gE6LF1okIEfizPQzHXVWwrCthel+FiGtS3OD0iGy0uvZ3lwOGhD3bZ6RzBWwqA684RfBctvj+4Ap1fo0tywo0iDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; c=relaxed/simple; bh=Bmy8Qmfkl+J8uq23YjuAmbR73gd/F3hjfU1RB5uUFPc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UmjkKu6nY9dMneNWeSybs9akHi2zdvYH7nVRWe2/kGv5dJ88k8nM59NZoTXnq52Lkn9ZYuju6UBbE+nIK6bMUeQq2k+fyyvo9WzKnmjk9HClj+RU5VOrwEdpoC4I0xfX7EbmNBUrdILm/j5Ecaf4a57BSaZHy7jkxFx6AXl5cbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=r7Zqwe2G; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="r7Zqwe2G" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C04E7C4CEFA; Sat, 30 Aug 2025 17:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756573762; bh=Bmy8Qmfkl+J8uq23YjuAmbR73gd/F3hjfU1RB5uUFPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r7Zqwe2GhWPYrIEy/pXGurvLrW8i32UhgfvJpqoKd0PwpG3mhOi2bi/mGjT6MlxJ0 bS9T8tQgKv7BbqPHaNPJqRQLpP5UBke/YkZqDB3/N5XhM8nELpTazkg7pp37p4nPxr 7Hr7RNwrmyOViL7oXb22Li+x/zomso7r9xxVS0ydq44qa+A51x87HLt/gVJ4PFAoIA YoRqcDlXWjy07lXp6earXSCSvbLfhqcjfoMnEpb51/55JV1AnoDbg7WlrqQejBd/UG B1IFTsxf2FPKE/ROE1s23NLdkF0L+mk05spB9E3ZHjYluIAhxKZXjiGmngX/Q99uOB MTa6GZ4p5AVrA== Received: by wens.tw (Postfix, from userid 1000) id 6D8225FEB3; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] clk: sunxi-ng: add support for the A523/T527 MCU CCU Date: Sun, 31 Aug 2025 01:08:59 +0800 Message-Id: <20250830170901.1996227-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset controls for the RISC-V MCU and other peripherals. There is no visible bus in this part, but there is a second audio PLL. The BSP driver uses the 24MHz main oscillator as the parent for all the bus clocks. Add a driver to support this part. Unlike the BSP driver, the SoC's main MBUS clock is chosen as the parent for the MCU MBUS clock, and the latter then serves as the parent of the MCU DMA controller's MBUS clock. Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c | 447 +++++++++++++++++++++ 3 files changed, 454 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8896fd052ef1..6af2d020e03e 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -57,6 +57,11 @@ config SUN55I_A523_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 +config SUN55I_A523_MCU_CCU + tristate "Support for the Allwinner A523/T527 MCU CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN55I_A523_R_CCU tristate "Support for the Allwinner A523/T527 PRCM CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 82e471036de6..a1c4087d7241 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SUN50I_H6_CCU) +=3D sun50i-h6-ccu.o obj-$(CONFIG_SUN50I_H6_R_CCU) +=3D sun50i-h6-r-ccu.o obj-$(CONFIG_SUN50I_H616_CCU) +=3D sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) +=3D sun55i-a523-ccu.o +obj-$(CONFIG_SUN55I_A523_MCU_CCU) +=3D sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) +=3D sun55i-a523-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) +=3D sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) +=3D sun5i-ccu.o @@ -61,6 +62,7 @@ sun50i-h6-ccu-y +=3D ccu-sun50i-h6.o sun50i-h6-r-ccu-y +=3D ccu-sun50i-h6-r.o sun50i-h616-ccu-y +=3D ccu-sun50i-h616.o sun55i-a523-ccu-y +=3D ccu-sun55i-a523.o +sun55i-a523-mcu-ccu-y +=3D ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y +=3D ccu-sun55i-a523-r.o sun4i-a10-ccu-y +=3D ccu-sun4i-a10.o sun5i-ccu-y +=3D ccu-sun5i.o diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c b/drivers/clk/sunxi= -ng/ccu-sun55i-a523-mcu.c new file mode 100644 index 000000000000..6105485837c9 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Chen-Yu Tsai + * + * Based on the A523 CCU driver: + * Copyright (C) 2023-2024 Arm Ltd. + */ + +#include +#include +#include +#include + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nm.h" + +static const struct clk_parent_data osc24M[] =3D { + { .fw_name =3D "hosc" } +}; + +#define SUN55I_A523_PLL_AUDIO1_REG 0x00c +static struct ccu_sdm_setting pll_audio1_sdm_table[] =3D { + { .rate =3D 2167603200, .pattern =3D 0xa000a234, .m =3D 1, .n =3D 90 }, /= * div2->22.5792 */ + { .rate =3D 2359296000, .pattern =3D 0xa0009ba6, .m =3D 1, .n =3D 98 }, /= * div2->24.576 */ + { .rate =3D 1806336000, .pattern =3D 0xa000872b, .m =3D 1, .n =3D 75 }, /= * div5->22.576 */ +}; + +static struct ccu_nm pll_audio1_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), + .sdm =3D _SUNXI_CCU_SDM(pll_audio1_sdm_table, BIT(24), + 0x010, BIT(31)), + .min_rate =3D 180000000U, + .max_rate =3D 3500000000U, + .common =3D { + .reg =3D 0x00c, + .features =3D CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("pll-audio1", + osc24M, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_audio1_div_parents[] =3D { &pll_audio1_clk= .common.hw }; +static CLK_FIXED_FACTOR_HWS(pll_periph1_div2_clk, "pll-audio1-div2", + pll_audio1_div_parents, 2, 1, + CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR_HWS(pll_periph1_div5_clk, "pll-audio1-div5", + pll_audio1_div_parents, 5, 1, + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_GATE(audio_out_clk, "audio-out", + "pll-audio1-div2", 0x01c, + 0, 5, BIT(31), CLK_SET_RATE_PARENT); + +static const struct clk_parent_data dsp_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .hw =3D &pll_periph1_div5_clk.hw }, + { .hw =3D &pll_periph1_div2_clk.hw }, + { .fw_name =3D "dsp" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "mcu-dsp", dsp_parents, 0x0= 020, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data i2s_parents[] =3D { + { .fw_name =3D "pll-audio0-4x" }, + { .hw =3D &pll_periph1_div2_clk.hw }, + { .hw =3D &pll_periph1_div5_clk.hw }, +}; + +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s0_clk, "i2s0", i2s_parents, 0x02c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s1_clk, "i2s1", i2s_parents, 0x030, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s2_clk, "i2s2", i2s_parents, 0x034, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_clk, "i2s3", i2s_parents, 0x038, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_parent_data i2s3_asrc_parents[] =3D { + { .fw_name =3D "pll-periph0-300m" }, + { .hw =3D &pll_periph1_div2_clk.hw }, + { .hw =3D &pll_periph1_div5_clk.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_asrc_clk, "i2s3-asrc", + i2s3_asrc_parents, 0x038, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_i2s0_clk, "bus-i2s0", osc24M, 0x040, BIT(0)= , 0); +static SUNXI_CCU_GATE_DATA(bus_i2s1_clk, "bus-i2s1", osc24M, 0x040, BIT(1)= , 0); +static SUNXI_CCU_GATE_DATA(bus_i2s2_clk, "bus-i2s2", osc24M, 0x040, BIT(2)= , 0); +static SUNXI_CCU_GATE_DATA(bus_i2s3_clk, "bus-i2s3", osc24M, 0x040, BIT(3)= , 0); + +static const struct clk_parent_data audio_parents[] =3D { + { .fw_name =3D "pll-audio0-4x" }, + { .hw =3D &pll_periph1_div2_clk.hw }, + { .hw =3D &pll_periph1_div5_clk.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_tx_clk, "spdif-tx", + audio_parents, 0x044, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_rx_clk, "spdif-rx", + i2s3_asrc_parents, 0x048, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_spdif_clk, "bus-spdif", osc24M, 0x04c, BIT(= 0), 0); + +static SUNXI_CCU_DUALDIV_MUX_GATE(dmic_clk, "dmic", audio_parents, 0x050, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_dmic_clk, "bus-dmic", osc24M, 0x054, BIT(0)= , 0); + +static SUNXI_CCU_DUALDIV_MUX_GATE(audio_dac_clk, "audio-dac", + audio_parents, 0x058, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(audio_adc_clk, "audio-adc", + audio_parents, 0x05c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_audio_codec_clk, "bus-audio-codec", + osc24M, 0x060, BIT(0), 0); + +static SUNXI_CCU_GATE_DATA(bus_dsp_msgbox_clk, "bus-dsp-msgbox", + osc24M, 0x068, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_dsp_cfg_clk, "bus-dsp-cfg", + osc24M, 0x06c, BIT(0), 0); + +static SUNXI_CCU_GATE_DATA(bus_npu_hclk, "bus-npu-hclk", osc24M, 0x070, BI= T(1), 0); +static SUNXI_CCU_GATE_DATA(bus_npu_aclk, "bus-npu-aclk", osc24M, 0x070, BI= T(2), 0); + +static const struct clk_parent_data timer_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "r-ahb" } +}; +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer0_clk, "mcu-timer0", timer_= parents, + 0x074, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer1_clk, "mcu-timer1", timer_= parents, + 0x078, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer2_clk, "mcu-timer2", timer_= parents, + 0x07c, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer3_clk, "mcu-timer3", timer_= parents, + 0x080, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer4_clk, "mcu-timer4", timer_= parents, + 0x084, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer5_clk, "mcu-timer5", timer_= parents, + 0x088, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_timer_clk, "bus-mcu-timer", osc24M, 0x0= 8c, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_dma_clk, "bus-mcu-dma", osc24M, 0x104, = BIT(0), 0); +static SUNXI_CCU_GATE_DATA(tzma0_clk, "tzma0", osc24M, 0x108, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(tzma1_clk, "tzma1", osc24M, 0x10c, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_pubsram_clk, "bus-pubsram", osc24M, 0x114, = BIT(0), 0); + +/* + * user manual has "mbus" clock as parent of both clocks below, + * but this makes more sense, since BSP MCU DMA controller has + * reference to both of them, likely needing both enabled. + */ +static SUNXI_CCU_GATE_FW(mbus_mcu_clk, "mbus-mcu", "mbus", 0x11c, BIT(1), = 0); +static SUNXI_CCU_GATE_HW(mbus_mcu_dma_clk, "mbus-mcu-dma", + &mbus_mcu_clk.common.hw, 0x11c, BIT(0), 0); + +static const struct clk_parent_data riscv_pwm_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, +}; + +static SUNXI_CCU_MUX_DATA_WITH_GATE(riscv_clk, "riscv", + riscv_pwm_parents, 0x120, + 27, 3, BIT(31), 0); +static SUNXI_CCU_GATE_DATA(bus_riscv_cfg_clk, "bus-riscv-cfg", osc24M, + 0x124, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_riscv_msgbox_clk, "bus-riscv-msgbox", osc24= M, + 0x128, BIT(0), 0); + +static SUNXI_CCU_MUX_DATA_WITH_GATE(mcu_pwm0_clk, "mcu-pwm0", + riscv_pwm_parents, 0x130, + 27, 3, BIT(31), 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_pwm0_clk, "bus-mcu-pwm0", osc24M, + 0x128, BIT(0), 0); + +/* + * Contains all clocks that are controlled by a hardware register. They + * have a (sunxi) .common member, which needs to be initialised by the com= mon + * sunxi CCU code, to be filled with the MMIO base address and the shared = lock. + */ +static struct ccu_common *sun55i_a523_mcu_ccu_clks[] =3D { + &pll_audio1_clk.common, + &audio_out_clk.common, + &dsp_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &i2s2_clk.common, + &i2s3_clk.common, + &i2s3_asrc_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_i2s2_clk.common, + &bus_i2s3_clk.common, + &spdif_tx_clk.common, + &spdif_rx_clk.common, + &bus_spdif_clk.common, + &dmic_clk.common, + &bus_dmic_clk.common, + &audio_dac_clk.common, + &audio_adc_clk.common, + &bus_audio_codec_clk.common, + &bus_dsp_msgbox_clk.common, + &bus_dsp_cfg_clk.common, + &bus_npu_aclk.common, + &bus_npu_hclk.common, + &mcu_timer0_clk.common, + &mcu_timer1_clk.common, + &mcu_timer2_clk.common, + &mcu_timer3_clk.common, + &mcu_timer4_clk.common, + &mcu_timer5_clk.common, + &bus_mcu_timer_clk.common, + &bus_mcu_dma_clk.common, + &tzma0_clk.common, + &tzma1_clk.common, + &bus_pubsram_clk.common, + &mbus_mcu_dma_clk.common, + &mbus_mcu_clk.common, + &riscv_clk.common, + &bus_riscv_cfg_clk.common, + &bus_riscv_msgbox_clk.common, + &mcu_pwm0_clk.common, + &bus_mcu_pwm0_clk.common, +}; + +static struct clk_hw_onecell_data sun55i_a523_mcu_hw_clks =3D { + .num =3D CLK_BUS_MCU_PWM0 + 1, + .hws =3D { + [CLK_MCU_PLL_AUDIO1] =3D &pll_audio1_clk.common.hw, + [CLK_MCU_PLL_AUDIO1_DIV2] =3D &pll_periph1_div2_clk.hw, + [CLK_MCU_PLL_AUDIO1_DIV5] =3D &pll_periph1_div5_clk.hw, + [CLK_MCU_AUDIO_OUT] =3D &audio_out_clk.common.hw, + [CLK_MCU_DSP] =3D &dsp_clk.common.hw, + [CLK_MCU_I2S0] =3D &i2s0_clk.common.hw, + [CLK_MCU_I2S1] =3D &i2s1_clk.common.hw, + [CLK_MCU_I2S2] =3D &i2s2_clk.common.hw, + [CLK_MCU_I2S3] =3D &i2s3_clk.common.hw, + [CLK_MCU_I2S3_ASRC] =3D &i2s3_asrc_clk.common.hw, + [CLK_BUS_MCU_I2S0] =3D &bus_i2s0_clk.common.hw, + [CLK_BUS_MCU_I2S1] =3D &bus_i2s1_clk.common.hw, + [CLK_BUS_MCU_I2S2] =3D &bus_i2s2_clk.common.hw, + [CLK_BUS_MCU_I2S3] =3D &bus_i2s3_clk.common.hw, + [CLK_MCU_SPDIF_TX] =3D &spdif_tx_clk.common.hw, + [CLK_MCU_SPDIF_RX] =3D &spdif_rx_clk.common.hw, + [CLK_BUS_MCU_SPDIF] =3D &bus_spdif_clk.common.hw, + [CLK_MCU_DMIC] =3D &dmic_clk.common.hw, + [CLK_BUS_MCU_DMIC] =3D &bus_dmic_clk.common.hw, + [CLK_MCU_AUDIO_CODEC_DAC] =3D &audio_dac_clk.common.hw, + [CLK_MCU_AUDIO_CODEC_ADC] =3D &audio_adc_clk.common.hw, + [CLK_BUS_MCU_AUDIO_CODEC] =3D &bus_audio_codec_clk.common.hw, + [CLK_BUS_MCU_DSP_MSGBOX] =3D &bus_dsp_msgbox_clk.common.hw, + [CLK_BUS_MCU_DSP_CFG] =3D &bus_dsp_cfg_clk.common.hw, + [CLK_BUS_MCU_NPU_HCLK] =3D &bus_npu_hclk.common.hw, + [CLK_BUS_MCU_NPU_ACLK] =3D &bus_npu_aclk.common.hw, + [CLK_MCU_TIMER0] =3D &mcu_timer0_clk.common.hw, + [CLK_MCU_TIMER1] =3D &mcu_timer1_clk.common.hw, + [CLK_MCU_TIMER2] =3D &mcu_timer2_clk.common.hw, + [CLK_MCU_TIMER3] =3D &mcu_timer3_clk.common.hw, + [CLK_MCU_TIMER4] =3D &mcu_timer4_clk.common.hw, + [CLK_MCU_TIMER5] =3D &mcu_timer5_clk.common.hw, + [CLK_BUS_MCU_TIMER] =3D &bus_mcu_timer_clk.common.hw, + [CLK_BUS_MCU_DMA] =3D &bus_mcu_dma_clk.common.hw, + [CLK_MCU_TZMA0] =3D &tzma0_clk.common.hw, + [CLK_MCU_TZMA1] =3D &tzma1_clk.common.hw, + [CLK_BUS_MCU_PUBSRAM] =3D &bus_pubsram_clk.common.hw, + [CLK_MCU_MBUS_DMA] =3D &mbus_mcu_dma_clk.common.hw, + [CLK_MCU_MBUS] =3D &mbus_mcu_clk.common.hw, + [CLK_MCU_RISCV] =3D &riscv_clk.common.hw, + [CLK_BUS_MCU_RISCV_CFG] =3D &bus_riscv_cfg_clk.common.hw, + [CLK_BUS_MCU_RISCV_MSGBOX] =3D &bus_riscv_msgbox_clk.common.hw, + [CLK_MCU_PWM0] =3D &mcu_pwm0_clk.common.hw, + [CLK_BUS_MCU_PWM0] =3D &bus_mcu_pwm0_clk.common.hw, + }, +}; + +static struct ccu_reset_map sun55i_a523_mcu_ccu_resets[] =3D { + [RST_BUS_MCU_I2S0] =3D { 0x0040, BIT(16) }, + [RST_BUS_MCU_I2S1] =3D { 0x0040, BIT(17) }, + [RST_BUS_MCU_I2S2] =3D { 0x0040, BIT(18) }, + [RST_BUS_MCU_I2S3] =3D { 0x0040, BIT(19) }, + [RST_BUS_MCU_SPDIF] =3D { 0x004c, BIT(16) }, + [RST_BUS_MCU_DMIC] =3D { 0x0054, BIT(16) }, + [RST_BUS_MCU_AUDIO_CODEC] =3D { 0x0060, BIT(16) }, + [RST_BUS_MCU_DSP_MSGBOX] =3D { 0x0068, BIT(16) }, + [RST_BUS_MCU_DSP_CFG] =3D { 0x006c, BIT(16) }, + [RST_BUS_MCU_NPU] =3D { 0x0070, BIT(16) }, + [RST_BUS_MCU_TIMER] =3D { 0x008c, BIT(16) }, + [RST_BUS_MCU_DSP_DEBUG] =3D { 0x0100, BIT(16) }, + [RST_BUS_MCU_DSP] =3D { 0x0100, BIT(17) }, + [RST_BUS_MCU_DMA] =3D { 0x0104, BIT(16) }, + [RST_BUS_MCU_PUBSRAM] =3D { 0x0114, BIT(16) }, + [RST_BUS_MCU_RISCV_CFG] =3D { 0x0124, BIT(16) }, + [RST_BUS_MCU_RISCV_DEBUG] =3D { 0x0124, BIT(17) }, + [RST_BUS_MCU_RISCV_CORE] =3D { 0x0124, BIT(18) }, + [RST_BUS_MCU_RISCV_MSGBOX] =3D { 0x0128, BIT(16) }, + [RST_BUS_MCU_PWM0] =3D { 0x0134, BIT(16) }, +}; + +static const struct sunxi_ccu_desc sun55i_a523_mcu_ccu_desc =3D { + .ccu_clks =3D sun55i_a523_mcu_ccu_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun55i_a523_mcu_ccu_clks), + + .hw_clks =3D &sun55i_a523_mcu_hw_clks, + + .resets =3D sun55i_a523_mcu_ccu_resets, + .num_resets =3D ARRAY_SIZE(sun55i_a523_mcu_ccu_resets), +}; + +static int sun55i_a523_mcu_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + u32 val; + int ret; + + reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + val =3D readl(reg + SUN55I_A523_PLL_AUDIO1_REG); + + /* + * The PLL clock code does not model all bits, for instance it does + * not support a separate enable and gate bit. We present the + * gate bit(27) as the enable bit, but then have to set the + * PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. + */ + val |=3D BIT(31) | BIT(30) | BIT(29); + + /* Enforce p1 =3D 5, p0 =3D 2 (the default) for PLL_AUDIO1 */ + val &=3D ~(GENMASK(22, 20) | GENMASK(18, 16)); + val |=3D (4 << 20) | (1 << 16); + + writel(val, reg + SUN55I_A523_PLL_AUDIO1_REG); + + ret =3D devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_mcu_ccu_desc); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id sun55i_a523_mcu_ccu_ids[] =3D { + { .compatible =3D "allwinner,sun55i-a523-mcu-ccu" }, + { } +}; + +static struct platform_driver sun55i_a523_mcu_ccu_driver =3D { + .probe =3D sun55i_a523_mcu_ccu_probe, + .driver =3D { + .name =3D "sun55i-a523-mcu-ccu", + .suppress_bind_attrs =3D true, + .of_match_table =3D sun55i_a523_mcu_ccu_ids, + }, +}; +module_platform_driver(sun55i_a523_mcu_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A523 MCU CCU"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ACBE2D543E; Sat, 30 Aug 2025 17:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; cv=none; b=lWedJ0ABog/sYzSTPGfMZ6RKsEhEChEw15Z3+66ZyCpLM1+GyvLudpkwlp5lEiuuQPSJ4twEr/aFUkC0A0A7nn+7viVBCAAl70vqcAjC8J06gIUpWDm8SemDZixowUQUijtv2grd8GkpBEwzNJr6BcyCWTDMKch8cTaKRJnpo3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; c=relaxed/simple; bh=3EElTfctldD5Dqcdckanf0DB/BbI9/XMswzxMb6oj8Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=htSnXoBKczk04QAty8keJ1FzCnPEJI6qhlakCV4+Ki/mblbDrSRKvCQWNTQQzHdQBTdRM/RSQikczFmQ8r36G8S4LPCm0cvFZncgbPN6EeWRVY1JUtLdkCrW8pMmD2NJ5mQEc/+SGOK4x38hnN1ToYU2A7DXAdMIrbh9OnvsMhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J5HIgdZo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J5HIgdZo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0542C4CEFB; Sat, 30 Aug 2025 17:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756573761; bh=3EElTfctldD5Dqcdckanf0DB/BbI9/XMswzxMb6oj8Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J5HIgdZo7fUrIavRXEx4kKLTdmW8vPp6jyDArGG2ys1mr6zR78jA9pttUs+fqdaSD T8EgKByOc1RUn7/IfHXBh7IR9rkIBeYVgNNQbJowLQFksA5CJ1VM1X4bO1bGvFvLeY 8HEMDLX3TxdrTK/jnBhf5UgSTdrVP1yyFIZvHFY4ak99ScG9sHbTs81PjFfRbGTRQg BsjjVMwBC8Cw2vQBGC1Bna0kXP/qQv3GlW00U/PIb5g6JoVcr6IgwFu5/xz/zfonGx WV/iFawQZNHaBEHI6k6PvKmS+fzgBihWb+i5uXOOqjEDtbXXKHNDFPl3xKBexwJpwF eixc+hikrSxyw== Received: by wens.tw (Postfix, from userid 1000) id 72A7E5FEDF; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] arm64: dts: allwinner: a523: Add MCU PRCM CCU node Date: Sun, 31 Aug 2025 01:09:00 +0800 Message-Id: <20250830170901.1996227-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai Add a device node for the third supported clock controller found in the A523 / T527 SoCs. This controller has clocks and resets for the RISC-V MCU, and others peripherals possibly meant to operate in low power mode driven by the MCU, such as audio interfaces, an audio DSP, and the NPU. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 79bd9ce08c7c..b6e82d53af54 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -4,8 +4,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -825,6 +827,29 @@ rtc: rtc@7090000 { clock-names =3D "bus", "hosc", "ahb"; #clock-cells =3D <1>; }; + + mcu_ccu: clock-controller@7102000 { + compatible =3D "allwinner,sun55i-a523-mcu-ccu"; + reg =3D <0x7102000 0x164>; + clocks =3D <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_PERIPH0_300M>, + <&ccu CLK_DSP>, + <&r_ccu CLK_R_AHB>, + <&ccu CLK_MBUS>; + clock-names =3D "hosc", + "losc", + "iosc", + "pll-audio0-4x", + "pll-periph0-300m", + "dsp", + "r-ahb", + "mbus"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; =20 thermal-zones { --=20 2.39.5 From nobody Fri Oct 3 13:30:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FF002D6406; Sat, 30 Aug 2025 17:09:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; cv=none; b=er8lLiGO3ET4gDXWXetN3Sgl0bSF3fqhlVFR1o0MIBf+OOJkDe/BVH6behHsuI25hEYvOqPrqrLNCwb+bQo0av23Oir7KkFbmIAcHsTZvrSnu9JliMWaVd5rjBcEoLS5q5BoBYosR1ZSVzwzuX6C/qhHIJcQ29xZ1y34fgRbuzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756573762; c=relaxed/simple; bh=X9UravRZTkYO/S1t31DyRCOSep0v8TZbjoIrBK1EKNA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NzP0q4eJPn42+F8X/8O0wvkeh4/Odjs9JnY+Il498DokVmJ2id7GAfGDe4j9NTJj+Cx7b01OclVvDj0zzTi9nS0BO7iADToHCLp70DIhFr6rc+Xd9ANjvU6QUqPNk+uZ0xpvAO1LKSjAjHyMNLVizJAoECSo8XZbiWeKmuiNUWE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iwFLUfxl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iwFLUfxl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E84C8C4CEF8; Sat, 30 Aug 2025 17:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756573762; bh=X9UravRZTkYO/S1t31DyRCOSep0v8TZbjoIrBK1EKNA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iwFLUfxlJFRuEDCHufRML+UIZZxkrkNLuW9Jorcc8xsw9v1WoDX0KJAJ8NHXNMfk+ yh/ifCmuennI9zj0KjV/5voVETLt/qc+ZxPVJ5xAZ2vSPBfijwsMjXdF8p9agJMWpD k2nwhPQEotMppPXpGxzPrFxKQmaEoTvdbZq6DFEFbQIwvI7PIpEshjdgXOsI7CHavy YUhA2F4y1pxYWGxRhGNu8u5b5aSp/NhW8ib3aRF/FZDXZHJrel6uweKlQtTXbsJJmf avfDBFenDBvxkH7gnmYNXvNWFt5CmAb3+SLuz8cv2PTAe/B/3noF205eW3jxwRoJuz KlphCMUjLomaA== Received: by wens.tw (Postfix, from userid 1000) id 78ADF5FF44; Sun, 31 Aug 2025 01:09:17 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] arm64: dts: allwinner: a523: Add NPU device node Date: Sun, 31 Aug 2025 01:09:01 +0800 Message-Id: <20250830170901.1996227-9-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250830170901.1996227-1-wens@kernel.org> References: <20250830170901.1996227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner T527 SoC has an NPU built in. Based on identifiers found in the BSP, it is a Vivante IP block. After enabling it, the etnaviv driver reports it as a GC9000 revision 9003. The standard bindings are used as everything matches directly. There is no option for DVFS at the moment. That might require some more work, perhaps on the efuse side to map speed bins. It is unclear whether the NPU block is fused out at the hardware level or the BSP limits use of the NPU through software, as the author only has boards with the T527. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index b6e82d53af54..1ab5b87ec78e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -850,6 +850,18 @@ mcu_ccu: clock-controller@7102000 { #clock-cells =3D <1>; #reset-cells =3D <1>; }; + + npu: npu@7122000 { + compatible =3D "vivante,gc"; + reg =3D <0x07122000 0x1000>; + interrupts =3D ; + clocks =3D <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, + <&ccu CLK_NPU>, + <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; + clock-names =3D "bus", "core", "reg"; + resets =3D <&mcu_ccu RST_BUS_MCU_NPU>; + power-domains =3D <&ppu PD_NPU>; + }; }; =20 thermal-zones { --=20 2.39.5