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Sat, 30 Aug 2025 07:03:57 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 57U73uQS001755; Sat, 30 Aug 2025 07:03:57 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id 4D3D56009E0; Sat, 30 Aug 2025 12:33:56 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, mani@kernel.org, neil.armstrong@linaro.org, dmitry.baryshkov@oss.qualcomm.com, andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Nitin Rawat Subject: [PATCH V4 1/2] phy: qcom-qmp-ufs: Add regulator load voting for UFS QMP PHY Date: Sat, 30 Aug 2025 12:33:52 +0530 Message-ID: <20250830070353.2694-2-nitin.rawat@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250830070353.2694-1-nitin.rawat@oss.qualcomm.com> References: <20250830070353.2694-1-nitin.rawat@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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To ensure proper operation, the regulator framework must be informed of the UFS PHY's load requirements. This is essential because the regulator's operating mode=E2=80=94whether Low Power or High Power=E2=80=94depends on the maximum expected load at any giv= en time, which the regulator driver needs to manage accordingly. To support this, replace devm_regulator_bulk_get() with devm_regulator_bulk_get_const() and inline the qmp_ufs_vreg_init() function. additionally replace the array of regulator names with a bulk regulator data structure, and utilize the init_load_uA field provided by the regulator framework. This ensures that regulator_set_load() is automatically invoked before the first enable operation. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 29 +++++++------------------ 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 9c69c77d10c8..aaa88ca0ef07 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1107,7 +1107,7 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY]; /* regulators to be requested */ - const char * const *vreg_list; + const struct regulator_bulk_data *vreg_list; int num_vregs; /* array of registers with different offsets */ @@ -1164,9 +1164,10 @@ static inline void qphy_clrbits(void __iomem *base, = u32 offset, u32 val) readl(base + offset); } -/* list of regulators */ -static const char * const qmp_phy_vreg_l[] =3D { - "vdda-phy", "vdda-pll", +/* Default regulator bulk data (no load used) */ +static const struct regulator_bulk_data qmp_phy_vreg_l[] =3D { + { .supply =3D "vdda-phy" }, + { .supply =3D "vdda-pll" }, }; static const struct qmp_ufs_offsets qmp_ufs_offsets =3D { @@ -1890,22 +1891,6 @@ static const struct phy_ops qcom_qmp_ufs_phy_ops =3D= { .owner =3D THIS_MODULE, }; -static int qmp_ufs_vreg_init(struct qmp_ufs *qmp) -{ - const struct qmp_phy_cfg *cfg =3D qmp->cfg; - struct device *dev =3D qmp->dev; - int num =3D cfg->num_vregs; - int i; - - qmp->vregs =3D devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); - if (!qmp->vregs) - return -ENOMEM; - - for (i =3D 0; i < num; i++) - qmp->vregs[i].supply =3D cfg->vreg_list[i]; - - return devm_regulator_bulk_get(dev, num, qmp->vregs); -} static int qmp_ufs_clk_init(struct qmp_ufs *qmp) { @@ -2068,7 +2053,9 @@ static int qmp_ufs_probe(struct platform_device *pdev) if (ret) return ret; - ret =3D qmp_ufs_vreg_init(qmp); + ret =3D devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, + qmp->cfg->vreg_list, + &qmp->vregs); if (ret) return ret; -- 2.50.1 From nobody Fri Oct 3 13:32:14 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74B801E990E; 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charset="utf-8" From: Nitin Rawat Add phy and pll regulator load voting support for all supported platforms by introducing dedicated regulator bulk data arrays with their load values. This ensures stable operation and proper power management for these platforms where regulators are shared between the QMP UFS PHY and other IP blocks by setting appropriate regulator load currents during PHY operations. Signed-off-by: Nitin Rawat Acked-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 138 ++++++++++++++++++------ 1 file changed, 104 insertions(+), 34 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index aaa88ca0ef07..8a280433a42b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1164,10 +1164,80 @@ static inline void qphy_clrbits(void __iomem *base,= u32 offset, u32 val) readl(base + offset); } -/* Default regulator bulk data (no load used) */ -static const struct regulator_bulk_data qmp_phy_vreg_l[] =3D { - { .supply =3D "vdda-phy" }, - { .supply =3D "vdda-pll" }, +/* Regulator bulk data with load values for specific configurations */ +static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 51400 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 14600 }, +}; + +static const struct regulator_bulk_data sa8775p_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 137000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18300 }, +}; + +static const struct regulator_bulk_data sc7280_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 97500 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18400 }, +}; + +static const struct regulator_bulk_data sc8280xp_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 85700 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18300 }, +}; + +static const struct regulator_bulk_data sdm845_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 51400 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 14600 }, +}; + +static const struct regulator_bulk_data sm6115_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 51400 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 14200 }, +}; + +static const struct regulator_bulk_data sm7150_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 62900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18300 }, +}; + +static const struct regulator_bulk_data sm8150_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 90200 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 19000 }, +}; + +static const struct regulator_bulk_data sm8250_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 89900 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18800 }, +}; + +static const struct regulator_bulk_data sm8350_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 91600 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 19000 }, +}; + +static const struct regulator_bulk_data sm8450_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 173000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 24900 }, +}; + +static const struct regulator_bulk_data sm8475_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 213030 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18340 }, +}; + +static const struct regulator_bulk_data sm8550_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 188000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18300 }, +}; + +static const struct regulator_bulk_data sm8650_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 205000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 17500 }, +}; + +static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 213000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 18300 }, }; static const struct qmp_ufs_offsets qmp_ufs_offsets =3D { @@ -1203,8 +1273,8 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = =3D { .rx_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D msm8996_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(msm8996_ufsphy_vreg_l), .regs =3D ufsphy_v2_regs_layout, @@ -1240,8 +1310,8 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = =3D { .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sa8775p_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sa8775p_ufsphy_vreg_l), .regs =3D ufsphy_v5_regs_layout, }; @@ -1274,8 +1344,8 @@ static const struct qmp_phy_cfg sc7280_ufsphy_cfg =3D= { .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sc7280_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sc7280_ufsphy_vreg_l), .regs =3D ufsphy_v4_regs_layout, }; @@ -1308,8 +1378,8 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sc8280xp_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sc8280xp_ufsphy_vreg_l), .regs =3D ufsphy_v5_regs_layout, }; @@ -1333,8 +1403,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { .serdes =3D sdm845_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sdm845_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sdm845_ufsphy_vreg_l), .regs =3D ufsphy_v3_regs_layout, .no_pcs_sw_reset =3D true, @@ -1360,8 +1430,8 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { .serdes =3D sm6115_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm6115_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm6115_ufsphy_vreg_l), .regs =3D ufsphy_v2_regs_layout, .no_pcs_sw_reset =3D true, @@ -1387,8 +1457,8 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg =3D= { .serdes =3D sdm845_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm7150_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm7150_ufsphy_vreg_l), .regs =3D ufsphy_v3_regs_layout, .no_pcs_sw_reset =3D true, @@ -1423,8 +1493,8 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8150_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8150_ufsphy_vreg_l), .regs =3D ufsphy_v4_regs_layout, }; @@ -1457,8 +1527,8 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D= { .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8250_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8250_ufsphy_vreg_l), .regs =3D ufsphy_v4_regs_layout, }; @@ -1491,8 +1561,8 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8350_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8350_ufsphy_vreg_l), .regs =3D ufsphy_v5_regs_layout, }; @@ -1525,8 +1595,8 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D= { .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8450_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8450_ufsphy_vreg_l), .regs =3D ufsphy_v5_regs_layout, }; @@ -1561,8 +1631,8 @@ static const struct qmp_phy_cfg sm8475_ufsphy_cfg =3D= { .pcs_num =3D ARRAY_SIZE(sm8475_ufsphy_g4_pcs), .max_gear =3D UFS_HS_G4, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8475_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8475_ufsphy_vreg_l), .regs =3D ufsphy_v6_regs_layout, }; @@ -1606,8 +1676,8 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg =3D= { .pcs_num =3D ARRAY_SIZE(sm8550_ufsphy_g5_pcs), .max_gear =3D UFS_HS_G5, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8550_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8550_ufsphy_vreg_l), .regs =3D ufsphy_v6_regs_layout, }; @@ -1638,8 +1708,8 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg =3D= { .max_gear =3D UFS_HS_G5, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8650_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8650_ufsphy_vreg_l), .regs =3D ufsphy_v6_regs_layout, }; @@ -1676,8 +1746,8 @@ static const struct qmp_phy_cfg sm8750_ufsphy_cfg =3D= { .max_gear =3D UFS_HS_G5, }, - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D sm8750_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(sm8750_ufsphy_vreg_l), .regs =3D ufsphy_v6_regs_layout, }; -- 2.50.1