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Sat, 30 Aug 2025 09:28:41 -0700 (PDT) Received: from [127.0.0.1] ([74.249.85.195]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70fb28b5a26sm8110786d6.64.2025.08.30.09.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Aug 2025 09:28:41 -0700 (PDT) From: Denzeel Oliva Date: Sat, 30 Aug 2025 16:28:38 +0000 Subject: [PATCH v5 1/5] clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250830-fix-cmu-top-v5-1-7c62f608309e@gmail.com> References: <20250830-fix-cmu-top-v5-0-7c62f608309e@gmail.com> In-Reply-To: <20250830-fix-cmu-top-v5-0-7c62f608309e@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756571319; l=2137; i=wachiturroxd150@gmail.com; s=20250830; h=from:subject:message-id; bh=6yax87RqbvYF0ActasAJerhVa1SUTvfy73gnHEk7z9c=; b=BCbvIMxI7eRG7Yukaw4ERMJfQIzWK6VhM8NKMcnXh5upDYGzAtOTPVieAzFHIx6K4czcLEYoe JleTq1TdQLJDxq4lWQ+TFncQfCy35ey6m1XL8S3pVNDC2U2WTA4BgnJ X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=rxHEBGA1eos5vQkPC9SlkEPD6sil9F03N6bc8qmUFrQ= Parent select bits for shared PLLs are in PLL_CON0, not PLL_CON3. Using the wrong register leads to incorrect parent selection and rates. Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller dr= iver") Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 8d3f193d2b4d4c2146d9b8b57d76605b88dc9bbb..12e98bf5005ae2dc32da0da684a= 15133d64ed305 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -239,12 +239,19 @@ static const unsigned long top_clk_regs[] __initconst= =3D { PLL_LOCKTIME_PLL_SHARED2, PLL_LOCKTIME_PLL_SHARED3, PLL_LOCKTIME_PLL_SHARED4, + PLL_CON0_PLL_G3D, PLL_CON3_PLL_G3D, + PLL_CON0_PLL_MMC, PLL_CON3_PLL_MMC, + PLL_CON0_PLL_SHARED0, PLL_CON3_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, PLL_CON3_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, PLL_CON3_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, PLL_CON3_PLL_SHARED3, + PLL_CON0_PLL_SHARED4, PLL_CON3_PLL_SHARED4, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, @@ -689,13 +696,13 @@ PNAME(mout_cmu_vra_bus_p) =3D { "dout_cmu_shared0_di= v3", =20 static const struct samsung_mux_clock top_mux_clks[] __initconst =3D { MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, - PLL_CON3_PLL_SHARED0, 4, 1), + PLL_CON0_PLL_SHARED0, 4, 1), MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, - PLL_CON3_PLL_SHARED1, 4, 1), + PLL_CON0_PLL_SHARED1, 4, 1), MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, - PLL_CON3_PLL_SHARED2, 4, 1), + PLL_CON0_PLL_SHARED2, 4, 1), MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, - PLL_CON3_PLL_SHARED3, 4, 1), + PLL_CON0_PLL_SHARED3, 4, 1), MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p, PLL_CON0_PLL_SHARED4, 4, 1), MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p, --=20 2.50.1 From nobody Fri Oct 3 13:21:33 2025 Received: from mail-qv1-f52.google.com (mail-qv1-f52.google.com [209.85.219.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B6592D0C8A; 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Sat, 30 Aug 2025 09:28:42 -0700 (PDT) Received: from [127.0.0.1] ([74.249.85.195]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70fb28b5a26sm8110786d6.64.2025.08.30.09.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Aug 2025 09:28:41 -0700 (PDT) From: Denzeel Oliva Date: Sat, 30 Aug 2025 16:28:39 +0000 Subject: [PATCH v5 2/5] clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250830-fix-cmu-top-v5-2-7c62f608309e@gmail.com> References: <20250830-fix-cmu-top-v5-0-7c62f608309e@gmail.com> In-Reply-To: <20250830-fix-cmu-top-v5-0-7c62f608309e@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756571319; l=4124; i=wachiturroxd150@gmail.com; s=20250830; h=from:subject:message-id; bh=eG/sqPWtkgzTsSio4RUmLrcfnT+7wa1K05i+7zQ30C0=; b=FqjDR3kxtVKWkMfPKMbdpzUivCRJC3agpWnZo2mbw7MmxwpKp79EfVLlkbkY6Ra3EANpcmECo VBq21rBMxfvBgeU+JMbz66hcgPA7l2PO7aR/GL7yTt0oef4SE7Q2n7n X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=rxHEBGA1eos5vQkPC9SlkEPD6sil9F03N6bc8qmUFrQ= Correct several mux/div widths (DSP_BUS, G2D_MSCL, HSI0 USBDP_DEBUG, HSI1 UFS_EMBD, APM_BUS, CPUCL0_DBG_BUS, DPU) to match hardware. Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller dr= iver") Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 12e98bf5005ae2dc32da0da684a15133d64ed305..385f1d9726675b37a901e1bb617= 2dc839afbb209 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -766,11 +766,11 @@ static const struct samsung_mux_clock top_mux_clks[] = __initconst =3D { MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt", mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2), MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus", - mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2), + mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 3), MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2), MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", - mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1), + mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2), MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", @@ -782,7 +782,7 @@ static const struct samsung_mux_clock top_mux_clks[] __= initconst =3D { 0, 2), MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug", mout_cmu_hsi0_usbdp_debug_p, - CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2), + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 1), MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card", @@ -795,7 +795,7 @@ static const struct samsung_mux_clock top_mux_clks[] __= initconst =3D { 0, 2), MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd", mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD, - 0, 1), + 0, 2), MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1), MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", @@ -869,7 +869,7 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), =20 DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus", - CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), + CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2), DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3), DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", @@ -894,9 +894,9 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2), DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), - DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug", + DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus", "gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, - 0, 3), + 0, 4), DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", @@ -986,8 +986,8 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus", CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), - DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu", - CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4), + DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", + CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), }; 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Sat, 30 Aug 2025 09:28:42 -0700 (PDT) Received: from [127.0.0.1] ([74.249.85.195]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70fb28b5a26sm8110786d6.64.2025.08.30.09.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Aug 2025 09:28:42 -0700 (PDT) From: Denzeel Oliva Date: Sat, 30 Aug 2025 16:28:40 +0000 Subject: [PATCH v5 3/5] clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250830-fix-cmu-top-v5-3-7c62f608309e@gmail.com> References: <20250830-fix-cmu-top-v5-0-7c62f608309e@gmail.com> In-Reply-To: <20250830-fix-cmu-top-v5-0-7c62f608309e@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756571319; l=3403; i=wachiturroxd150@gmail.com; s=20250830; h=from:subject:message-id; bh=l3sVrdnJv1dCoe2zTIV4QQOQgosblDanMaN6/DUrxNk=; b=bWMZV72hCHH8WTWopB+8nMN/ZoLxLeornlqLEOU4HlDU74gAsMkfzBr1KtoTAEUavVR3m27N0 O068adzet0EBjyq3Y9B/1dU1Q72rC7iHtzDEUHXbNaxrP+Cpov3S/C2 X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=rxHEBGA1eos5vQkPC9SlkEPD6sil9F03N6bc8qmUFrQ= HSI1/2 PCIe and HSI0 USBDP debug outputs are fixed divide-by-8. OTP also uses 1/8 from oscclk. Replace incorrect div clocks with fixed-factor clocks to reflect hardware. Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller dr= iver") Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 385f1d9726675b37a901e1bb6172dc839afbb209..8571c225d09074cfd1c299879c1= e6b4a7322520a 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -931,16 +931,11 @@ static const struct samsung_div_clock top_div_clks[] = __initconst =3D { CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3), DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4), - DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug", - "gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG, - 0, 4), DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3), DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card", "gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9), - DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", - CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7), DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card", "gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD, 0, 3), @@ -949,8 +944,6 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { 0, 3), DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), - DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", - CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7), DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", @@ -990,6 +983,16 @@ static const struct samsung_div_clock top_div_clks[] _= _initconst =3D { CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), }; =20 +static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initcon= st =3D { + FFACTOR(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", + "gout_cmu_hsi1_pcie", 1, 8, 0), + FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), + FFACTOR(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug", + "gout_cmu_hsi0_usbdp_debug", 1, 8, 0), + FFACTOR(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", + "gout_cmu_hsi2_pcie", 1, 8, 0), +}; + static const struct samsung_gate_clock top_gate_clks[] __initconst =3D { GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0), @@ -1133,6 +1136,8 @@ static const struct samsung_cmu_info top_cmu_info __i= nitconst =3D { .nr_mux_clks =3D ARRAY_SIZE(top_mux_clks), .div_clks =3D top_div_clks, .nr_div_clks =3D ARRAY_SIZE(top_div_clks), + .fixed_factor_clks =3D cmu_top_ffactor, + .nr_fixed_factor_clks =3D ARRAY_SIZE(cmu_top_ffactor), .gate_clks =3D top_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(top_gate_clks), .nr_clk_ids =3D CLKS_NR_TOP, --=20 2.50.1 From nobody Fri Oct 3 13:21:33 2025 Received: from mail-qv1-f44.google.com (mail-qv1-f44.google.com [209.85.219.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8C502D29CA; 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a=ed25519-sha256; t=1756571319; l=919; i=wachiturroxd150@gmail.com; s=20250830; h=from:subject:message-id; bh=04MZLdRvtv3dYSrEKVA7n7X4qOcNIGMw9F8ZkaILBxE=; b=aSAEvIpGXqzUd2y38j1q7ddgyOtKqqD82eO8ZsEzv+81Mv3QsoMnm6TOP3BDfFmeM36Z7qusH GbtyJYNZBajDXdB9Zwt/SHySAhyqqtQmhGIYSvpYyuiZRrMQCIj37Xe X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=rxHEBGA1eos5vQkPC9SlkEPD6sil9F03N6bc8qmUFrQ= Add missing clock definitions for DPU and CMUREF. Acked-by: Rob Herring (Arm) Signed-off-by: Denzeel Oliva --- include/dt-bindings/clock/samsung,exynos990.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bin= dings/clock/samsung,exynos990.h index 6b9df09d2822f1c8e5086a2fc0bda783ca224812..c5c79e078f2f60fdb2c0f61ba6e= 7f3c6f2fbe9f2 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -208,6 +208,10 @@ #define CLK_GOUT_CMU_SSP_BUS 197 #define CLK_GOUT_CMU_TNR_BUS 198 #define CLK_GOUT_CMU_VRA_BUS 199 +#define CLK_MOUT_CMU_CMUREF 200 +#define CLK_MOUT_CMU_DPU_BUS 201 +#define CLK_MOUT_CMU_CLK_CMUREF 202 +#define CLK_DOUT_CMU_CLK_CMUREF 203 =20 /* CMU_HSI0 */ #define CLK_MOUT_HSI0_BUS_USER 1 --=20 2.50.1 From nobody Fri Oct 3 13:21:33 2025 Received: from mail-qv1-f53.google.com (mail-qv1-f53.google.com [209.85.219.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1CF52D3758; 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a=ed25519-sha256; t=1756571320; l=5654; i=wachiturroxd150@gmail.com; s=20250830; h=from:subject:message-id; bh=5IPuwTPYxNGQIBDJPCqLNlhrVjtDtNs6m7JTklARsrQ=; b=CvwDr0wXhmzZT+RELAeJJ1yiEwqe5yMi7s5f4NyHS4xmHtZvt/7vrTANzyvxMaEuG7HHsuMwn 2NmBW5cswaGDDBohXFGDWB0dI0sOYtTb9DOG5TIzsGVpHBgr+EnMkjN X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=rxHEBGA1eos5vQkPC9SlkEPD6sil9F03N6bc8qmUFrQ= Add DPU_BUS and CMUREF mux/div, wire their registers and parents, and update CLKS_NR_TOP. These use the new IDs appended to the bindings to avoid ABI changes. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 8571c225d09074cfd1c299879c1e6b4a7322520a..91736b15c4b4a0759419517f7b0= 4dd0a8f38a289 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -17,7 +17,7 @@ #include "clk-pll.h" =20 /* NOTE: Must be equal to the last clock ID increased by one */ -#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) +#define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1) #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) =20 @@ -45,6 +45,7 @@ #define PLL_CON3_PLL_SHARED3 0x024c #define PLL_CON0_PLL_SHARED4 0x0280 #define PLL_CON3_PLL_SHARED4 0x028c +#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c @@ -103,6 +104,8 @@ #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8 +#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808 @@ -162,6 +165,7 @@ #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc @@ -253,6 +257,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { PLL_CON3_PLL_SHARED3, PLL_CON0_PLL_SHARED4, PLL_CON3_PLL_SHARED4, + CLK_CON_MUX_CLKCMU_DPU_BUS, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, @@ -311,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, + CLK_CON_MUX_MUX_CLK_CMU_CMUREF, + CLK_CON_MUX_MUX_CMU_CMUREF, CLK_CON_DIV_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_BUS0_BUS, @@ -370,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_DIV_CLKCMU_VRA_BUS, CLK_CON_DIV_DIV_CLKCMU_DPU, CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, CLK_CON_DIV_PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV3, CLK_CON_DIV_PLL_SHARED0_DIV4, @@ -465,6 +473,8 @@ PNAME(mout_pll_shared3_p) =3D { "oscclk", "fout_shared= 3_pll" }; PNAME(mout_pll_shared4_p) =3D { "oscclk", "fout_shared4_pll" }; PNAME(mout_pll_mmc_p) =3D { "oscclk", "fout_mmc_pll" }; PNAME(mout_pll_g3d_p) =3D { "oscclk", "fout_g3d_pll" }; +PNAME(mout_cmu_dpu_bus_p) =3D { "dout_cmu_dpu", + "dout_cmu_dpu_alt" }; PNAME(mout_cmu_apm_bus_p) =3D { "dout_cmu_shared0_div2", "dout_cmu_shared2_div2" }; PNAME(mout_cmu_aud_cpu_p) =3D { "dout_cmu_shared0_div2", @@ -679,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) =3D { "dout_cmu_shared0_div= 3", "dout_cmu_shared4_div2", "dout_cmu_shared0_div4", "dout_cmu_shared4_div3" }; +PNAME(mout_cmu_cmuref_p) =3D { "oscclk", + "dout_cmu_clk_cmuref" }; +PNAME(mout_cmu_clk_cmuref_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "oscclk" }; =20 /* * Register name to clock name mangling strategy used in this file @@ -709,6 +725,8 @@ static const struct samsung_mux_clock top_mux_clks[] __= initconst =3D { PLL_CON0_PLL_MMC, 4, 1), MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p, PLL_CON0_PLL_G3D, 4, 1), + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", + mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1), MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", @@ -837,6 +855,10 @@ static const struct samsung_mux_clock top_mux_clks[] _= _initconst =3D { mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus", mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2), + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", + mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), + MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref", + mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2), }; =20 static const struct samsung_div_clock top_div_clks[] __initconst =3D { @@ -981,6 +1003,10 @@ static const struct samsung_div_clock top_div_clks[] = __initconst =3D { CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), + DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus", + CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4), + DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref", + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), }; =20 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initcon= st =3D { --=20 2.50.1