From nobody Fri Oct 3 14:44:00 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3973244665 for ; Fri, 29 Aug 2025 19:33:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756496039; cv=none; b=IaAjSUa7xhf0Q0i2uWL96hshLcYHAYmLsFNrx+BqKV6Q39Q9tu1QbOs734QmetOjD+3Wendk2oDMrUItjB/nB0hn6YIFS0cBFYL3/ukoTtFS4PiIG86F1v81aZ7cZ75VfRXmCk6/WX1m1uWGFLRPg3iLzKMIt6peosl7fewOftg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756496039; c=relaxed/simple; bh=SfB0TJk736u2g5k+kCz54QRQtQYbcEfPwysTGPOw1Vk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vg8yQK3v9en4gpVEtXV9UQoLSaIta9ul/bcc76gE7txvuPHEAgv1jKd47WU+2UzOLkB/61IU+1DK4ofYw20UegBoFCQzNEDviEJPUM7OnLDK9C7WGF8RbA3fNN8PDeezhV5KZPVPc/9Ty7/odhlrmSDxFStx9Nb+A5tt4cTAvEo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=V0KebGrZ; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="V0KebGrZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756496037; x=1788032037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SfB0TJk736u2g5k+kCz54QRQtQYbcEfPwysTGPOw1Vk=; b=V0KebGrZY5YGli99hw9liyjUxwDRRzA+UZX5Il0vYwbrdWpl3/Yqw6rB 4nk/YutZrljeTcdUsVLpuVCqKrR/Zi/tKBbPIyFuAoYORhVZ/Tq4gi0Km U+m7j5ZeIckze0kMpt/IIKZSBKdx7vkQhVLkna66biFPfpO8q0Kzv2JIm IR+8an4JiC4YDyD4e0hdtREJRFM9f1vOtKubvKX8CMKlmgVVccywgZXVo TO3ui1mjPdMFFunnpHsxIgYkqjw9GJPWHN7S7BvgLlhFDQJa+XNvvBZor nd6IHmD3DRwyf2w9E8dU7f5LwEGNgTU780VvXSngadXuygHX2+QMsrPtw w==; X-CSE-ConnectionGUID: QVaGysHHQxGIhGKNBrgROQ== X-CSE-MsgGUID: yxdda5L1RF+IDUmwuXXj5g== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="62625180" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="62625180" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 12:33:53 -0700 X-CSE-ConnectionGUID: yKJWZhfeTO64WvroOe32uA== X-CSE-MsgGUID: s0bFJI1MQT6fV5HlZzzi4Q== X-ExtLoop1: 1 Received: from ldmartin-desk2.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.220.202]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 12:33:53 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu Cc: x86@kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v9 06/31] x86/resctrl: Move L3 initialization into new helper function Date: Fri, 29 Aug 2025 12:33:18 -0700 Message-ID: <20250829193346.31565-7-tony.luck@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250829193346.31565-1-tony.luck@intel.com> References: <20250829193346.31565-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All resctrl monitor events are associated with the L3 resource, but this is about to change. To prepare for additional types of monitoring domains, move open coded L3 resource monitoring domain initialization from domain_add_cpu_mon() into a new helper l3_mon_domain_setup() called by domain_add_cpu_mon(). Signed-off-by: Tony Luck --- arch/x86/kernel/cpu/resctrl/core.c | 56 ++++++++++++++++++------------ 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 420e4eb7c160..4db46c282b5c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -496,34 +496,13 @@ static void domain_add_cpu_ctrl(int cpu, struct rdt_r= esource *r) } } =20 -static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) +static void l3_mon_domain_setup(int cpu, int id, struct rdt_resource *r, s= truct list_head *add_pos) { - int id =3D get_domain_id_from_scope(cpu, r->mon_scope); - struct list_head *add_pos =3D NULL; struct rdt_hw_mon_domain *hw_dom; - struct rdt_domain_hdr *hdr; struct rdt_mon_domain *d; struct cacheinfo *ci; int err; =20 - lockdep_assert_held(&domain_list_lock); - - if (id < 0) { - pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resou= rce %s\n", - cpu, r->mon_scope, r->name); - return; - } - - hdr =3D resctrl_find_domain(&r->mon_domains, id, &add_pos); - if (hdr) { - if (!domain_header_is_valid(hdr, RESCTRL_MON_DOMAIN, r->rid)) - return; - d =3D container_of(hdr, struct rdt_mon_domain, hdr); - - cpumask_set_cpu(cpu, &d->hdr.cpu_mask); - return; - } - hw_dom =3D kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); if (!hw_dom) return; @@ -558,6 +537,39 @@ static void domain_add_cpu_mon(int cpu, struct rdt_res= ource *r) } } =20 +static void domain_add_cpu_mon(int cpu, struct rdt_resource *r) +{ + int id =3D get_domain_id_from_scope(cpu, r->mon_scope); + struct list_head *add_pos =3D NULL; + struct rdt_domain_hdr *hdr; + + lockdep_assert_held(&domain_list_lock); + + if (id < 0) { + pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resou= rce %s\n", + cpu, r->mon_scope, r->name); + return; + } + + hdr =3D resctrl_find_domain(&r->mon_domains, id, &add_pos); + if (hdr) { + if (!domain_header_is_valid(hdr, RESCTRL_MON_DOMAIN, r->rid)) + return; + cpumask_set_cpu(cpu, &hdr->cpu_mask); + + return; + } + + switch (r->rid) { + case RDT_RESOURCE_L3: + l3_mon_domain_setup(cpu, id, r, add_pos); + break; + default: + pr_warn_once("Unknown resource rid=3D%d\n", r->rid); + break; + } +} + static void domain_add_cpu(int cpu, struct rdt_resource *r) { if (r->alloc_capable) --=20 2.50.1