From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05A44322A18; Fri, 29 Aug 2025 15:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481593; cv=none; b=eQl+0ChrGa1Yd1//5scDCpwWSPXGW7WZBjkAzAEH7ItBcY6yJzT6FDuDgFLZNBuKJFntup2A2HBgdSZGgrvzUwvidECmpAUk/9DDdpiwmKt5sJPTGMJCdihIAbYajDHw3gXz46C2quVcV/J12MDdHr9ToZA8FqMcmt9P56iftns= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481593; c=relaxed/simple; bh=+ZWqzAVOzmU9lLd+PcegSgkJMegZ4d4f6NYVM/aZOFA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EcPGQ1HGNrAh9aRrSoztM0Ih/HjX7m3iB8fMaaPkBMuL1nW9UAzWti/PS3mB1g4L7KzBahu98zbX846hLXiqvzvG0PXXvAdGiNz0W23xMo02f7f4gWh0vpHI5mK09y/QaH26vnWMSR9HH86jweLK8pU9l6a6ISit/CQVq1NfuA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=a1ioVOZV; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="a1ioVOZV" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo472871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:12 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo472871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481533; bh=NStuWvxvM+qj9llA7FZ8ztXhbbvOMfjUnsFWO96qtlc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a1ioVOZVZHLqi7AX8lpMzxyI0c2HeUpW8xXIdlF8vsTmKxs3L9UzRx7tc6Essi+V/ kjvAj+GZg0d3oi65fhBpx/5m6ZT0LnWPAV2wC19aMhC/QsKJEhArj0Pvdaq03e5H64 xY4uUv9iAEAL+XhJ0nd9XJgRKRJLpi3AS4kBhzHmYeMTPDZhryV8E94R4qCE+vPXWW +DWCtXdAaKt6QP7klVPH/P3nkCohwf48eZ+CJiC82Sd2hqPOIi7LGG/Uk9N1flNwnQ +JOjjCC1fELrd4l8dUvJqRiIz3iKBLaCvRyzZAbh8Wh1Ewv1K+WwC/HE5RPu+oxcNx SvRZI30pgJQEQ== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 01/21] KVM: VMX: Add support for the secondary VM exit controls Date: Fri, 29 Aug 2025 08:31:29 -0700 Message-ID: <20250829153149.2871901-2-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Always load the secondary VM exit controls to prepare for FRED enabling. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. Changes in v4: * Fix clearing VM_EXIT_ACTIVATE_SECONDARY_CONTROLS (Chao Gao). * Check VM exit/entry consistency based on the new macro from Sean Christopherson. Change in v3: * Do FRED controls consistency checks in the VM exit/entry consistency check framework (Sean Christopherson). Change in v2: * Always load the secondary VM exit controls (Sean Christopherson). --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 3 +++ arch/x86/kvm/vmx/capabilities.h | 9 ++++++++- arch/x86/kvm/vmx/vmcs.h | 1 + arch/x86/kvm/vmx/vmx.c | 29 +++++++++++++++++++++++++++-- arch/x86/kvm/vmx/vmx.h | 7 ++++++- 6 files changed, 46 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 20fa4a79df13..7c59cc5ee044 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1208,6 +1208,7 @@ #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 +#define MSR_IA32_VMX_EXIT_CTLS2 0x00000493 =20 /* Resctrl MSRs: */ /* - Intel: */ diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index c85c50019523..1f60c04d11fb 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -107,6 +107,7 @@ #define VM_EXIT_PT_CONCEAL_PIP 0x01000000 #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 #define VM_EXIT_LOAD_CET_STATE 0x10000000 +#define VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000 =20 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff =20 @@ -262,6 +263,8 @@ enum vmcs_field { SHARED_EPT_POINTER =3D 0x0000203C, PID_POINTER_TABLE =3D 0x00002042, PID_POINTER_TABLE_HIGH =3D 0x00002043, + SECONDARY_VM_EXIT_CONTROLS =3D 0x00002044, + SECONDARY_VM_EXIT_CONTROLS_HIGH =3D 0x00002045, GUEST_PHYSICAL_ADDRESS =3D 0x00002400, GUEST_PHYSICAL_ADDRESS_HIGH =3D 0x00002401, VMCS_LINK_POINTER =3D 0x00002800, diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index 47b0dec8665a..7b9e306c359d 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -58,8 +58,9 @@ struct vmcs_config { u32 cpu_based_exec_ctrl; u32 cpu_based_2nd_exec_ctrl; u64 cpu_based_3rd_exec_ctrl; - u32 vmexit_ctrl; u32 vmentry_ctrl; + u32 vmexit_ctrl; + u64 vmexit_2nd_ctrl; u64 misc; struct nested_vmx_msrs nested; }; @@ -144,6 +145,12 @@ static inline bool cpu_has_tertiary_exec_ctrls(void) CPU_BASED_ACTIVATE_TERTIARY_CONTROLS; } =20 +static inline bool cpu_has_secondary_vmexit_ctrls(void) +{ + return vmcs_config.vmexit_ctrl & + VM_EXIT_ACTIVATE_SECONDARY_CONTROLS; +} + static inline bool cpu_has_vmx_virtualize_apic_accesses(void) { return vmcs_config.cpu_based_2nd_exec_ctrl & diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h index b25625314658..ae152a9d1963 100644 --- a/arch/x86/kvm/vmx/vmcs.h +++ b/arch/x86/kvm/vmx/vmcs.h @@ -47,6 +47,7 @@ struct vmcs_host_state { struct vmcs_controls_shadow { u32 vm_entry; u32 vm_exit; + u64 secondary_vm_exit; u32 pin; u32 exec; u32 secondary_exec; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 989008f5307e..590e0826ba08 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2596,8 +2596,9 @@ static int setup_vmcs_config(struct vmcs_config *vmcs= _conf, u32 _cpu_based_exec_control =3D 0; u32 _cpu_based_2nd_exec_control =3D 0; u64 _cpu_based_3rd_exec_control =3D 0; - u32 _vmexit_control =3D 0; u32 _vmentry_control =3D 0; + u32 _vmexit_control =3D 0; + u64 _vmexit2_control =3D 0; u64 basic_msr; u64 misc_msr; =20 @@ -2618,6 +2619,12 @@ static int setup_vmcs_config(struct vmcs_config *vmc= s_conf, { VM_ENTRY_LOAD_CET_STATE, VM_EXIT_LOAD_CET_STATE }, }; =20 + struct { + u32 entry_control; + u64 exit_control; + } const vmcs_entry_exit2_pairs[] =3D { + }; + memset(vmcs_conf, 0, sizeof(*vmcs_conf)); =20 if (adjust_vmx_controls(KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL, @@ -2704,10 +2711,19 @@ static int setup_vmcs_config(struct vmcs_config *vm= cs_conf, &_vmentry_control)) return -EIO; =20 + if (_vmexit_control & VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) + _vmexit2_control =3D + adjust_vmx_controls64(KVM_OPTIONAL_VMX_SECONDARY_VM_EXIT_CONTROLS, + MSR_IA32_VMX_EXIT_CTLS2); + if (vmx_check_entry_exit_pairs(vmcs_entry_exit_pairs, _vmentry_control, _vmexit_control)) return -EIO; =20 + if (vmx_check_entry_exit_pairs(vmcs_entry_exit2_pairs, + _vmentry_control, _vmexit2_control)) + return -EIO; + /* * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they * can't be used due to an errata where VM Exit may incorrectly clear @@ -2756,8 +2772,9 @@ static int setup_vmcs_config(struct vmcs_config *vmcs= _conf, vmcs_conf->cpu_based_exec_ctrl =3D _cpu_based_exec_control; vmcs_conf->cpu_based_2nd_exec_ctrl =3D _cpu_based_2nd_exec_control; vmcs_conf->cpu_based_3rd_exec_ctrl =3D _cpu_based_3rd_exec_control; - vmcs_conf->vmexit_ctrl =3D _vmexit_control; vmcs_conf->vmentry_ctrl =3D _vmentry_control; + vmcs_conf->vmexit_ctrl =3D _vmexit_control; + vmcs_conf->vmexit_2nd_ctrl =3D _vmexit2_control; vmcs_conf->misc =3D misc_msr; =20 #if IS_ENABLED(CONFIG_HYPERV) @@ -4406,6 +4423,11 @@ static u32 vmx_vmexit_ctrl(void) ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER); } =20 +static u64 vmx_secondary_vmexit_ctrl(void) +{ + return vmcs_config.vmexit_2nd_ctrl; +} + void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx =3D to_vmx(vcpu); @@ -4754,6 +4776,9 @@ static void init_vmcs(struct vcpu_vmx *vmx) =20 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); =20 + if (cpu_has_secondary_vmexit_ctrls()) + secondary_vm_exit_controls_set(vmx, vmx_secondary_vmexit_ctrl()); + /* 22.2.1, 20.8.1 */ vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); =20 diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index ecfdba666465..840e48a2fcc5 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -511,7 +511,11 @@ static inline u8 vmx_get_rvi(void) VM_EXIT_CLEAR_BNDCFGS | \ VM_EXIT_PT_CONCEAL_PIP | \ VM_EXIT_CLEAR_IA32_RTIT_CTL | \ - VM_EXIT_LOAD_CET_STATE) + VM_EXIT_LOAD_CET_STATE | \ + VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) + +#define KVM_REQUIRED_VMX_SECONDARY_VM_EXIT_CONTROLS (0) +#define KVM_OPTIONAL_VMX_SECONDARY_VM_EXIT_CONTROLS (0) =20 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ (PIN_BASED_EXT_INTR_MASK | \ @@ -616,6 +620,7 @@ static __always_inline void lname##_controls_clearbit(s= truct vcpu_vmx *vmx, u##b } BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) +BUILD_CONTROLS_SHADOW(secondary_vm_exit, SECONDARY_VM_EXIT_CONTROLS, 64) BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32) BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32) BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32) --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C8CD31064E; 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arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="YREQ55ny" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo482871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:13 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo482871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481534; bh=febSAquEyZNB4upRK2xjrDEFN+GEHBHhYW+/4ob2MDg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YREQ55nyPG4vo4VnJ7/Yl+E/A336mnU5pBIqRKXfDb/ZKh1dX55tL5YfSKVSZxzzv 5eozUDTjosrMeRUp7s+rd766vIfu72UnO9y2THsJ7AoBrx9hOeiHG94snLfKg3k95B MfSy7toC5ajZCqjQPGF+6DhoTUrh1ZTeBvW1BxpHDXPwNCsaMueA8dZrudv36AdBon /mUaYtaoSRmftwSEE7oehedSMJUS6JT96caTKoFe96izbmRUE9C5ASfH/98Jhi87Qb ewieuTz0Vrgk920poWf3eBvTw5xlnX8lJ0ZBMWLwuBieZT1+mYtemP85+DUskd4Wwn hcTIPAssBpfcA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 02/21] KVM: VMX: Initialize VM entry/exit FRED controls in vmcs_config Date: Fri, 29 Aug 2025 08:31:30 -0700 Message-ID: <20250829153149.2871901-3-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Setup VM entry/exit FRED controls in the global vmcs_config for proper FRED VMCS fields management: 1) load guest FRED state upon VM entry. 2) save guest FRED state during VM exit. 3) load host FRED state during VM exit. Also add FRED control consistency checks to the existing VM entry/exit consistency check framework. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo Reviewed-by: Chao Gao --- Change in v5: * Remove the pair VM_ENTRY_LOAD_IA32_FRED/VM_EXIT_ACTIVATE_SECONDARY_CONTRO= LS, since the secondary VM exit controls are unconditionally enabled anyway, = and there are features other than FRED needing it (Chao Gao). * Add TB from Xuelian Guo. Change in v4: * Do VM exit/entry consistency checks using the new macro from Sean Christopherson. Changes in v3: * Add FRED control consistency checks to the existing VM entry/exit consistency check framework (Sean Christopherson). * Just do the unnecessary FRED state load/store on every VM entry/exit (Sean Christopherson). --- arch/x86/include/asm/vmx.h | 4 ++++ arch/x86/kvm/vmx/vmx.c | 2 ++ arch/x86/kvm/vmx/vmx.h | 7 +++++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 1f60c04d11fb..dd79d027ea70 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -109,6 +109,9 @@ #define VM_EXIT_LOAD_CET_STATE 0x10000000 #define VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000 =20 +#define SECONDARY_VM_EXIT_SAVE_IA32_FRED BIT_ULL(0) +#define SECONDARY_VM_EXIT_LOAD_IA32_FRED BIT_ULL(1) + #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff =20 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 @@ -122,6 +125,7 @@ #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000 #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 #define VM_ENTRY_LOAD_CET_STATE 0x00100000 +#define VM_ENTRY_LOAD_IA32_FRED 0x00800000 =20 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 590e0826ba08..3b5e2805a06d 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2623,6 +2623,8 @@ static int setup_vmcs_config(struct vmcs_config *vmcs= _conf, u32 entry_control; u64 exit_control; } const vmcs_entry_exit2_pairs[] =3D { + { VM_ENTRY_LOAD_IA32_FRED, + SECONDARY_VM_EXIT_SAVE_IA32_FRED | SECONDARY_VM_EXIT_LOAD_IA32_FRED }, }; =20 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 840e48a2fcc5..e577af1003d8 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -488,7 +488,8 @@ static inline u8 vmx_get_rvi(void) VM_ENTRY_LOAD_BNDCFGS | \ VM_ENTRY_PT_CONCEAL_PIP | \ VM_ENTRY_LOAD_IA32_RTIT_CTL | \ - VM_ENTRY_LOAD_CET_STATE) + VM_ENTRY_LOAD_CET_STATE | \ + VM_ENTRY_LOAD_IA32_FRED) =20 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ (VM_EXIT_SAVE_DEBUG_CONTROLS | \ @@ -515,7 +516,9 @@ static inline u8 vmx_get_rvi(void) VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) =20 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXIT_CONTROLS (0) -#define KVM_OPTIONAL_VMX_SECONDARY_VM_EXIT_CONTROLS (0) +#define KVM_OPTIONAL_VMX_SECONDARY_VM_EXIT_CONTROLS \ + (SECONDARY_VM_EXIT_SAVE_IA32_FRED | \ + SECONDARY_VM_EXIT_LOAD_IA32_FRED) =20 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ (PIN_BASED_EXT_INTR_MASK | \ --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F24BE322750; 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charset="utf-8" From: Xin Li Do not virtualize FRED if FRED consistency checks fail. Either on broken hardware, or when run KVM on top of another hypervisor before the underlying hypervisor implements nested FRED correctly. Suggested-by: Chao Gao Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Reviewed-by: Chao Gao Tested-by: Shan Kang Tested-by: Xuelian Guo --- Changes in v5: * Drop the cpu_feature_enabled() in cpu_has_vmx_fred() (Sean). * Add TB from Xuelian Guo. Change in v4: * Call out the reason why not check FRED VM-exit controls in cpu_has_vmx_fred() (Chao Gao). --- arch/x86/kvm/vmx/capabilities.h | 10 ++++++++++ arch/x86/kvm/vmx/vmx.c | 3 +++ 2 files changed, 13 insertions(+) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index 7b9e306c359d..7fe95a601c9f 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -408,6 +408,16 @@ static inline bool vmx_pebs_supported(void) return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept; } =20 +static inline bool cpu_has_vmx_fred(void) +{ + /* + * setup_vmcs_config() guarantees FRED VM-entry/exit controls + * are either all set or none. So, no need to check FRED VM-exit + * controls. + */ + return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_FRED); +} + static inline bool cpu_has_notify_vmexit(void) { return vmcs_config.cpu_based_2nd_exec_ctrl & diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 3b5e2805a06d..c8b95c215869 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7993,6 +7993,9 @@ static __init void vmx_set_cpu_caps(void) kvm_cpu_cap_check_and_set(X86_FEATURE_DTES64); } =20 + if (!cpu_has_vmx_fred()) + kvm_cpu_cap_clear(X86_FEATURE_FRED); + if (!enable_pmu) kvm_cpu_cap_clear(X86_FEATURE_PDCM); kvm_caps.supported_perf_cap =3D vmx_get_perf_capabilities(); --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 076CD322A1B; Fri, 29 Aug 2025 15:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481591; cv=none; b=kIvJ56x4dCIcjPU2h2DFU1OJPx0r0gr89f02wVp8mzItcsndw+o/qxd6iFkaDoHQydI7P+RU/M279ewW5+EX/apLlvW5fM9YL0Du1bdubzt8sSC/VqQZDNX+y9FXkH2FoW0mWONfkpuAlxuo/lBF0juPSNPsB1Oi1PqojntXpJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481591; c=relaxed/simple; bh=0f5Md5XSXilShhWXgBqtBCoet75joAtRIZT3JPPoEgo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TeAlVvgeW5LQsUFy0dWU+e5bkumK1i4C9DVwq0Zr0u0JcEx5BKIs3CKwN2rBdwRQGT7exritG1dKdcov7dns8rD4pY0i4dp0WOtUXKjy2SbFxd5XSFVlRu4epsyqjhgTZ+K/yt5A4UjeEEk8ia8+og1xuaoG6kImQ0XYYEA3oBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=At9YR4US; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="At9YR4US" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4A2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:15 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4A2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481536; bh=FIYL8ksvIB3wOVrxze4s41+WDAAwTEKhjiDnFUYmjYA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=At9YR4USFu8aWwz871/z2W1uuSmyPjiWQgmSR0lLvdVVYyKGdN6rBAm37qzO3eNl2 0nGFbMiJnVqFZKBOKlR7FaYl04b1JT3tzrIlFYPeX+t3d4y/92AU0JeCKyFcjcRlAW PnRcMBVCcLnWW1gYxslRgtAueZJw6ZZ4/lYrXGNRjnUH6UjdUZ7v0hUW0SP2GnjVL2 3RK242QSY2H8+jjTJux9ZNHSXYuQCxVx7s+PjNhhtlR+vqGBgxkSF8sVU5+0xAp1Yv qgKAGbYvt5xCJ/b2ydQB+23QOTRK744fMO3D1n1j/klXUWs9E8y0QgkoeCiN6g7DTf ZQVq3Fb50S1cQ== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 04/21] x86/cea: Prefix event stack names with ESTACK_ Date: Fri, 29 Aug 2025 08:31:32 -0700 Message-ID: <20250829153149.2871901-5-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the ESTACK_ prefix to event stack names to improve clarity and readability. Without the prefix, names like DF, NMI, and DB are too brief and potentially ambiguous. This renaming also prepares for converting __this_cpu_ist_top_va from a macro into a function that accepts an enum exception_stack_ordering argument, without requiring changes to existing callsites. Signed-off-by: Xin Li (Intel) --- Changes in v7: * Move rename code to this patch (Dave Hansen). * Fix a vertical alignment (Dave Hansen). --- arch/x86/coco/sev/sev-nmi.c | 4 ++-- arch/x86/coco/sev/vc-handle.c | 2 +- arch/x86/include/asm/cpu_entry_area.h | 26 +++++++++++++------------- arch/x86/kernel/cpu/common.c | 10 +++++----- arch/x86/kernel/dumpstack_64.c | 14 +++++++------- arch/x86/kernel/fred.c | 6 +++--- arch/x86/kernel/traps.c | 2 +- arch/x86/mm/cpu_entry_area.c | 12 ++++++------ arch/x86/mm/fault.c | 2 +- 9 files changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/x86/coco/sev/sev-nmi.c b/arch/x86/coco/sev/sev-nmi.c index d8dfaddfb367..73e34ad7a1a9 100644 --- a/arch/x86/coco/sev/sev-nmi.c +++ b/arch/x86/coco/sev/sev-nmi.c @@ -30,7 +30,7 @@ static __always_inline bool on_vc_stack(struct pt_regs *r= egs) if (ip_within_syscall_gap(regs)) return false; =20 - return ((sp >=3D __this_cpu_ist_bottom_va(VC)) && (sp < __this_cpu_ist_to= p_va(VC))); + return ((sp >=3D __this_cpu_ist_bottom_va(ESTACK_VC)) && (sp < __this_cpu= _ist_top_va(ESTACK_VC))); } =20 /* @@ -82,7 +82,7 @@ void noinstr __sev_es_ist_exit(void) /* Read IST entry */ ist =3D __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]); =20 - if (WARN_ON(ist =3D=3D __this_cpu_ist_top_va(VC))) + if (WARN_ON(ist =3D=3D __this_cpu_ist_top_va(ESTACK_VC))) return; =20 /* Read back old IST entry and write it to the TSS */ diff --git a/arch/x86/coco/sev/vc-handle.c b/arch/x86/coco/sev/vc-handle.c index c3b4acbde0d8..88b6bc518a5a 100644 --- a/arch/x86/coco/sev/vc-handle.c +++ b/arch/x86/coco/sev/vc-handle.c @@ -859,7 +859,7 @@ static enum es_result vc_handle_exitcode(struct es_em_c= txt *ctxt, =20 static __always_inline bool is_vc2_stack(unsigned long sp) { - return (sp >=3D __this_cpu_ist_bottom_va(VC2) && sp < __this_cpu_ist_top_= va(VC2)); + return (sp >=3D __this_cpu_ist_bottom_va(ESTACK_VC2) && sp < __this_cpu_i= st_top_va(ESTACK_VC2)); } =20 static __always_inline bool vc_from_invalid_context(struct pt_regs *regs) diff --git a/arch/x86/include/asm/cpu_entry_area.h b/arch/x86/include/asm/c= pu_entry_area.h index 462fc34f1317..d0f884c28178 100644 --- a/arch/x86/include/asm/cpu_entry_area.h +++ b/arch/x86/include/asm/cpu_entry_area.h @@ -18,19 +18,19 @@ =20 /* Macro to enforce the same ordering and stack sizes */ #define ESTACKS_MEMBERS(guardsize, optional_stack_size) \ - char DF_stack_guard[guardsize]; \ - char DF_stack[EXCEPTION_STKSZ]; \ - char NMI_stack_guard[guardsize]; \ - char NMI_stack[EXCEPTION_STKSZ]; \ - char DB_stack_guard[guardsize]; \ - char DB_stack[EXCEPTION_STKSZ]; \ - char MCE_stack_guard[guardsize]; \ - char MCE_stack[EXCEPTION_STKSZ]; \ - char VC_stack_guard[guardsize]; \ - char VC_stack[optional_stack_size]; \ - char VC2_stack_guard[guardsize]; \ - char VC2_stack[optional_stack_size]; \ - char IST_top_guard[guardsize]; \ + char ESTACK_DF_stack_guard[guardsize]; \ + char ESTACK_DF_stack[EXCEPTION_STKSZ]; \ + char ESTACK_NMI_stack_guard[guardsize]; \ + char ESTACK_NMI_stack[EXCEPTION_STKSZ]; \ + char ESTACK_DB_stack_guard[guardsize]; \ + char ESTACK_DB_stack[EXCEPTION_STKSZ]; \ + char ESTACK_MCE_stack_guard[guardsize]; \ + char ESTACK_MCE_stack[EXCEPTION_STKSZ]; \ + char ESTACK_VC_stack_guard[guardsize]; \ + char ESTACK_VC_stack[optional_stack_size]; \ + char ESTACK_VC2_stack_guard[guardsize]; \ + char ESTACK_VC2_stack[optional_stack_size]; \ + char ESTACK_IST_top_guard[guardsize]; \ =20 /* The exception stacks' physical storage. No guard pages required */ struct exception_stacks { diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 34a054181c4d..5c888f1783e5 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2307,12 +2307,12 @@ static inline void setup_getcpu(int cpu) static inline void tss_setup_ist(struct tss_struct *tss) { /* Set up the per-CPU TSS IST stacks */ - tss->x86_tss.ist[IST_INDEX_DF] =3D __this_cpu_ist_top_va(DF); - tss->x86_tss.ist[IST_INDEX_NMI] =3D __this_cpu_ist_top_va(NMI); - tss->x86_tss.ist[IST_INDEX_DB] =3D __this_cpu_ist_top_va(DB); - tss->x86_tss.ist[IST_INDEX_MCE] =3D __this_cpu_ist_top_va(MCE); + tss->x86_tss.ist[IST_INDEX_DF] =3D __this_cpu_ist_top_va(ESTACK_DF); + tss->x86_tss.ist[IST_INDEX_NMI] =3D __this_cpu_ist_top_va(ESTACK_NMI); + tss->x86_tss.ist[IST_INDEX_DB] =3D __this_cpu_ist_top_va(ESTACK_DB); + tss->x86_tss.ist[IST_INDEX_MCE] =3D __this_cpu_ist_top_va(ESTACK_MCE); /* Only mapped when SEV-ES is active */ - tss->x86_tss.ist[IST_INDEX_VC] =3D __this_cpu_ist_top_va(VC); + tss->x86_tss.ist[IST_INDEX_VC] =3D __this_cpu_ist_top_va(ESTACK_VC); } #else /* CONFIG_X86_64 */ static inline void tss_setup_ist(struct tss_struct *tss) { } diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c index 6c5defd6569a..40f51e278171 100644 --- a/arch/x86/kernel/dumpstack_64.c +++ b/arch/x86/kernel/dumpstack_64.c @@ -73,7 +73,7 @@ struct estack_pages { PFN_DOWN(CEA_ESTACK_OFFS(st) + CEA_ESTACK_SIZE(st) - 1)] =3D { \ .offs =3D CEA_ESTACK_OFFS(st), \ .size =3D CEA_ESTACK_SIZE(st), \ - .type =3D STACK_TYPE_EXCEPTION + ESTACK_ ##st, } + .type =3D STACK_TYPE_EXCEPTION + st, } =20 /* * Array of exception stack page descriptors. If the stack is larger than @@ -83,12 +83,12 @@ struct estack_pages { */ static const struct estack_pages estack_pages[CEA_ESTACK_PAGES] ____cacheline_aligned = =3D { - EPAGERANGE(DF), - EPAGERANGE(NMI), - EPAGERANGE(DB), - EPAGERANGE(MCE), - EPAGERANGE(VC), - EPAGERANGE(VC2), + EPAGERANGE(ESTACK_DF), + EPAGERANGE(ESTACK_NMI), + EPAGERANGE(ESTACK_DB), + EPAGERANGE(ESTACK_MCE), + EPAGERANGE(ESTACK_VC), + EPAGERANGE(ESTACK_VC2), }; =20 static __always_inline bool in_exception_stack(unsigned long *stack, struc= t stack_info *info) diff --git a/arch/x86/kernel/fred.c b/arch/x86/kernel/fred.c index 816187da3a47..06d944a3d051 100644 --- a/arch/x86/kernel/fred.c +++ b/arch/x86/kernel/fred.c @@ -87,7 +87,7 @@ void cpu_init_fred_rsps(void) FRED_STKLVL(X86_TRAP_DF, FRED_DF_STACK_LEVEL)); =20 /* The FRED equivalents to IST stacks... */ - wrmsrq(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); - wrmsrq(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); - wrmsrq(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); + wrmsrq(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(ESTACK_DB)); + wrmsrq(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(ESTACK_NMI)); + wrmsrq(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(ESTACK_DF)); } diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 36354b470590..5c9c5ebf5e73 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -954,7 +954,7 @@ asmlinkage __visible noinstr struct pt_regs *vc_switch_= off_ist(struct pt_regs *r =20 if (!get_stack_info_noinstr(stack, current, &info) || info.type =3D=3D ST= ACK_TYPE_ENTRY || info.type > STACK_TYPE_EXCEPTION_LAST) - sp =3D __this_cpu_ist_top_va(VC2); + sp =3D __this_cpu_ist_top_va(ESTACK_VC2); =20 sync: /* diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c index 575f863f3c75..9fa371af8abc 100644 --- a/arch/x86/mm/cpu_entry_area.c +++ b/arch/x86/mm/cpu_entry_area.c @@ -151,15 +151,15 @@ static void __init percpu_setup_exception_stacks(unsi= gned int cpu) * by guard pages so each stack must be mapped separately. DB2 is * not mapped; it just exists to catch triple nesting of #DB. */ - cea_map_stack(DF); - cea_map_stack(NMI); - cea_map_stack(DB); - cea_map_stack(MCE); + cea_map_stack(ESTACK_DF); + cea_map_stack(ESTACK_NMI); + cea_map_stack(ESTACK_DB); + cea_map_stack(ESTACK_MCE); =20 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) { if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) { - cea_map_stack(VC); - cea_map_stack(VC2); + cea_map_stack(ESTACK_VC); + cea_map_stack(ESTACK_VC2); } } } diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 998bd807fc7b..1804eb86cc14 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -671,7 +671,7 @@ page_fault_oops(struct pt_regs *regs, unsigned long err= or_code, * and then double-fault, though, because we're likely to * break the console driver and lose most of the stack dump. */ - call_on_stack(__this_cpu_ist_top_va(DF) - sizeof(void*), + call_on_stack(__this_cpu_ist_top_va(ESTACK_DF) - sizeof(void*), handle_stack_overflow, ASM_CALL_ARG3, , [arg1] "r" (regs), [arg2] "r" (address), [arg3] "r" (&info)); --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D56A1F2382; Fri, 29 Aug 2025 15:33:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481588; cv=none; b=NIjEh6vzj7heMqr3wgJvIyDrRUKPUcyn4ZpBa8VvnZ1Ksn7vzRqyvUkwLR1EzXTFOjIpgrcZpu70f02oyu0u49A5W9udA6B8t3lb256OmlPXYv6hy58nWJ/JCge4GLsb1onqQWM1sX14F8HMc88sxNObwwLPiTaHkb9swIYKKvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481588; c=relaxed/simple; bh=boYL1l9xLWGo3/2NolmH1TULXM2fhR0/YNy1xNfKfLw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QQx+lC0CFNBOBcA2KO2Lp2P6Y2FZ/6F74Q+bA4aiLiF0qmsKOm8/pipJzVml5AVqSRC+n907CVZ37x9iybQEM4oTDErV9vnYGVYz7+n/TXWqNotUZ38tI+dkvI5wg1OTwJFuT/N5n8IpVK0CNIRz4c2Cv1JC5UFEU4rRw7/b1n8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=PTY0zdud; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="PTY0zdud" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4B2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:16 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4B2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481537; bh=z2lJVqJT0UMdIkbScgCd4Til78kV6zueUTLcEHbIfcE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PTY0zdudJdqO1RYUAVTWmiL5CE/RYZ5GK42VNYODYMqm58F5tBp513OuCe42lqwha bk5RHF30YlAg6UCqGMMZ1L4yRmoCmG9dTyJiHlk6TN14EYO7fA7IhFyYb7QaXwAB9f fk6znHgYfAfagwrp9pjwKowrhChYN87MDbW9NGQ+AIsEr6T64RMf6M3cB1WQm7hOyu JfGT53AfhbslvmFOXmS7olsBOeNLgNUxNrN7dQ1u4vFFh0ia7Yi6CuxqFcjRm0nrUH 17zplyWjx6bKaM4t1B7adVRxwST06YD8nGIaVUfQytpKd5Ge5L2SyDF2b+1k0uy4St 6zwY5YPSr+kTg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 05/21] x86/cea: Export API for per-CPU exception stacks for KVM Date: Fri, 29 Aug 2025 08:31:33 -0700 Message-ID: <20250829153149.2871901-6-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the __this_cpu_ist_{top,bottom}_va() macros into proper functions, and export __this_cpu_ist_top_va() to allow KVM to retrieve the top of the per-CPU exception stack. FRED introduced new fields in the host-state area of the VMCS for stack levels 1->3 (HOST_IA32_FRED_RSP[123]), each respectively corresponding to per-CPU exception stacks for #DB, NMI and #DF. KVM must populate these fields each time a vCPU is loaded onto a CPU. To simplify access to the exception stacks in struct cea_exception_stacks, a union is used to create an array alias, enabling array-style indexing of the stack entries. Signed-off-by: Xin Li (Intel) --- Change in v7: * Remove Suggested-bys (Dave Hansen). * Move rename code in a separate patch (Dave Hansen). * Access cea_exception_stacks using array indexing (Dave Hansen). * Use BUILD_BUG_ON(ESTACK_DF !=3D 0) to ensure the starting index is 0 (Dave Hansen). Change in v5: * Export accessor instead of data (Christoph Hellwig). * Add TB from Xuelian Guo. Change in v4: * Rewrite the change log and add comments to the export (Dave Hansen). --- arch/x86/include/asm/cpu_entry_area.h | 51 +++++++++++++-------------- arch/x86/mm/cpu_entry_area.c | 25 +++++++++++++ 2 files changed, 50 insertions(+), 26 deletions(-) diff --git a/arch/x86/include/asm/cpu_entry_area.h b/arch/x86/include/asm/c= pu_entry_area.h index d0f884c28178..58cd71144e5e 100644 --- a/arch/x86/include/asm/cpu_entry_area.h +++ b/arch/x86/include/asm/cpu_entry_area.h @@ -16,6 +16,19 @@ #define VC_EXCEPTION_STKSZ 0 #endif =20 +/* + * The exception stack ordering in [cea_]exception_stacks + */ +enum exception_stack_ordering { + ESTACK_DF, + ESTACK_NMI, + ESTACK_DB, + ESTACK_MCE, + ESTACK_VC, + ESTACK_VC2, + N_EXCEPTION_STACKS +}; + /* Macro to enforce the same ordering and stack sizes */ #define ESTACKS_MEMBERS(guardsize, optional_stack_size) \ char ESTACK_DF_stack_guard[guardsize]; \ @@ -39,37 +52,29 @@ struct exception_stacks { =20 /* The effective cpu entry area mapping with guard pages. */ struct cea_exception_stacks { - ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ) -}; - -/* - * The exception stack ordering in [cea_]exception_stacks - */ -enum exception_stack_ordering { - ESTACK_DF, - ESTACK_NMI, - ESTACK_DB, - ESTACK_MCE, - ESTACK_VC, - ESTACK_VC2, - N_EXCEPTION_STACKS + union{ + struct { + ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ) + }; + struct { + char stack_guard[PAGE_SIZE]; + char stack[EXCEPTION_STKSZ]; + } event_stacks[N_EXCEPTION_STACKS]; + }; }; =20 #define CEA_ESTACK_SIZE(st) \ sizeof(((struct cea_exception_stacks *)0)->st## _stack) =20 -#define CEA_ESTACK_BOT(ceastp, st) \ - ((unsigned long)&(ceastp)->st## _stack) - -#define CEA_ESTACK_TOP(ceastp, st) \ - (CEA_ESTACK_BOT(ceastp, st) + CEA_ESTACK_SIZE(st)) - #define CEA_ESTACK_OFFS(st) \ offsetof(struct cea_exception_stacks, st## _stack) =20 #define CEA_ESTACK_PAGES \ (sizeof(struct cea_exception_stacks) / PAGE_SIZE) =20 +extern unsigned long __this_cpu_ist_top_va(enum exception_stack_ordering s= tack); +extern unsigned long __this_cpu_ist_bottom_va(enum exception_stack_orderin= g stack); + #endif =20 #ifdef CONFIG_X86_32 @@ -144,10 +149,4 @@ static __always_inline struct entry_stack *cpu_entry_s= tack(int cpu) return &get_cpu_entry_area(cpu)->entry_stack_page.stack; } =20 -#define __this_cpu_ist_top_va(name) \ - CEA_ESTACK_TOP(__this_cpu_read(cea_exception_stacks), name) - -#define __this_cpu_ist_bottom_va(name) \ - CEA_ESTACK_BOT(__this_cpu_read(cea_exception_stacks), name) - #endif diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c index 9fa371af8abc..595c2e03ddd5 100644 --- a/arch/x86/mm/cpu_entry_area.c +++ b/arch/x86/mm/cpu_entry_area.c @@ -18,6 +18,31 @@ static DEFINE_PER_CPU_PAGE_ALIGNED(struct entry_stack_pa= ge, entry_stack_storage) static DEFINE_PER_CPU_PAGE_ALIGNED(struct exception_stacks, exception_stac= ks); DEFINE_PER_CPU(struct cea_exception_stacks*, cea_exception_stacks); =20 +/* + * FRED introduced new fields in the host-state area of the VMCS for + * stack levels 1->3 (HOST_IA32_FRED_RSP[123]), each respectively + * corresponding to per CPU stacks for #DB, NMI and #DF. KVM must + * populate these each time a vCPU is loaded onto a CPU. + * + * Called from entry code, so must be noinstr. + */ +noinstr unsigned long __this_cpu_ist_bottom_va(enum exception_stack_orderi= ng stack) +{ + struct cea_exception_stacks *s; + + BUILD_BUG_ON(ESTACK_DF !=3D 0); + + s =3D __this_cpu_read(cea_exception_stacks); + + return (unsigned long)&s->event_stacks[stack].stack; +} + +noinstr unsigned long __this_cpu_ist_top_va(enum exception_stack_ordering = stack) +{ + return __this_cpu_ist_bottom_va(stack) + EXCEPTION_STKSZ; +} +EXPORT_SYMBOL(__this_cpu_ist_top_va); + static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, _cea_offset); =20 static __always_inline unsigned int cea_offset(unsigned int cpu) --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 908DB320389; Fri, 29 Aug 2025 15:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481591; cv=none; b=PL9+GCAkPWExRYeEqzSoDjAmoTSBZAgm6QwC81IvzMXZ1DCVuwBiOxtV5/cV3aZQWsnWsTTmlvS8W2k76Jn2KJcSwzvX0ZarEqT9kaOYFBXO5vjkvmqf1+11EHgSYcvpbWByVpmt2MkZqRsBplQ8+dGVTGOrnG/M6hAPdBbZqhk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481591; c=relaxed/simple; bh=LUB8S/9zQlfe+FMfxRkxfpyEEIeTs5iSwBYJ8HJ0p84=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C5CDjFLf5SqeiGKWVJeN0d4HNl9DoF/WoQRednVj2QcMX1VODLLe9e1kwRdDpXrLMOz3CsOz81prkmox4nysT7upB63rfCRGBoJob+R5ZSjZmc/sPZxh2DwnmPesWbeTg3BacfRnl+731DORHEZdTmk9lPp7Wub5vtdFr8ZOcKE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=A4Dyqw9L; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="A4Dyqw9L" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4C2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:17 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4C2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481538; bh=kCEtrMvfk0PSIuAHRru4DrevfRxLJgJrqIuIB4hgTRI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A4Dyqw9LnZt/LnNJn00IGTyQcMKTLawyjE7wuj0Q2hF3WDFo9e6Fa7cXNxDQWKXN9 ohKsLt/gMvAKuUJZAcCTS1Ac2gsKQ/TP7hcSavch1U6smPNZvNTGOhme/yVgnZXNwb 5phWI44y+ifpfxKKiLVeIrXuxppK2M0rlKmB+ep38oa46eYs4nP+2JA4sXnxWyyZfw gM5sjgu0H3X5VFrZuU5L1dP982dtFQy4grOIYnjyq0IbOXpcPPeKve95ccIpoNcDGc wu+QGul83QiNvuAfiUJa/fHTb+FEvS8i/bvJjoW45RhPNl+d4+oDREtWW2iqINAx0S JEiVlAuwO53iQ== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 06/21] KVM: VMX: Initialize VMCS FRED fields Date: Fri, 29 Aug 2025 08:31:34 -0700 Message-ID: <20250829153149.2871901-7-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Initialize host VMCS FRED fields with host FRED MSRs' value and guest VMCS FRED fields to 0. FRED CPU state is managed in 9 new FRED MSRs: IA32_FRED_CONFIG, IA32_FRED_STKLVLS, IA32_FRED_RSP0, IA32_FRED_RSP1, IA32_FRED_RSP2, IA32_FRED_RSP3, IA32_FRED_SSP1, IA32_FRED_SSP2, IA32_FRED_SSP3, as well as a few existing CPU registers and MSRs: CR4.FRED, IA32_STAR, IA32_KERNEL_GS_BASE, IA32_PL0_SSP (also known as IA32_FRED_SSP0). CR4, IA32_KERNEL_GS_BASE and IA32_STAR are already well managed. Except IA32_FRED_RSP0 and IA32_FRED_SSP0, all other FRED CPU state MSRs have corresponding VMCS fields in both the host-state and guest-state areas. So KVM just needs to initialize them, and with proper VM entry/exit FRED controls, a FRED CPU will keep tracking host and guest FRED CPU state in VMCS automatically. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. Change in v4: * Initialize host SSP[1-3] to 0s in vmx_set_constant_host_state() because Linux doesn't support kernel shadow stacks (Chao Gao). Change in v3: * Use structure kvm_host_values to keep host fred config & stack levels (Sean Christopherson). Changes in v2: * Use kvm_cpu_cap_has() instead of cpu_feature_enabled() to decouple KVM's capability to virtualize a feature and host's enabling of a feature (Chao Gao). * Move guest FRED state init into __vmx_vcpu_reset() (Chao Gao). --- arch/x86/include/asm/vmx.h | 32 ++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 36 ++++++++++++++++++++++++++++++++++++ arch/x86/kvm/x86.h | 3 +++ 3 files changed, 71 insertions(+) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index dd79d027ea70..6f8b8947c60c 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -293,12 +293,44 @@ enum vmcs_field { GUEST_BNDCFGS_HIGH =3D 0x00002813, GUEST_IA32_RTIT_CTL =3D 0x00002814, GUEST_IA32_RTIT_CTL_HIGH =3D 0x00002815, + GUEST_IA32_FRED_CONFIG =3D 0x0000281a, + GUEST_IA32_FRED_CONFIG_HIGH =3D 0x0000281b, + GUEST_IA32_FRED_RSP1 =3D 0x0000281c, + GUEST_IA32_FRED_RSP1_HIGH =3D 0x0000281d, + GUEST_IA32_FRED_RSP2 =3D 0x0000281e, + GUEST_IA32_FRED_RSP2_HIGH =3D 0x0000281f, + GUEST_IA32_FRED_RSP3 =3D 0x00002820, + GUEST_IA32_FRED_RSP3_HIGH =3D 0x00002821, + GUEST_IA32_FRED_STKLVLS =3D 0x00002822, + GUEST_IA32_FRED_STKLVLS_HIGH =3D 0x00002823, + GUEST_IA32_FRED_SSP1 =3D 0x00002824, + GUEST_IA32_FRED_SSP1_HIGH =3D 0x00002825, + GUEST_IA32_FRED_SSP2 =3D 0x00002826, + GUEST_IA32_FRED_SSP2_HIGH =3D 0x00002827, + GUEST_IA32_FRED_SSP3 =3D 0x00002828, + GUEST_IA32_FRED_SSP3_HIGH =3D 0x00002829, HOST_IA32_PAT =3D 0x00002c00, HOST_IA32_PAT_HIGH =3D 0x00002c01, HOST_IA32_EFER =3D 0x00002c02, HOST_IA32_EFER_HIGH =3D 0x00002c03, HOST_IA32_PERF_GLOBAL_CTRL =3D 0x00002c04, HOST_IA32_PERF_GLOBAL_CTRL_HIGH =3D 0x00002c05, + HOST_IA32_FRED_CONFIG =3D 0x00002c08, + HOST_IA32_FRED_CONFIG_HIGH =3D 0x00002c09, + HOST_IA32_FRED_RSP1 =3D 0x00002c0a, + HOST_IA32_FRED_RSP1_HIGH =3D 0x00002c0b, + HOST_IA32_FRED_RSP2 =3D 0x00002c0c, + HOST_IA32_FRED_RSP2_HIGH =3D 0x00002c0d, + HOST_IA32_FRED_RSP3 =3D 0x00002c0e, + HOST_IA32_FRED_RSP3_HIGH =3D 0x00002c0f, + HOST_IA32_FRED_STKLVLS =3D 0x00002c10, + HOST_IA32_FRED_STKLVLS_HIGH =3D 0x00002c11, + HOST_IA32_FRED_SSP1 =3D 0x00002c12, + HOST_IA32_FRED_SSP1_HIGH =3D 0x00002c13, + HOST_IA32_FRED_SSP2 =3D 0x00002c14, + HOST_IA32_FRED_SSP2_HIGH =3D 0x00002c15, + HOST_IA32_FRED_SSP3 =3D 0x00002c16, + HOST_IA32_FRED_SSP3_HIGH =3D 0x00002c17, PIN_BASED_VM_EXEC_CONTROL =3D 0x00004000, CPU_BASED_VM_EXEC_CONTROL =3D 0x00004002, EXCEPTION_BITMAP =3D 0x00004004, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index c8b95c215869..42e179f19c23 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1460,6 +1460,15 @@ void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int c= pu) (unsigned long)(cpu_entry_stack(cpu) + 1)); } =20 + /* Per-CPU FRED MSRs */ + if (kvm_cpu_cap_has(X86_FEATURE_FRED)) { +#ifdef CONFIG_X86_64 + vmcs_write64(HOST_IA32_FRED_RSP1, __this_cpu_ist_top_va(ESTACK_DB)); + vmcs_write64(HOST_IA32_FRED_RSP2, __this_cpu_ist_top_va(ESTACK_NMI)); + vmcs_write64(HOST_IA32_FRED_RSP3, __this_cpu_ist_top_va(ESTACK_DF)); +#endif + } + vmx->loaded_vmcs->cpu =3D cpu; } } @@ -4307,6 +4316,17 @@ void vmx_set_constant_host_state(struct vcpu_vmx *vm= x) */ vmcs_write16(HOST_DS_SELECTOR, 0); vmcs_write16(HOST_ES_SELECTOR, 0); + + if (kvm_cpu_cap_has(X86_FEATURE_FRED)) { + /* FRED CONFIG and STKLVLS are the same on all CPUs */ + vmcs_write64(HOST_IA32_FRED_CONFIG, kvm_host.fred_config); + vmcs_write64(HOST_IA32_FRED_STKLVLS, kvm_host.fred_stklvls); + + /* Linux doesn't support kernel shadow stacks, thus SSPs are 0s */ + vmcs_write64(HOST_IA32_FRED_SSP1, 0); + vmcs_write64(HOST_IA32_FRED_SSP2, 0); + vmcs_write64(HOST_IA32_FRED_SSP3, 0); + } #else vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ @@ -4824,6 +4844,17 @@ static void init_vmcs(struct vcpu_vmx *vmx) } =20 vmx_setup_uret_msrs(vmx); + + if (kvm_cpu_cap_has(X86_FEATURE_FRED)) { + vmcs_write64(GUEST_IA32_FRED_CONFIG, 0); + vmcs_write64(GUEST_IA32_FRED_RSP1, 0); + vmcs_write64(GUEST_IA32_FRED_RSP2, 0); + vmcs_write64(GUEST_IA32_FRED_RSP3, 0); + vmcs_write64(GUEST_IA32_FRED_STKLVLS, 0); + vmcs_write64(GUEST_IA32_FRED_SSP1, 0); + vmcs_write64(GUEST_IA32_FRED_SSP2, 0); + vmcs_write64(GUEST_IA32_FRED_SSP3, 0); + } } =20 static void __vmx_vcpu_reset(struct kvm_vcpu *vcpu) @@ -8679,6 +8710,11 @@ __init int vmx_hardware_setup(void) =20 kvm_caps.inapplicable_quirks &=3D ~KVM_X86_QUIRK_IGNORE_GUEST_PAT; =20 + if (kvm_cpu_cap_has(X86_FEATURE_FRED)) { + rdmsrl(MSR_IA32_FRED_CONFIG, kvm_host.fred_config); + rdmsrl(MSR_IA32_FRED_STKLVLS, kvm_host.fred_stklvls); + } + return r; } =20 diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index d6b21ba41416..b6dc23c478ff 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -52,6 +52,9 @@ struct kvm_host_values { u64 xss; u64 s_cet; u64 arch_capabilities; + + u64 fred_config; + u64 fred_stklvls; }; =20 void kvm_spurious_fault(void); --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7667322DDE; Fri, 29 Aug 2025 15:33:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; cv=none; b=YNfnWmL+3sn/hTsCKtZ+vwv1NuDKxEU1yVSdj6HOe1H+4uJKnmwrY/SgJPSiojLu7VcG1R70q0Bbis+ekilov2+OGGTi3Gn9iOTDHan+6f8kFsahswMm3zw/Xr4K9apaEENUHg1jxjkEA6lv5HW90890dIHRJpJqU+8ETncDPYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; c=relaxed/simple; bh=TajmWRHRpulYaL3Ezgb6JK2nld0TR9mgSOrqKoDxdj0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Fri, 29 Aug 2025 08:32:18 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4D2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481539; bh=t+WgOmDPWX9Ho3zVppzgC3aSr34E3+f5Z93Cy1TLXmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O7uTc3QiBIFpKOEJ3KWvFdzWximz6PJASqESkiKclP7I+dn5LrTLD3tHfkDt7ex+S dTmKzOGxoP4L4OUyt6cEQuO6c66+lEnOyWB74sfpuS/r2+cOr0Htf2vXwnDrYrOESF Yvg3PaaF78Qk1646jkGrcFRfJfj6jC0QMmfKVon1PkF2xMdGm9k2SbPn7DPtExQU/A 1A+xYTfW4u8h4IKy+mG88yndan8c+DvLZWl4Dsxxnx+RDnEs6TZORrUTqBjCl5qi+8 iRYzieaBJqbTkRpRAwynHR3Yv70KsfdNCbzHSuywL9J5W5YM3cn6eKerDgkKWOUkDi lT4nODLv5LQwg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 07/21] KVM: VMX: Set FRED MSR intercepts Date: Fri, 29 Aug 2025 08:31:35 -0700 Message-ID: <20250829153149.2871901-8-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li On a userspace MSR filter change, set FRED MSR intercepts. The eight FRED MSRs, MSR_IA32_FRED_RSP[123], MSR_IA32_FRED_STKLVLS, MSR_IA32_FRED_SSP[123] and MSR_IA32_FRED_CONFIG, are all safe to passthrough, because each has a corresponding host and guest field in VMCS. Both MSR_IA32_FRED_RSP0 and MSR_IA32_FRED_SSP0 (aka MSR_IA32_PL0_SSP) are dedicated for userspace event delivery, IOW they are NOT used in any kernel event delivery and the execution of ERETS. Thus KVM can run safely with guest values in the two MSRs. As a result, save and restore of their guest values are deferred until vCPU context switch, Host MSR_IA32_FRED_RSP0 is restored upon returning to userspace, and Host MSR_IA32_PL0_SSP is managed with XRSTORS/XSAVES. Note, FRED SSP MSRs, including MSR_IA32_PL0_SSP, are available on any processor that enumerates FRED. On processors that support FRED but not CET, FRED transitions do not use these MSRs, but they remain accessible via MSR instructions such as RDMSR and WRMSR. Intercept MSR_IA32_PL0_SSP when CET shadow stack is not supported, regardless of FRED support. This ensures the guest value remains fully virtual and does not modify the hardware FRED SSP0 MSR. This behavior is consistent with the current setup in vmx_recalc_msr_intercepts(), so no change is needed to the interception logic for MSR_IA32_PL0_SSP. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Changes in v7: * Rewrite the changelog and comment, majorly for MSR_IA32_PL0_SSP. Changes in v5: * Skip execution of vmx_set_intercept_for_fred_msr() if FRED is not available or enabled (Sean). * Use 'intercept' as the variable name to indicate whether MSR interception should be enabled (Sean). * Add TB from Xuelian Guo. --- arch/x86/kvm/vmx/vmx.c | 47 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 42e179f19c23..368f1799394c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4128,6 +4128,51 @@ void pt_update_intercept_for_msr(struct kvm_vcpu *vc= pu) } } =20 +static void vmx_set_intercept_for_fred_msr(struct kvm_vcpu *vcpu) +{ + bool intercept =3D !guest_cpu_cap_has(vcpu, X86_FEATURE_FRED); + + if (!kvm_cpu_cap_has(X86_FEATURE_FRED)) + return; + + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP1, MSR_TYPE_RW, intercep= t); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP2, MSR_TYPE_RW, intercep= t); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP3, MSR_TYPE_RW, intercep= t); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_STKLVLS, MSR_TYPE_RW, inter= cept); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP1, MSR_TYPE_RW, intercep= t); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP2, MSR_TYPE_RW, intercep= t); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP3, MSR_TYPE_RW, intercep= t); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_CONFIG, MSR_TYPE_RW, interc= ept); + + /* + * MSR_IA32_FRED_RSP0 and MSR_IA32_PL0_SSP (aka MSR_IA32_FRED_SSP0) are + * designed for event delivery while executing in userspace. Since KVM + * operates entirely in kernel mode (CPL is always 0 after any VM exit), + * it can safely retain and operate with guest-defined values for these + * MSRs. + * + * As a result, interception of MSR_IA32_FRED_RSP0 and MSR_IA32_PL0_SSP + * is unnecessary. + * + * Note: Saving and restoring MSR_IA32_PL0_SSP is part of CET supervisor + * context management. However, FRED SSP MSRs, including MSR_IA32_PL0_SS= P, + * are available on any processor that enumerates FRED. + * + * On processors that support FRED but not CET, FRED transitions do not + * use these MSRs, but they remain accessible via MSR instructions such + * as RDMSR and WRMSR. + * + * Intercept MSR_IA32_PL0_SSP when CET shadow stack is not supported, + * regardless of FRED support. This ensures the guest value remains + * fully virtual and does not modify the hardware FRED SSP0 MSR. + * + * This behavior is consistent with the current setup in + * vmx_recalc_msr_intercepts(), so no change is needed to the interception + * logic for MSR_IA32_PL0_SSP. + */ + vmx_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP0, MSR_TYPE_RW, intercep= t); +} + void vmx_recalc_msr_intercepts(struct kvm_vcpu *vcpu) { bool intercept; @@ -4194,6 +4239,8 @@ void vmx_recalc_msr_intercepts(struct kvm_vcpu *vcpu) vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, intercept); } =20 + vmx_set_intercept_for_fred_msr(vcpu); + /* * x2APIC and LBR MSR intercepts are modified on-demand and cannot be * filtered by userspace. --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F10D0321F26; Fri, 29 Aug 2025 15:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; cv=none; b=TkRgHu5VeOOcQ6WkisLolGsw7k/dq0PMGIo5RpnoJbzRJgyJl9LPfVLXmC8NktVDWmrBakhjZibvSyw4I/ADlXECTObhTs1yIOsgebZTkk0OBpsPI+6Z0ij0G8AkptL5mCY0Xby0t03A9jUqvnXPvrhazE3q33kw9WWD5KqJktA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; c=relaxed/simple; bh=B+m/8qllmHVTlj/AM37AJiiUWBYT48rw46oDultWBPo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nx7a0rxda9VUWI2HHi48tQpeBf/eZS1utkYGyvhmz/WPfU/994i6PVe54qTPl6qYzRk3qinlaxZ0J9xDfEsKE9bDPV430wzHI0qleJZCKXsq1g1MipxxL9FUmF9dUhoG+IcjLTneL8bF7e2Uk0vN5GIDsJC4+UK93vmWWAZ7y/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=bWcGNT/Z; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="bWcGNT/Z" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4E2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:19 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4E2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481540; bh=bvBHvjul1GobdicSx2txFw5fgQ8wUMiarsYtlt6XWY4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bWcGNT/ZCkVvaDiyN0n7t4aRTwIleF7m6yMZ52/htAc/ffzypnMVINfmqiyYHTbxP Pa/GxNTnt3HYNsy5ujNp5op9TqQLd+UJNa671y9ZvOEuXH+lMZO5ld8XpKz3DENu+i lUkMpBwh2hq/iOvW+9/KK4+Sxan4yPyz1atRerF8EE1MeYA3FGn4UQr3+RsI42Gztz qiyMRVuiCtGAIJ0GxTwyK/e5MFLVg4FLBGmaKZbVk9Bg8jfjm9ddBOCfTcRgbmGNbp B2Q7Bgjonr1WaNhXtZa+0X9GPFav4/94Ud5/AiEBYVzA8BsF5//TVAYFzlZ5pygcYf 9OlMRbPmrf4Eg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 08/21] KVM: VMX: Save/restore guest FRED RSP0 Date: Fri, 29 Aug 2025 08:31:36 -0700 Message-ID: <20250829153149.2871901-9-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Save guest FRED RSP0 in vmx_prepare_switch_to_host() and restore it in vmx_prepare_switch_to_guest() because MSR_IA32_FRED_RSP0 is passed through to the guest, thus is volatile/unknown. Note, host FRED RSP0 is restored in arch_exit_to_user_mode_prepare(), regardless of whether it is modified in KVM. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Changes in v5: * Remove the cpu_feature_enabled() check when set/get guest MSR_IA32_FRED_RSP0, as guest_cpu_cap_has() should suffice (Sean). * Add a comment when synchronizing current MSR_IA32_FRED_RSP0 MSR to the kernel's local cache, because its handling is different from the MSR_KERNEL_GS_BASE handling (Sean). * Add TB from Xuelian Guo. Changes in v3: * KVM only needs to save/restore guest FRED RSP0 now as host FRED RSP0 is restored in arch_exit_to_user_mode_prepare() (Sean Christopherson). Changes in v2: * Don't use guest_cpuid_has() in vmx_prepare_switch_to_{host,guest}(), which are called from IRQ-disabled context (Chao Gao). * Reset msr_guest_fred_rsp0 in __vmx_vcpu_reset() (Chao Gao). --- arch/x86/kvm/vmx/vmx.c | 13 +++++++++++++ arch/x86/kvm/vmx/vmx.h | 1 + 2 files changed, 14 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 368f1799394c..5f639fb3b44d 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1293,6 +1293,9 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcp= u) } =20 wrmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); + + if (guest_cpu_cap_has(vcpu, X86_FEATURE_FRED)) + wrmsrns(MSR_IA32_FRED_RSP0, vmx->msr_guest_fred_rsp0); #else savesegment(fs, fs_sel); savesegment(gs, gs_sel); @@ -1337,6 +1340,16 @@ static void vmx_prepare_switch_to_host(struct vcpu_v= mx *vmx) invalidate_tss_limit(); #ifdef CONFIG_X86_64 wrmsrq(MSR_KERNEL_GS_BASE, vmx->vt.msr_host_kernel_gs_base); + + if (guest_cpu_cap_has(&vmx->vcpu, X86_FEATURE_FRED)) { + vmx->msr_guest_fred_rsp0 =3D read_msr(MSR_IA32_FRED_RSP0); + /* + * Synchronize the current value in hardware to the kernel's + * local cache. The desired host RSP0 will be set when the + * CPU exits to userspace (RSP0 is a per-task value). + */ + fred_sync_rsp0(vmx->msr_guest_fred_rsp0); + } #endif load_fixmap_gdt(raw_smp_processor_id()); vmx->vt.guest_state_loaded =3D false; diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index e577af1003d8..733fa2ef4bea 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -227,6 +227,7 @@ struct vcpu_vmx { bool guest_uret_msrs_loaded; #ifdef CONFIG_X86_64 u64 msr_guest_kernel_gs_base; + u64 msr_guest_fred_rsp0; #endif =20 u64 spec_ctrl; --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D8C62222B6; Fri, 29 Aug 2025 15:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481591; cv=none; b=us9k2y2Ma9aGCeWTn4FObgKs6Z8sbBG56q1quIOtsTTqsXvvo2RfhZivresfuFZufA3O8cd3O+4GEH+qr0IRCyvMjH6JeVUTzGTkWWck5OLbSfpoNgUMHa5n+KLQGCudAG5J8zeY3mG03SpQYvYf6EL9kmnXQU+XGF2KobG73qY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481591; c=relaxed/simple; bh=IZAcf1aegp8pBPTiC7aXNvJ/BlAxYHGr/n/69Rd7MOM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V04rsKy+JYUl/Fi5wVFKSOtyy32/D/WPbhROE8MM2MTx5xA1quAJ8i3YwjKBWK/JLURrJu8LTZDHiUPd0x6kyhpnYuGyqKNmUEEzbief6urZ6GE3cFvoBWcjzyopLnPyMt+m3htOOw4gd6dc2mr6UC6cs4XBRkDhHXasHlowymk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=iCEMVUl1; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="iCEMVUl1" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4F2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:20 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4F2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481541; bh=kMHxdPrkyi+mof/Hq/9CeRaL5H712EGkw71jXlrR6gE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iCEMVUl1TOAq+0goTRaxXw2JO73B/zQGROzwnk0h+Pa/I0f1v0vz89g3PXu16T+lt 6dIC50NCZzpVZtDlK+JMaA9RYMaPGXABNicmvdzobpDTE2zyy1eBZRPQK/gGCN1N/X /qo6Y1bFhxUs++9UntgxlGf3zOdPw4HYq3IL63wDpnyAS7vMIxpRlI06r9zVa2b1jm ZhqIB5SsTXEaDSboZkMewO0NAqBMk6F6RyK17JJx1UegdT+2y/tdWDfNu+wWSmeqjM Gjtes7yaYc/1Z9gmsZvnkLjlni2ylFmb5FWgH4RSMiEMieXHcTurXgbftk6VM+hQNh BBLX/zpNzRPAA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 09/21] KVM: VMX: Add support for saving and restoring FRED MSRs Date: Fri, 29 Aug 2025 08:31:37 -0700 Message-ID: <20250829153149.2871901-10-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Introduce support for handling FRED MSR access requests, enabling both host and guest to read and write FRED MSRs, which is essential for VM save/restore and live migration, and allows userspace tools such as QEMU to access the relevant MSRs. Specially, intercept accesses to the FRED SSP0 MSR (IA32_PL0_SSP), which remains accessible when FRED is enumerated even if CET is not. This ensures the guest value is fully virtual and does not alter the hardware FRED SSP0 MSR. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v7: * Intercept accesses to FRED SSP0, i.e., IA32_PL0_SSP, which remains accessible when FRED but !CET (Sean). Change in v6: * Return KVM_MSR_RET_UNSUPPORTED instead of 1 when FRED is not available (Chao Gao) * Handle MSR_IA32_PL0_SSP when FRED is enumerated but CET not. Change in v5: * Use the newly added guest MSR read/write helpers (Sean). * Check the size of fred_msr_vmcs_fields[] using static_assert() (Sean). * Rewrite setting FRED MSRs to make it much easier to read (Sean). * Add TB from Xuelian Guo. Changes since v2: * Add a helper to convert FRED MSR index to VMCS field encoding to make the code more compact (Chao Gao). * Get rid of the "host_initiated" check because userspace has to set CPUID before MSRs (Chao Gao & Sean Christopherson). * Address a few cleanup comments (Sean Christopherson). Changes since v1: * Use kvm_cpu_cap_has() instead of cpu_feature_enabled() (Chao Gao). * Fail host requested FRED MSRs access if KVM cannot virtualize FRED (Chao Gao). * Handle the case FRED MSRs are valid but KVM cannot virtualize FRED (Chao Gao). * Add sanity checks when writing to FRED MSRs. --- arch/x86/include/asm/kvm_host.h | 5 ++ arch/x86/kvm/vmx/vmx.c | 45 ++++++++++++++ arch/x86/kvm/x86.c | 102 ++++++++++++++++++++++++++++++-- 3 files changed, 148 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 061c0cd73d39..bec644eec92f 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1091,6 +1091,11 @@ struct kvm_vcpu_arch { #if IS_ENABLED(CONFIG_HYPERV) hpa_t hv_root_tdp; #endif + /* + * Stores the FRED SSP0 MSR when CET is not supported, prompting KVM + * to intercept its accesses. + */ + u64 fred_ssp0_fallback; }; =20 struct kvm_lpage_info { diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 5f639fb3b44d..358410220cc2 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1387,6 +1387,18 @@ static void vmx_write_guest_kernel_gs_base(struct vc= pu_vmx *vmx, u64 data) vmx_write_guest_host_msr(vmx, MSR_KERNEL_GS_BASE, data, &vmx->msr_guest_kernel_gs_base); } + +static u64 vmx_read_guest_fred_rsp0(struct vcpu_vmx *vmx) +{ + return vmx_read_guest_host_msr(vmx, MSR_IA32_FRED_RSP0, + &vmx->msr_guest_fred_rsp0); +} + +static void vmx_write_guest_fred_rsp0(struct vcpu_vmx *vmx, u64 data) +{ + vmx_write_guest_host_msr(vmx, MSR_IA32_FRED_RSP0, data, + &vmx->msr_guest_fred_rsp0); +} #endif =20 static void grow_ple_window(struct kvm_vcpu *vcpu) @@ -1988,6 +2000,27 @@ int vmx_get_feature_msr(u32 msr, u64 *data) } } =20 +#ifdef CONFIG_X86_64 +static const u32 fred_msr_vmcs_fields[] =3D { + GUEST_IA32_FRED_RSP1, + GUEST_IA32_FRED_RSP2, + GUEST_IA32_FRED_RSP3, + GUEST_IA32_FRED_STKLVLS, + GUEST_IA32_FRED_SSP1, + GUEST_IA32_FRED_SSP2, + GUEST_IA32_FRED_SSP3, + GUEST_IA32_FRED_CONFIG, +}; + +static_assert(MSR_IA32_FRED_CONFIG - MSR_IA32_FRED_RSP1 =3D=3D + ARRAY_SIZE(fred_msr_vmcs_fields) - 1); + +static u32 fred_msr_to_vmcs(u32 msr) +{ + return fred_msr_vmcs_fields[msr - MSR_IA32_FRED_RSP1]; +} +#endif + /* * Reads an msr value (of 'msr_info->index') into 'msr_info->data'. * Returns 0 on success, non-0 otherwise. @@ -2010,6 +2043,12 @@ int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_da= ta *msr_info) case MSR_KERNEL_GS_BASE: msr_info->data =3D vmx_read_guest_kernel_gs_base(vmx); break; + case MSR_IA32_FRED_RSP0: + msr_info->data =3D vmx_read_guest_fred_rsp0(vmx); + break; + case MSR_IA32_FRED_RSP1 ... MSR_IA32_FRED_CONFIG: + msr_info->data =3D vmcs_read64(fred_msr_to_vmcs(msr_info->index)); + break; #endif case MSR_EFER: return kvm_get_msr_common(vcpu, msr_info); @@ -2242,6 +2281,12 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_da= ta *msr_info) vmx_update_exception_bitmap(vcpu); } break; + case MSR_IA32_FRED_RSP0: + vmx_write_guest_fred_rsp0(vmx, data); + break; + case MSR_IA32_FRED_RSP1 ... MSR_IA32_FRED_CONFIG: + vmcs_write64(fred_msr_to_vmcs(msr_index), data); + break; #endif case MSR_IA32_SYSENTER_CS: if (is_guest_mode(vcpu)) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9930678f5a3b..c53fc235b8bd 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -329,6 +329,9 @@ static const u32 msrs_to_save_base[] =3D { MSR_STAR, #ifdef CONFIG_X86_64 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, + MSR_IA32_FRED_RSP0, MSR_IA32_FRED_RSP1, MSR_IA32_FRED_RSP2, + MSR_IA32_FRED_RSP3, MSR_IA32_FRED_STKLVLS, MSR_IA32_FRED_SSP1, + MSR_IA32_FRED_SSP2, MSR_IA32_FRED_SSP3, MSR_IA32_FRED_CONFIG, #endif MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, @@ -1910,7 +1913,7 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 i= ndex, u64 data, * architecture. Intercepting XRSTORS/XSAVES for this * special case isn't deemed worthwhile. */ - case MSR_IA32_PL0_SSP ... MSR_IA32_INT_SSP_TAB: + case MSR_IA32_PL1_SSP ... MSR_IA32_INT_SSP_TAB: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK)) return KVM_MSR_RET_UNSUPPORTED; /* @@ -1925,6 +1928,52 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 = index, u64 data, if (index !=3D MSR_IA32_INT_SSP_TAB && !IS_ALIGNED(data, 4)) return 1; break; + case MSR_IA32_FRED_STKLVLS: + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_FRED)) + return KVM_MSR_RET_UNSUPPORTED; + break; + case MSR_IA32_FRED_RSP0 ... MSR_IA32_FRED_RSP3: + case MSR_IA32_FRED_SSP1 ... MSR_IA32_FRED_CONFIG: { + u64 reserved_bits =3D 0; + + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_FRED)) + return KVM_MSR_RET_UNSUPPORTED; + + if (is_noncanonical_msr_address(data, vcpu)) + return 1; + + switch (index) { + case MSR_IA32_FRED_CONFIG: + reserved_bits =3D BIT_ULL(11) | GENMASK_ULL(5, 4) | BIT_ULL(2); + break; + case MSR_IA32_FRED_RSP0 ... MSR_IA32_FRED_RSP3: + reserved_bits =3D GENMASK_ULL(5, 0); + break; + case MSR_IA32_FRED_SSP1 ... MSR_IA32_FRED_SSP3: + reserved_bits =3D GENMASK_ULL(2, 0); + break; + default: + WARN_ON_ONCE(1); + return 1; + } + + if (data & reserved_bits) + return 1; + + break; + } + case MSR_IA32_PL0_SSP: /* I.e., MSR_IA32_FRED_SSP0 */ + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK) && + !guest_cpu_cap_has(vcpu, X86_FEATURE_FRED)) + return KVM_MSR_RET_UNSUPPORTED; + + if (is_noncanonical_msr_address(data, vcpu)) + return 1; + + if (!IS_ALIGNED(data, 4)) + return 1; + + break; } =20 msr.data =3D data; @@ -1979,10 +2028,19 @@ static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32= index, u64 *data, if (!host_initiated) return 1; fallthrough; - case MSR_IA32_PL0_SSP ... MSR_IA32_INT_SSP_TAB: + case MSR_IA32_PL1_SSP ... MSR_IA32_INT_SSP_TAB: if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK)) return KVM_MSR_RET_UNSUPPORTED; break; + case MSR_IA32_FRED_RSP0 ... MSR_IA32_FRED_CONFIG: + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_FRED)) + return KVM_MSR_RET_UNSUPPORTED; + break; + case MSR_IA32_PL0_SSP: /* I.e., MSR_IA32_FRED_SSP0 */ + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK) && + !guest_cpu_cap_has(vcpu, X86_FEATURE_FRED)) + return KVM_MSR_RET_UNSUPPORTED; + break; } =20 msr.index =3D index; @@ -4275,6 +4333,12 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct= msr_data *msr_info) #endif case MSR_IA32_U_CET: case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP: + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK)) { + WARN_ON_ONCE(msr !=3D MSR_IA32_FRED_SSP0); + vcpu->arch.fred_ssp0_fallback =3D data; + break; + } + kvm_set_xstate_msr(vcpu, msr_info); break; default: @@ -4628,6 +4692,12 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct= msr_data *msr_info) #endif case MSR_IA32_U_CET: case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP: + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK)) { + WARN_ON_ONCE(msr_info->index !=3D MSR_IA32_FRED_SSP0); + msr_info->data =3D vcpu->arch.fred_ssp0_fallback; + break; + } + kvm_get_xstate_msr(vcpu, msr_info); break; default: @@ -4648,8 +4718,23 @@ static bool is_xstate_managed_msr(u32 index) { switch (index) { case MSR_IA32_U_CET: - case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP: + case MSR_IA32_PL1_SSP ... MSR_IA32_PL3_SSP: return true; + case MSR_IA32_PL0_SSP: + /* + * When CET is not supported, XRSTORS/XSAVES do not cover + * MSR_IA32_PL0_SSP. However, this MSR remains accessible + * to a FRED guest. + * + * Return false to skip loading the guest FPU in __msr_io() + * whenever CET is unsupported, regardless of FRED support. + * + * Note: if !guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK) but + * kvm_cpu_cap_has(X86_FEATURE_SHSTK), this function returns + * true and XSAVES/XRSTORS save and restore MSR_IA32_PL0_SSP, + * even such a guest doesn't affect the hardware PL0 SSP MSR. + */ + return kvm_caps.supported_xss & XFEATURE_MASK_CET_KERNEL; default: return false; } @@ -7603,10 +7688,19 @@ static void kvm_probe_msr_to_save(u32 msr_index) if (!kvm_cpu_cap_has(X86_FEATURE_LM)) return; fallthrough; - case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP: + case MSR_IA32_PL1_SSP ... MSR_IA32_PL3_SSP: if (!kvm_cpu_cap_has(X86_FEATURE_SHSTK)) return; break; + case MSR_IA32_FRED_RSP0 ... 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charset="utf-8" From: Xin Li Signed-off-by: Xin Li [ Sean: removed the "kvm_" prefix from the function name ] Signed-off-by: Sean Christopherson Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. --- arch/x86/kvm/kvm_cache_regs.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 36a8786db291..31b446b6cbd7 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -204,6 +204,21 @@ static __always_inline bool kvm_is_cr4_bit_set(struct = kvm_vcpu *vcpu, return !!kvm_read_cr4_bits(vcpu, cr4_bit); } =20 +/* + * It's enough to check just CR4.FRED (X86_CR4_FRED) to tell if + * a vCPU is running with FRED enabled, because: + * 1) CR4.FRED can be set to 1 only _after_ IA32_EFER.LMA =3D 1. + * 2) To leave IA-32e mode, CR4.FRED must be cleared first. + */ +static inline bool is_fred_enabled(struct kvm_vcpu *vcpu) +{ +#ifdef CONFIG_X86_64 + return kvm_is_cr4_bit_set(vcpu, X86_CR4_FRED); +#else + return false; +#endif +} + static inline ulong kvm_read_cr3(struct kvm_vcpu *vcpu) { if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 000ED322766; Fri, 29 Aug 2025 15:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; cv=none; b=ZpHutz+xdPHnGwdxK5UQHlvVmXC+8O+FbZIvtf7Hj76nvczx3qFduhJuS1TKuTXtZBdErP1JoCZ95f1Oh3Q9o2pD+LSCFIatYuHIDxTojHOluRr2hyRAhMCrPOnV6uBp5MMlK+QojwM5l00v3s2VrQrC/Yf7KO0XkPlBTywKU2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; c=relaxed/simple; bh=TLgbBxiKolxuXOrjRLi0rkoZU9vP1gi3n6LpK9m1o/g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Fri, 29 Aug 2025 08:32:22 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4H2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481542; bh=BBKTXTsrn2Zw8Dcn2Z3/WpVvozoH+mmJCd/M7GhuKco=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JynVGdVWwpU+LxqO1Q6rtxg8YUh1ZNf1mJUMEYAZLP31wfjEe93yKXR5PGfVMyUim rXYqdJLMYinVyhHh8xDiDb9bLFppZgsnRCjw1HE4+q8PkCtYIGGvtpa+3NjULgOuUJ MdRfsulqOELpM8gHe9cMksAWiFijHFRo21GATyI4m3u0kbTUm4wio70TvOU+VA/YEa la5RU89IijuloZQPA4zoKBAjX9Hh1p1elNRSiqeV+jS8lJySJOPS9w4P9XiHaO0qhe mzpg8Hvyo9nz3Vly0vXzf+nrJPQ9GILmbE5UbraQyWDmQ/hzdng26eCOg6pvnmrj75 v9h4oNBUeZnfw== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 11/21] KVM: VMX: Virtualize FRED event_data Date: Fri, 29 Aug 2025 08:31:39 -0700 Message-ID: <20250829153149.2871901-12-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Set injected-event data when injecting a #PF, #DB, or #NM caused by extended feature disable using FRED event delivery, and save original-event data for being used as injected-event data. Unlike IDT using some extra CPU register as part of an event context, e.g., %cr2 for #PF, FRED saves a complete event context in its stack frame, e.g., FRED saves the faulting linear address of a #PF into the event data field defined in its stack frame. Thus a new VMX control field called injected-event data is added to provide the event data that will be pushed into a FRED stack frame for VM entries that inject an event using FRED event delivery. In addition, a new VM exit information field called original-event data is added to store the event data that would have saved into a FRED stack frame for VM exits that occur during FRED event delivery. After such a VM exit is handled to allow the original-event to be delivered, the data in the original-event data VMCS field needs to be set into the injected-event data VMCS field for the injection of the original event. Signed-off-by: Xin Li [ Sean: reworked event data injection for nested ] Signed-off-by: Sean Christopherson Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. Change in v3: * Rework event data injection for nested (Chao Gao & Sean Christopherson). Changes in v2: * Document event data should be equal to CR2/DR6/IA32_XFD_ERR instead of using WARN_ON() (Chao Gao). * Zero event data if a #NM was not caused by extended feature disable (Chao Gao). --- arch/x86/include/asm/kvm_host.h | 3 ++- arch/x86/include/asm/vmx.h | 4 ++++ arch/x86/kvm/svm/svm.c | 2 +- arch/x86/kvm/vmx/vmx.c | 22 ++++++++++++++++++---- arch/x86/kvm/x86.c | 16 +++++++++++++++- 5 files changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index bec644eec92f..5c48acc98939 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -759,6 +759,7 @@ struct kvm_queued_exception { u32 error_code; unsigned long payload; bool has_payload; + u64 event_data; }; =20 /* @@ -2227,7 +2228,7 @@ void kvm_queue_exception(struct kvm_vcpu *vcpu, unsig= ned nr); void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_c= ode); void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned lo= ng payload); void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned int nr, - bool has_error_code, u32 error_code); + bool has_error_code, u32 error_code, u64 event_data); void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fa= ult); void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 6f8b8947c60c..539af190ad3e 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -269,8 +269,12 @@ enum vmcs_field { PID_POINTER_TABLE_HIGH =3D 0x00002043, SECONDARY_VM_EXIT_CONTROLS =3D 0x00002044, SECONDARY_VM_EXIT_CONTROLS_HIGH =3D 0x00002045, + INJECTED_EVENT_DATA =3D 0x00002052, + INJECTED_EVENT_DATA_HIGH =3D 0x00002053, GUEST_PHYSICAL_ADDRESS =3D 0x00002400, GUEST_PHYSICAL_ADDRESS_HIGH =3D 0x00002401, + ORIGINAL_EVENT_DATA =3D 0x00002404, + ORIGINAL_EVENT_DATA_HIGH =3D 0x00002405, VMCS_LINK_POINTER =3D 0x00002800, VMCS_LINK_POINTER_HIGH =3D 0x00002801, GUEST_IA32_DEBUGCTL =3D 0x00002802, diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e4af4907c7d8..9feca6b90380 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4127,7 +4127,7 @@ static void svm_complete_interrupts(struct kvm_vcpu *= vcpu) =20 kvm_requeue_exception(vcpu, vector, exitintinfo & SVM_EXITINTINFO_VALID_ERR, - error_code); + error_code, 0); break; } case SVM_EXITINTINFO_TYPE_INTR: diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 358410220cc2..1abfba2139a5 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1861,6 +1861,9 @@ void vmx_inject_exception(struct kvm_vcpu *vcpu) =20 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); =20 + if (is_fred_enabled(vcpu)) + vmcs_write64(INJECTED_EVENT_DATA, ex->event_data); + vmx_clear_hlt(vcpu); } =20 @@ -7269,7 +7272,8 @@ static void vmx_recover_nmi_blocking(struct vcpu_vmx = *vmx) static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, u32 idt_vectoring_info, int instr_len_field, - int error_code_field) + int error_code_field, + int event_data_field) { u8 vector; int type; @@ -7304,13 +7308,17 @@ static void __vmx_complete_interrupts(struct kvm_vc= pu *vcpu, fallthrough; case INTR_TYPE_HARD_EXCEPTION: { u32 error_code =3D 0; + u64 event_data =3D 0; =20 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) error_code =3D vmcs_read32(error_code_field); + if (is_fred_enabled(vcpu)) + event_data =3D vmcs_read64(event_data_field); =20 kvm_requeue_exception(vcpu, vector, idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK, - error_code); + error_code, + event_data); break; } case INTR_TYPE_SOFT_INTR: @@ -7328,7 +7336,8 @@ static void vmx_complete_interrupts(struct vcpu_vmx *= vmx) { __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, VM_EXIT_INSTRUCTION_LEN, - IDT_VECTORING_ERROR_CODE); + IDT_VECTORING_ERROR_CODE, + ORIGINAL_EVENT_DATA); } =20 void vmx_cancel_injection(struct kvm_vcpu *vcpu) @@ -7336,7 +7345,8 @@ void vmx_cancel_injection(struct kvm_vcpu *vcpu) __vmx_complete_interrupts(vcpu, vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), VM_ENTRY_INSTRUCTION_LEN, - VM_ENTRY_EXCEPTION_ERROR_CODE); + VM_ENTRY_EXCEPTION_ERROR_CODE, + INJECTED_EVENT_DATA); =20 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); } @@ -7490,6 +7500,10 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_v= cpu *vcpu, =20 vmx_disable_fb_clear(vmx); =20 + /* + * Note, even though FRED delivers the faulting linear address via the + * event data field on the stack, CR2 is still updated. + */ if (vcpu->arch.cr2 !=3D native_read_cr2()) native_write_cr2(vcpu->arch.cr2); =20 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c53fc235b8bd..dbcf00c55012 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -807,9 +807,22 @@ void kvm_deliver_exception_payload(struct kvm_vcpu *vc= pu, * breakpoint), it is reserved and must be zero in DR6. */ vcpu->arch.dr6 &=3D ~BIT(12); + + /* + * FRED #DB event data matches DR6, but follows the polarity of + * VMX's pending debug exceptions, not DR6. + */ + ex->event_data =3D ex->payload & ~BIT(12); + break; + case NM_VECTOR: + ex->event_data =3D ex->payload; break; case PF_VECTOR: vcpu->arch.cr2 =3D ex->payload; + ex->event_data =3D ex->payload; + break; + default: + ex->event_data =3D 0; break; } =20 @@ -917,7 +930,7 @@ static void kvm_queue_exception_e_p(struct kvm_vcpu *vc= pu, unsigned nr, } =20 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned int nr, - bool has_error_code, u32 error_code) + bool has_error_code, u32 error_code, u64 event_data) { =20 /* @@ -942,6 +955,7 @@ void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsig= ned int nr, vcpu->arch.exception.error_code =3D error_code; vcpu->arch.exception.has_payload =3D false; vcpu->arch.exception.payload =3D 0; + vcpu->arch.exception.event_data =3D event_data; } EXPORT_SYMBOL_GPL(kvm_requeue_exception); =20 --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DE70314B82; Fri, 29 Aug 2025 15:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; cv=none; b=YB7XkrIymDl+ennhzUZYhCT/i4zp2/BmBODhePYduktqfewm0j37xZwf6ZQifcJxvWjc9E/YWauWr0lrd9ZDC5C5mMrKCaHitN+4FQakSxLoRijOMifFSeDxVrNL0pzJ6rSEw5TSCJTlicoFfXquCU03tKa9xbHU8Kw3zr0yOb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; c=relaxed/simple; bh=hKIBVl3UsTHWBwPBbxISchvDVw51wNLqpk5vwLBJI/4=; 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Fri, 29 Aug 2025 08:32:23 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4I2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481543; bh=dLc18oJcaFgQ7It5XQKc+8vj0uGdMz5U25Cz2rPw3zE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eHdt0HizRWsXjXz6Z89KyOucuw+Ud15wOK0+hkRLmutMOl/9xSnnV5/TUIs0w9rqj eBtZNlDGY733ttYzjM73VELDeOCQkg2G+KMcxz4txC8QKZ53eP8BhiCdKb5vZTcc6H QIicjDq00C/BFayhWM2HT8k2dk3lo3xHzbnQpyQJODXR2G812BfbZ+j+ltaCdLq6wE 0k5F14bGyEFupzXZKvIVmG1ezJpPRNvipXii+Ew5EjXorkO+v0dOeo72suBxz+JvB9 GGI6AkEUb2TLXLHZbfYrkdw87msIYbpc+T90+LEzMmkcOgm/1ICmuS2kKp1l6If/Fn ZCo/pOGy9NLdA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 12/21] KVM: VMX: Virtualize FRED nested exception tracking Date: Fri, 29 Aug 2025 08:31:40 -0700 Message-ID: <20250829153149.2871901-13-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Set the VMX nested exception bit in VM-entry interruption information field when injecting a nested exception using FRED event delivery to ensure: 1) A nested exception is injected on a correct stack level. 2) The nested bit defined in FRED stack frame is set. The event stack level used by FRED event delivery depends on whether the event was a nested exception encountered during delivery of an earlier event, because a nested exception is "regarded" as happening on ring 0. E.g., when #PF is configured to use stack level 1 in IA32_FRED_STKLVLS MSR: - nested #PF will be delivered on the stack pointed by IA32_FRED_RSP1 MSR when encountered in ring 3 and ring 0. - normal #PF will be delivered on the stack pointed by IA32_FRED_RSP0 MSR when encountered in ring 3. The VMX nested-exception support ensures a correct event stack level is chosen when a VM entry injects a nested exception. Signed-off-by: Xin Li [ Sean: reworked kvm_requeue_exception() to simply the code changes ] Signed-off-by: Sean Christopherson Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. Change in v4: * Move the check is_fred_enable() from kvm_multiple_exception() to vmx_inject_exception() thus avoid bleeding FRED details into kvm_multiple_exception() (Chao Gao). Change in v3: * Rework kvm_requeue_exception() to simply the code changes (Sean Christopherson). Change in v2: * Set the nested flag when there is an original interrupt (Chao Gao). --- arch/x86/include/asm/kvm_host.h | 4 +++- arch/x86/include/asm/vmx.h | 5 ++++- arch/x86/kvm/svm/svm.c | 2 +- arch/x86/kvm/vmx/vmx.c | 6 +++++- arch/x86/kvm/x86.c | 13 ++++++++++++- arch/x86/kvm/x86.h | 1 + 6 files changed, 26 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 5c48acc98939..b5a1fef8d637 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -759,6 +759,7 @@ struct kvm_queued_exception { u32 error_code; unsigned long payload; bool has_payload; + bool nested; u64 event_data; }; =20 @@ -2228,7 +2229,8 @@ void kvm_queue_exception(struct kvm_vcpu *vcpu, unsig= ned nr); void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_c= ode); void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned lo= ng payload); void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned int nr, - bool has_error_code, u32 error_code, u64 event_data); + bool has_error_code, u32 error_code, bool nested, + u64 event_data); void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fa= ult); void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 539af190ad3e..7b34a9357b28 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -140,6 +140,7 @@ #define VMX_BASIC_INOUT BIT_ULL(54) #define VMX_BASIC_TRUE_CTLS BIT_ULL(55) #define VMX_BASIC_NO_HW_ERROR_CODE_CC BIT_ULL(56) +#define VMX_BASIC_NESTED_EXCEPTION BIT_ULL(58) =20 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic) { @@ -442,13 +443,15 @@ enum vmcs_field { #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ +#define INTR_INFO_NESTED_EXCEPTION_MASK 0x2000 /* 13 */ #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ -#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 +#define INTR_INFO_RESVD_BITS_MASK 0x7fffd000 =20 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK +#define VECTORING_INFO_NESTED_EXCEPTION_MASK INTR_INFO_NESTED_EXCEPTION_MA= SK =20 #define INTR_TYPE_EXT_INTR (EVENT_TYPE_EXTINT << 8) /* external interrupt= */ #define INTR_TYPE_RESERVED (EVENT_TYPE_RESERVED << 8) /* reserved */ diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9feca6b90380..c4402e50c828 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4127,7 +4127,7 @@ static void svm_complete_interrupts(struct kvm_vcpu *= vcpu) =20 kvm_requeue_exception(vcpu, vector, exitintinfo & SVM_EXITINTINFO_VALID_ERR, - error_code, 0); + error_code, false, 0); break; } case SVM_EXITINTINFO_TYPE_INTR: diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 1abfba2139a5..3d968584d854 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1856,8 +1856,11 @@ void vmx_inject_exception(struct kvm_vcpu *vcpu) vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, vmx->vcpu.arch.event_exit_inst_len); intr_info |=3D INTR_TYPE_SOFT_EXCEPTION; - } else + } else { intr_info |=3D INTR_TYPE_HARD_EXCEPTION; + if (ex->nested && is_fred_enabled(vcpu)) + intr_info |=3D INTR_INFO_NESTED_EXCEPTION_MASK; + } =20 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); =20 @@ -7318,6 +7321,7 @@ static void __vmx_complete_interrupts(struct kvm_vcpu= *vcpu, kvm_requeue_exception(vcpu, vector, idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK, error_code, + idt_vectoring_info & VECTORING_INFO_NESTED_EXCEPTION_MASK, event_data); break; } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index dbcf00c55012..7598b8d72b07 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -871,6 +871,10 @@ static void kvm_multiple_exception(struct kvm_vcpu *vc= pu, unsigned int nr, vcpu->arch.exception.pending =3D true; vcpu->arch.exception.injected =3D false; =20 + vcpu->arch.exception.nested =3D vcpu->arch.exception.nested || + vcpu->arch.nmi_injected || + vcpu->arch.interrupt.injected; + vcpu->arch.exception.has_error_code =3D has_error; vcpu->arch.exception.vector =3D nr; vcpu->arch.exception.error_code =3D error_code; @@ -900,8 +904,13 @@ static void kvm_multiple_exception(struct kvm_vcpu *vc= pu, unsigned int nr, vcpu->arch.exception.injected =3D false; vcpu->arch.exception.pending =3D false; =20 + /* #DF is NOT a nested event, per its definition. */ + vcpu->arch.exception.nested =3D false; + kvm_queue_exception_e(vcpu, DF_VECTOR, 0); } else { + vcpu->arch.exception.nested =3D true; + /* replace previous exception with a new one in a hope that instruction re-execution will regenerate lost exception */ @@ -930,7 +939,8 @@ static void kvm_queue_exception_e_p(struct kvm_vcpu *vc= pu, unsigned nr, } =20 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned int nr, - bool has_error_code, u32 error_code, u64 event_data) + bool has_error_code, u32 error_code, bool nested, + u64 event_data) { =20 /* @@ -955,6 +965,7 @@ void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsig= ned int nr, vcpu->arch.exception.error_code =3D error_code; vcpu->arch.exception.has_payload =3D false; vcpu->arch.exception.payload =3D 0; + vcpu->arch.exception.nested =3D nested; vcpu->arch.exception.event_data =3D event_data; } EXPORT_SYMBOL_GPL(kvm_requeue_exception); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index b6dc23c478ff..685eb710b1f2 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -198,6 +198,7 @@ static inline void kvm_clear_exception_queue(struct kvm= _vcpu *vcpu) { vcpu->arch.exception.pending =3D false; vcpu->arch.exception.injected =3D false; + vcpu->arch.exception.nested =3D false; vcpu->arch.exception_vmexit.pending =3D false; } =20 --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D5031E51EA; Fri, 29 Aug 2025 15:33:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Save/restore the nested flag of an exception during VM save/restore and live migration to ensure a correct event stack level is chosen when a nested exception is injected through FRED event delivery. Signed-off-by: Xin Li (Intel) Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. Change in v4: * Add live migration support for exception nested flag (Chao Gao). --- Documentation/virt/kvm/api.rst | 21 ++++++++++++++++++++- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/uapi/asm/kvm.h | 4 +++- arch/x86/kvm/x86.c | 19 ++++++++++++++++++- include/uapi/linux/kvm.h | 1 + 5 files changed, 43 insertions(+), 3 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 6aa40ee05a4a..c496b0883a7f 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -1184,6 +1184,10 @@ The following bits are defined in the flags field: fields contain a valid state. This bit will be set whenever KVM_CAP_EXCEPTION_PAYLOAD is enabled. =20 +- KVM_VCPUEVENT_VALID_NESTED_FLAG may be set to inform that the + exception is a nested exception. This bit will be set whenever + KVM_CAP_EXCEPTION_NESTED_FLAG is enabled. + - KVM_VCPUEVENT_VALID_TRIPLE_FAULT may be set to signal that the triple_fault_pending field contains a valid state. This bit will be set whenever KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled. @@ -1283,6 +1287,10 @@ can be set in the flags field to signal that the exception_has_payload, exception_payload, and exception.pending fields contain a valid state and shall be written into the VCPU. =20 +If KVM_CAP_EXCEPTION_NESTED_FLAG is enabled, KVM_VCPUEVENT_VALID_NESTED_FL= AG +can be set in the flags field to inform that the exception is a nested +exception and exception_is_nested shall be written into the VCPU. + If KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled, KVM_VCPUEVENT_VALID_TRIPLE_F= AULT can be set in flags field to signal that the triple_fault field contains a valid state and shall be written into the VCPU. @@ -8651,7 +8659,7 @@ given VM. When this capability is enabled, KVM resets the VCPU when setting MP_STATE_INIT_RECEIVED through IOCTL. The original MP_STATE is preserved. =20 -7.43 KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED +7.44 KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED ------------------------------------------- =20 :Architectures: arm64 @@ -8662,6 +8670,17 @@ This capability indicate to the userspace whether a = PFNMAP memory region can be safely mapped as cacheable. This relies on the presence of force write back (FWB) feature support on the hardware. =20 +7.45 KVM_CAP_EXCEPTION_NESTED_FLAG +---------------------------------- + +:Architectures: x86 +:Parameters: args[0] whether feature should be enabled or not + +With this capability enabled, an exception is save/restored with the +additional information of whether it was nested or not. FRED event +delivery uses this information to ensure a correct event stack level +is chosen when a VM entry injects a nested exception. + 8. Other capabilities. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index b5a1fef8d637..0a646305e9d1 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1489,6 +1489,7 @@ struct kvm_arch { bool has_mapped_host_mmio; bool guest_can_read_msr_platform_info; bool exception_payload_enabled; + bool exception_nested_flag_enabled; =20 bool triple_fault_event; =20 diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kv= m.h index 478d9b63a9db..03ea8c46d8cf 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -326,6 +326,7 @@ struct kvm_reinject_control { #define KVM_VCPUEVENT_VALID_SMM 0x00000008 #define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010 #define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020 +#define KVM_VCPUEVENT_VALID_NESTED_FLAG 0x00000040 =20 /* Interrupt shadow states */ #define KVM_X86_SHADOW_INT_MOV_SS 0x01 @@ -363,7 +364,8 @@ struct kvm_vcpu_events { struct { __u8 pending; } triple_fault; - __u8 reserved[26]; + __u8 reserved[25]; + __u8 exception_is_nested; __u8 exception_has_payload; __u64 exception_payload; }; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7598b8d72b07..c030c7c43346 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4958,6 +4958,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, lon= g ext) case KVM_CAP_GET_MSR_FEATURES: case KVM_CAP_MSR_PLATFORM_INFO: case KVM_CAP_EXCEPTION_PAYLOAD: + case KVM_CAP_EXCEPTION_NESTED_FLAG: case KVM_CAP_X86_TRIPLE_FAULT_EVENT: case KVM_CAP_SET_GUEST_DEBUG: case KVM_CAP_LAST_CPU: @@ -5703,6 +5704,7 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct= kvm_vcpu *vcpu, events->exception.error_code =3D ex->error_code; events->exception_has_payload =3D ex->has_payload; events->exception_payload =3D ex->payload; + events->exception_is_nested =3D ex->nested; =20 events->interrupt.injected =3D vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; @@ -5728,6 +5730,8 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct= kvm_vcpu *vcpu, | KVM_VCPUEVENT_VALID_SMM); if (vcpu->kvm->arch.exception_payload_enabled) events->flags |=3D KVM_VCPUEVENT_VALID_PAYLOAD; + if (vcpu->kvm->arch.exception_nested_flag_enabled) + events->flags |=3D KVM_VCPUEVENT_VALID_NESTED_FLAG; if (vcpu->kvm->arch.triple_fault_event) { events->triple_fault.pending =3D kvm_test_request(KVM_REQ_TRIPLE_FAULT, = vcpu); events->flags |=3D KVM_VCPUEVENT_VALID_TRIPLE_FAULT; @@ -5742,7 +5746,8 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct = kvm_vcpu *vcpu, | KVM_VCPUEVENT_VALID_SHADOW | KVM_VCPUEVENT_VALID_SMM | KVM_VCPUEVENT_VALID_PAYLOAD - | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) + | KVM_VCPUEVENT_VALID_TRIPLE_FAULT + | KVM_VCPUEVENT_VALID_NESTED_FLAG)) return -EINVAL; =20 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { @@ -5757,6 +5762,13 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct= kvm_vcpu *vcpu, events->exception_has_payload =3D 0; } =20 + if (events->flags & KVM_VCPUEVENT_VALID_NESTED_FLAG) { + if (!vcpu->kvm->arch.exception_nested_flag_enabled) + return -EINVAL; + } else { + events->exception_is_nested =3D 0; + } + if ((events->exception.injected || events->exception.pending) && (events->exception.nr > 31 || events->exception.nr =3D=3D NMI_VECTOR)) return -EINVAL; @@ -5782,6 +5794,7 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct = kvm_vcpu *vcpu, vcpu->arch.exception.error_code =3D events->exception.error_code; vcpu->arch.exception.has_payload =3D events->exception_has_payload; vcpu->arch.exception.payload =3D events->exception_payload; + vcpu->arch.exception.nested =3D events->exception_is_nested; =20 vcpu->arch.interrupt.injected =3D events->interrupt.injected; vcpu->arch.interrupt.nr =3D events->interrupt.nr; @@ -6831,6 +6844,10 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, kvm->arch.exception_payload_enabled =3D cap->args[0]; r =3D 0; break; + case KVM_CAP_EXCEPTION_NESTED_FLAG: + kvm->arch.exception_nested_flag_enabled =3D cap->args[0]; + r =3D 0; + break; case KVM_CAP_X86_TRIPLE_FAULT_EVENT: kvm->arch.triple_fault_event =3D cap->args[0]; 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Fri, 29 Aug 2025 08:32:24 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4K2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481545; bh=S87+e5AIiml5QKKoFffy5oFiRjofF0+3pqtQrcseFdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FE3jkUIqAYZ3XyHQ+ueyxC3TgPQvUBXZ94l7gW1PG2QstVXhF2n6iZ7rcoF+Zioq1 X+9ki8NwGQjBha+uAIExs0ZUm7jZJpJdWmpo21UwYt/rLRFOdSaydA+X1Q4H2dkUkE N+WQ8WL+ihDaEXjQj81in/earbQK/6uvGeMYbIRJs+yCCxZOBrVjsP4Bl4qjsyMvm+ RnCJvl/HPOMSuwCyooLlcvuLVruIR1OhkbNkaPgYJtYNTSLFXYTcnxN+8df/wV1EVc Ofg3fHHjGTKB67dMDb1pX+S1Y/9wTuOk3k5mk67NxJV3xT1hv54wQTiQs84YY8xHZr BqUdHHb/agRTg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 14/21] KVM: x86: Mark CR4.FRED as not reserved Date: Fri, 29 Aug 2025 08:31:42 -0700 Message-ID: <20250829153149.2871901-15-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when guest cpu cap has FRED, i.e., 1) All of FRED KVM support is in place. 2) Guest enumerates FRED. Otherwise it is still a reserved bit. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. Change in v4: * Rebase on top of "guest_cpu_cap". Change in v3: * Don't allow CR4.FRED=3D1 before all of FRED KVM support is in place (Sean Christopherson). --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/x86.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 0a646305e9d1..92766dec64e8 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -142,7 +142,7 @@ | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ - | X86_CR4_LAM_SUP | X86_CR4_CET)) + | X86_CR4_LAM_SUP | X86_CR4_CET | X86_CR4_FRED)) =20 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) =20 diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 685eb710b1f2..c9f010862b2a 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -688,6 +688,8 @@ static inline bool __kvm_is_valid_cr4(struct kvm_vcpu *= vcpu, unsigned long cr4) if (!__cpu_has(__c, X86_FEATURE_SHSTK) && \ !__cpu_has(__c, X86_FEATURE_IBT)) \ __reserved_bits |=3D X86_CR4_CET; \ + if (!__cpu_has(__c, X86_FEATURE_FRED)) \ + __reserved_bits |=3D X86_CR4_FRED; \ __reserved_bits; \ }) =20 --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D85F1FDA8E; Fri, 29 Aug 2025 15:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481589; cv=none; b=rxiShqnGatrLMePwFx3o6EsuLNW1WyOWZtVn2ZbIkVHEdmtjZajY607AuIXpMGFcGqebRSP57WQQ97Zfnqz2w8j2l8V0by+XaqTtF6A/t+pqDQ9v/jHAYzlrxg5ed80tCj+Op0J1nhHg1PB1c9ywmiLV4rSzGSVLcxjUmT1diqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481589; c=relaxed/simple; bh=ARFaGoblNDj/7V5u02fzaPmoWcAukAa38gvCZrRWPrc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OJXI6UBss+rYQp9d8RrxWo6ttLgyfIO2W23mu3U3aLzGv0MnOLT/EYYAW+1A/XlJZLMZFmKgNfCCHOEaTeY7bMx1tsfssIsMvVNibpbuhx2jgO8/CzmUEbVGvh2WE28omO4ofNcv8DcA9EgtFIATGMQQpvZcD/323RLO8XyUAAI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=AKaL+HIs; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="AKaL+HIs" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4L2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:25 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4L2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481546; bh=u76jAY9BM212NYWyi3pL6oF5mg9gsqc88AxmrQcbX2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AKaL+HIsA8JKK+0dSA+Ti8415+LPr0w8MlX6A0bM8jzwhj9PsWoeaycgkAdYdR70K MgbHv2BaC/h2WChdF96DhLWk0xU8hhRLJBKyZnidGc7TpcvMOkBSsIicM/mw6iUWmO UkB3Er1hZf8C7kelHUICVQjipqXDxsCLIjAf5LtFgdL2YuJ1Y+Nb8vODPfXSSSvBKX 4500mr3PXGtBfWftANn6LD9/SxcWFlOzECVGbXxbWclQcOLWnn+AAmIcouN2l6jRrn 8a/Wh6kso7JkWM2hxOGtgsCfcijL1SGCN9LodAISwPi7qf1R5uOnABS2FwQuMslfX5 vJOEyWpzwaJ8g== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 15/21] KVM: VMX: Dump FRED context in dump_vmcs() Date: Fri, 29 Aug 2025 08:31:43 -0700 Message-ID: <20250829153149.2871901-16-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Add FRED related VMCS fields to dump_vmcs() to dump FRED context. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Changes in v5: * Read guest FRED RSP0 with vmx_read_guest_fred_rsp0() (Sean). * Add TB from Xuelian Guo. Change in v3: * Use (vmentry_ctrl & VM_ENTRY_LOAD_IA32_FRED) instead of is_fred_enabled() (Chao Gao). Changes in v2: * Use kvm_cpu_cap_has() instead of cpu_feature_enabled() (Chao Gao). * Dump guest FRED states only if guest has FRED enabled (Nikolay Borisov). --- arch/x86/kvm/vmx/vmx.c | 43 +++++++++++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 3d968584d854..c280e4cd4485 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1399,6 +1399,9 @@ static void vmx_write_guest_fred_rsp0(struct vcpu_vmx= *vmx, u64 data) vmx_write_guest_host_msr(vmx, MSR_IA32_FRED_RSP0, data, &vmx->msr_guest_fred_rsp0); } +#else +/* Make sure it builds on 32-bit */ +static u64 vmx_read_guest_fred_rsp0(struct vcpu_vmx *vmx) { return 0; } #endif =20 static void grow_ple_window(struct kvm_vcpu *vcpu) @@ -6436,7 +6439,7 @@ void dump_vmcs(struct kvm_vcpu *vcpu) struct vcpu_vmx *vmx =3D to_vmx(vcpu); u32 vmentry_ctl, vmexit_ctl; u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; - u64 tertiary_exec_control; + u64 tertiary_exec_control, secondary_vmexit_ctl; unsigned long cr4; int efer_slot; =20 @@ -6447,6 +6450,8 @@ void dump_vmcs(struct kvm_vcpu *vcpu) =20 vmentry_ctl =3D vmcs_read32(VM_ENTRY_CONTROLS); vmexit_ctl =3D vmcs_read32(VM_EXIT_CONTROLS); + secondary_vmexit_ctl =3D cpu_has_secondary_vmexit_ctrls() ? + vmcs_read64(SECONDARY_VM_EXIT_CONTROLS) : 0; cpu_based_exec_ctrl =3D vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); pin_based_exec_ctrl =3D vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); cr4 =3D vmcs_readl(GUEST_CR4); @@ -6493,6 +6498,16 @@ void dump_vmcs(struct kvm_vcpu *vcpu) vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); + if (vmentry_ctl & VM_ENTRY_LOAD_IA32_FRED) + pr_err("FRED guest: config=3D0x%016llx, stack_levels=3D0x%016llx\n" + "RSP0=3D0x%016llx, RSP1=3D0x%016llx\n" + "RSP2=3D0x%016llx, RSP3=3D0x%016llx\n", + vmcs_read64(GUEST_IA32_FRED_CONFIG), + vmcs_read64(GUEST_IA32_FRED_STKLVLS), + vmx_read_guest_fred_rsp0(vmx), + vmcs_read64(GUEST_IA32_FRED_RSP1), + vmcs_read64(GUEST_IA32_FRED_RSP2), + vmcs_read64(GUEST_IA32_FRED_RSP3)); efer_slot =3D vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_E= FER); if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER) pr_err("EFER=3D 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER)); @@ -6544,6 +6559,16 @@ void dump_vmcs(struct kvm_vcpu *vcpu) vmcs_readl(HOST_TR_BASE)); pr_err("GDTBase=3D%016lx IDTBase=3D%016lx\n", vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); + if (vmexit_ctl & SECONDARY_VM_EXIT_LOAD_IA32_FRED) + pr_err("FRED host: config=3D0x%016llx, stack_levels=3D0x%016llx\n" + "RSP0=3D0x%016lx, RSP1=3D0x%016llx\n" + "RSP2=3D0x%016llx, RSP3=3D0x%016llx\n", + vmcs_read64(HOST_IA32_FRED_CONFIG), + vmcs_read64(HOST_IA32_FRED_STKLVLS), + (unsigned long)task_stack_page(current) + THREAD_SIZE, + vmcs_read64(HOST_IA32_FRED_RSP1), + vmcs_read64(HOST_IA32_FRED_RSP2), + vmcs_read64(HOST_IA32_FRED_RSP3)); pr_err("CR0=3D%016lx CR3=3D%016lx CR4=3D%016lx\n", vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), vmcs_readl(HOST_CR4)); @@ -6569,25 +6594,29 @@ void dump_vmcs(struct kvm_vcpu *vcpu) pr_err("*** Control State ***\n"); pr_err("CPUBased=3D0x%08x SecondaryExec=3D0x%08x TertiaryExec=3D0x%016llx= \n", cpu_based_exec_ctrl, secondary_exec_control, tertiary_exec_control= ); - pr_err("PinBased=3D0x%08x EntryControls=3D%08x ExitControls=3D%08x\n", - pin_based_exec_ctrl, vmentry_ctl, vmexit_ctl); + pr_err("PinBased=3D0x%08x EntryControls=3D0x%08x\n", + pin_based_exec_ctrl, vmentry_ctl); + pr_err("ExitControls=3D0x%08x SecondaryExitControls=3D0x%016llx\n", + vmexit_ctl, secondary_vmexit_ctl); pr_err("ExceptionBitmap=3D%08x PFECmask=3D%08x PFECmatch=3D%08x\n", vmcs_read32(EXCEPTION_BITMAP), vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); - pr_err("VMEntry: intr_info=3D%08x errcode=3D%08x ilen=3D%08x\n", + pr_err("VMEntry: intr_info=3D%08x errcode=3D%08x ilen=3D%08x event_data= =3D%016llx\n", vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), - vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); + vmcs_read32(VM_ENTRY_INSTRUCTION_LEN), + kvm_cpu_cap_has(X86_FEATURE_FRED) ? vmcs_read64(INJECTED_EVENT_DAT= A) : 0); pr_err("VMExit: intr_info=3D%08x errcode=3D%08x ilen=3D%08x\n", vmcs_read32(VM_EXIT_INTR_INFO), vmcs_read32(VM_EXIT_INTR_ERROR_CODE), vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); pr_err(" reason=3D%08x qualification=3D%016lx\n", vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); - pr_err("IDTVectoring: info=3D%08x errcode=3D%08x\n", + pr_err("IDTVectoring: info=3D%08x errcode=3D%08x event_data=3D%016llx\n", vmcs_read32(IDT_VECTORING_INFO_FIELD), - vmcs_read32(IDT_VECTORING_ERROR_CODE)); + vmcs_read32(IDT_VECTORING_ERROR_CODE), + kvm_cpu_cap_has(X86_FEATURE_FRED) ? vmcs_read64(ORIGINAL_EVENT_DAT= A) : 0); pr_err("TSC Offset =3D 0x%016llx\n", vmcs_read64(TSC_OFFSET)); if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) pr_err("TSC Multiplier =3D 0x%016llx\n", --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9302E2EF3; Fri, 29 Aug 2025 15:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481590; cv=none; b=j579cpf+BKlojkB7HMffUH5vHCH4mpZtHA2LKWc+VxSEA1xVduAcNy8fCgURW8uKEx9+b1mcLLoqYXZjGLsoygS5vH94zWA5ljMAyNN4jLOY82KQCOHq3t/lvTLli/JFL04S7JMFex+hcO218MHuleea2zDeYzL0sJ1B0Sp8sdw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481590; c=relaxed/simple; bh=dGIU0Te0b2UjpQBN0ljD4w2cmQFMKr3KMP0Hw1YgLEU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IALrX15h+4foYLZ8lPGj6KHWv+YIxSE118dDIsd20ChPUMq3r8pouWV3N8NOeTCjaIgnxIjaP5Syno184P6D1zqudwIWptcby5dOoqO2X2ywgn0825kjFXif20sVy+Qq9TN7Y9bg5j8pSCAKxoKBnf7Vo0gWEVRNtWME2Pa2+68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=Cy3Q4YwC; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="Cy3Q4YwC" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4M2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:26 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4M2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481547; bh=x5APr7DYSSBSefCejuZvINp7dxvm6yF/POGDlz0O8VM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cy3Q4YwCmYdnx/jj15y7roWwaZCLUO5kdVgjTh557G3JM3LR2Gqw15uLG4L8ccjdh zSVpWR6QvkJXwk3tXe+EZ3PVrhe9Hns3o3DQ0ouEKCfUg+VzDBl2tIEeDuaiAR2V8P CGH6cZM9CF91R0Yz2KuM6wKvj1zJCVV1agtCLxe+V/bQMbn5228dmXLgCHORrvjOCO kxf7RMeEZ6jVavq6EOUUEN78qrQl1192AU13nbwTO08iEbFqaO6vs1jIrvBYhZbNIV SpVBVSO90nEPR2qL6kDBTXEtSeEEq+P2Z/6CYfg+m6F04BgrREJfXgiWjPC/RfxKEI pVqmMzLoDsRbg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 16/21] KVM: x86: Advertise support for FRED Date: Fri, 29 Aug 2025 08:31:44 -0700 Message-ID: <20250829153149.2871901-17-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Advertise support for FRED to userspace after changes required to enable FRED in a KVM guest are in place. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Don't advertise FRED/LKGS together, LKGS can be advertised as an independent feature (Sean). * Add TB from Xuelian Guo. --- arch/x86/kvm/cpuid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ee05b876c656..1f15aad02c68 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -994,6 +994,7 @@ void kvm_set_cpu_caps(void) F(FSRS), F(FSRC), F(WRMSRNS), + X86_64_F(FRED), X86_64_F(LKGS), F(AMX_FP16), F(AVX_IFMA), --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 812F42F659F; Fri, 29 Aug 2025 15:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481589; cv=none; b=tJXrJk+i3ZyZLHbzpLPviL75Pqe6pZCjVFla8WJsIaxc2TSM6/lO/O2lBhnSrxpzync0Sk9lpaWvMMzZt9Wi40PCMw7SdVMoIpbuczkamEHXsubXahIIZjGeqqD0gq86RA8CIoO2UlEoCMY9lVssjsEgqVE25HSLeKyz2qX/O5o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481589; c=relaxed/simple; bh=z3nyTEussIklaolK9NA6/6cGkJ56IRf3vu3UW5Ol1v4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Um+QrgvXjSWtIBzwxSCC98X1oGLmhoFOhJ0GYU9jWNW5NPoNoFos2XOUL+Ttfbipj67Dx7DPMJYRkJQGljYT2O5REJmgsZPALuhXL+WLaoL+6K3hsNIGwduyw6nR/j6gJFk7lvqJkOR0lhshOteub/bBekXZ6SUAekYQE+BoE5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=aqSCEp1c; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="aqSCEp1c" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4N2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:27 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4N2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481548; bh=lZ/WzxecCe7ne2rP//nQnPDGR0RJI2OoOg3sVAWNauA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aqSCEp1cHyWHkV3/7EXr/uI1dc8ELTM9FF24/MzZE985cVpzbdUMKtSJDQedkofNz gs4bdUFESDZl6hD+AFCQ15f3hE4EcYHyJ4tM0WiQ+UcjAeBRSKjWS4BNLt3GlYWBY8 V6EKwEiGgZEt0v/g9AOfBOW+8WU7ubG0uydZD9Lnf4KfJX6RowoXjlGgc+loPCdvsw N1VVERTzF3jBJqX8wzZVoGEEzY83nYFO6RwKGjY08LDVeTvhH+NMYElC1e8NdDPlcN vXqbyIVCsGL32nd8mF4lxy9Y7RQPmA6rP3Ng4u+xb1JI24PVOeCz8zsx+0v1cvETk8 J+dEOC8cV1WMQ== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 17/21] KVM: nVMX: Add support for the secondary VM exit controls Date: Fri, 29 Aug 2025 08:31:45 -0700 Message-ID: <20250829153149.2871901-18-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Enable the secondary VM exit controls to prepare for nested FRED. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Changes in v5: * Allow writing MSR_IA32_VMX_EXIT_CTLS2 (Sean). * Add TB from Xuelian Guo. Change in v3: * Read secondary VM exit controls from vmcs_conf insteasd of the hardware MSR MSR_IA32_VMX_EXIT_CTLS2 to avoid advertising features to L1 that KVM itself doesn't support, e.g. because the expected entry+exit pairs aren't supported. (Sean Christopherson) --- Documentation/virt/kvm/x86/nested-vmx.rst | 1 + arch/x86/kvm/vmx/capabilities.h | 1 + arch/x86/kvm/vmx/nested.c | 26 ++++++++++++++++++++++- arch/x86/kvm/vmx/vmcs12.c | 1 + arch/x86/kvm/vmx/vmcs12.h | 2 ++ arch/x86/kvm/x86.h | 2 +- 6 files changed, 31 insertions(+), 2 deletions(-) diff --git a/Documentation/virt/kvm/x86/nested-vmx.rst b/Documentation/virt= /kvm/x86/nested-vmx.rst index ac2095d41f02..e64ef231f310 100644 --- a/Documentation/virt/kvm/x86/nested-vmx.rst +++ b/Documentation/virt/kvm/x86/nested-vmx.rst @@ -217,6 +217,7 @@ struct shadow_vmcs is ever changed. u16 host_fs_selector; u16 host_gs_selector; u16 host_tr_selector; + u64 secondary_vm_exit_controls; }; =20 =20 diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index 7fe95a601c9f..c9f00b6594d9 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -37,6 +37,7 @@ struct nested_vmx_msrs { u32 pinbased_ctls_high; u32 exit_ctls_low; u32 exit_ctls_high; + u64 secondary_exit_ctls; u32 entry_ctls_low; u32 entry_ctls_high; u32 misc_low; diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index d7e2fb30fc1a..e4de8372b9f9 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -1531,6 +1531,11 @@ int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_i= ndex, u64 data) return -EINVAL; vmx->nested.msrs.vmfunc_controls =3D data; return 0; + case MSR_IA32_VMX_EXIT_CTLS2: + if (data & ~vmcs_config.nested.secondary_exit_ctls) + return -EINVAL; + vmx->nested.msrs.secondary_exit_ctls =3D data; + return 0; default: /* * The rest of the VMX capability MSRs do not support restore. @@ -1570,6 +1575,9 @@ int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32= msr_index, u64 *pdata) if (msr_index =3D=3D MSR_IA32_VMX_EXIT_CTLS) *pdata |=3D VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; break; + case MSR_IA32_VMX_EXIT_CTLS2: + *pdata =3D msrs->secondary_exit_ctls; + break; case MSR_IA32_VMX_TRUE_ENTRY_CTLS: case MSR_IA32_VMX_ENTRY_CTLS: *pdata =3D vmx_control_msr( @@ -2520,6 +2528,11 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vm= x, struct loaded_vmcs *vmcs0 exec_control &=3D ~VM_EXIT_LOAD_IA32_EFER; vm_exit_controls_set(vmx, exec_control); =20 + if (exec_control & VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) { + exec_control =3D __secondary_vm_exit_controls_get(vmcs01); + secondary_vm_exit_controls_set(vmx, exec_control); + } + /* * Interrupt/Exception Fields */ @@ -7176,7 +7189,8 @@ static void nested_vmx_setup_exit_ctls(struct vmcs_co= nfig *vmcs_conf, VM_EXIT_HOST_ADDR_SPACE_SIZE | #endif VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT | - VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_LOAD_CET_STATE; + VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_LOAD_CET_STATE | + VM_EXIT_ACTIVATE_SECONDARY_CONTROLS; msrs->exit_ctls_high |=3D VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | @@ -7185,6 +7199,16 @@ static void nested_vmx_setup_exit_ctls(struct vmcs_c= onfig *vmcs_conf, =20 /* We support free control of debug control saving. */ msrs->exit_ctls_low &=3D ~VM_EXIT_SAVE_DEBUG_CONTROLS; + + if (msrs->exit_ctls_high & VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) { + msrs->secondary_exit_ctls =3D vmcs_conf->vmexit_2nd_ctrl; + /* + * As the secondary VM exit control is always loaded, do not + * advertise any feature in it to nVMX until its nVMX support + * is ready. + */ + msrs->secondary_exit_ctls &=3D 0; + } } =20 static void nested_vmx_setup_entry_ctls(struct vmcs_config *vmcs_conf, diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c index 4233b5ca9461..3b01175f392a 100644 --- a/arch/x86/kvm/vmx/vmcs12.c +++ b/arch/x86/kvm/vmx/vmcs12.c @@ -66,6 +66,7 @@ const unsigned short vmcs12_field_offsets[] =3D { FIELD64(HOST_IA32_PAT, host_ia32_pat), FIELD64(HOST_IA32_EFER, host_ia32_efer), FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), + FIELD64(SECONDARY_VM_EXIT_CONTROLS, secondary_vm_exit_controls), FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), FIELD(EXCEPTION_BITMAP, exception_bitmap), diff --git a/arch/x86/kvm/vmx/vmcs12.h b/arch/x86/kvm/vmx/vmcs12.h index 4ad6b16525b9..7866fdce7a23 100644 --- a/arch/x86/kvm/vmx/vmcs12.h +++ b/arch/x86/kvm/vmx/vmcs12.h @@ -191,6 +191,7 @@ struct __packed vmcs12 { u16 host_gs_selector; u16 host_tr_selector; u16 guest_pml_index; + u64 secondary_vm_exit_controls; }; =20 /* @@ -372,6 +373,7 @@ static inline void vmx_check_vmcs12_offsets(void) CHECK_OFFSET(host_gs_selector, 992); CHECK_OFFSET(host_tr_selector, 994); CHECK_OFFSET(guest_pml_index, 996); + CHECK_OFFSET(secondary_vm_exit_controls, 998); } =20 extern const unsigned short vmcs12_field_offsets[]; diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index c9f010862b2a..88a4eaafc81b 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -95,7 +95,7 @@ do { \ * associated feature that KVM supports for nested virtualization. */ #define KVM_FIRST_EMULATED_VMX_MSR MSR_IA32_VMX_BASIC -#define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_VMFUNC +#define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_EXIT_CTLS2 =20 #define KVM_DEFAULT_PLE_GAP 128 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BA3B3277B4; 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arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="mNozeXxP" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4O2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:28 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4O2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481549; bh=TcNbRjd6Jo2BLAEWXiDR0Yu8Hs3YGDeUSClrnKGZ+Ws=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mNozeXxPoTYgesgbM5I1WCRdIBioMoSPExkUCOxPouCfxHc9sW7a2YbTrr4rni1km UbcEoe/9iXOUZcopxAt36BZwcFPm8czEM4B9pJhlxVkf/ONPjRafkoltGh1KdBYNfI HTQfMVbJLFWf+TooxPf1BnxLi9UimnUfagzYlCxiKC5BwWl1mMRmaOBo6TsXm+gEpn wnr50+Nl14k0ivfxXuPC1BNOqwe2rjEHTaG7zCJmAsPccG/qq0LWvhN6cz8acJ6tvf Fdzeg6/iaSi6D6df8kfZCn3+OzkQ2gV0Y+iezUvRJuLRsASfw6/ioHTaVFY5xOJDXC vifNHebNytnog== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 18/21] KVM: nVMX: Add FRED VMCS fields to nested VMX context handling Date: Fri, 29 Aug 2025 08:31:46 -0700 Message-ID: <20250829153149.2871901-19-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Extend nested VMX context management to include FRED-related VMCS fields. This enables proper handling of FRED state during nested virtualization. Because KVM always sets SECONDARY_VM_EXIT_SAVE_IA32_FRED, FRED MSRs are always saved to vmcs02. However an L1 VMM may choose to clear this bit, i.e., not to save FRED MSRs to vmcs12. This is not a problem when the L1 VMM sets SECONDARY_VM_EXIT_LOAD_IA32_FRED, as KVM then immediately loads host FRED MSRs of vmcs12 to guest FRED MSRs of vmcs01. However if the L1 VMM clears SECONDARY_VM_EXIT_LOAD_IA32_FRED, KVM should retain FRED MSRs to run the L1 VMM. To propagate guest FRED MSRs from vmcs02 to vmcs01, save them in sync_vmcs02_to_vmcs12() regardless of whether SECONDARY_VM_EXIT_SAVE_IA32_FRED is set in vmcs12. Then, use the saved values to set guest FRED MSRs in vmcs01 within load_vmcs12_host_state() when !nested_cpu_load_host_fred_state(). Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v6: * Handle FRED MSR pre-vmenter save/restore (Chao Gao). * Save FRED MSRs of vmcs02 at VM-Exit even an L1 VMM clears SECONDARY_VM_EXIT_SAVE_IA32_FRED. * Save FRED MSRs in sync_vmcs02_to_vmcs12() instead of its rare version. Change in v5: * Add TB from Xuelian Guo. Changes in v4: * Advertise VMX nested exception as if the CPU supports it (Chao Gao). * Split FRED state management controls (Chao Gao). Changes in v3: * Add and use nested_cpu_has_fred(vmcs12) because vmcs02 should be set from vmcs12 if and only if the field is enabled in L1's VMX config (Sean Christopherson). * Fix coding style issues (Sean Christopherson). Changes in v2: * Remove hyperv TLFS related changes (Jeremi Piotrowski). * Use kvm_cpu_cap_has() instead of cpu_feature_enabled() (Chao Gao). --- Documentation/virt/kvm/x86/nested-vmx.rst | 18 ++++ arch/x86/kvm/vmx/capabilities.h | 5 + arch/x86/kvm/vmx/nested.c | 113 +++++++++++++++++++++- arch/x86/kvm/vmx/nested.h | 22 +++++ arch/x86/kvm/vmx/vmcs12.c | 18 ++++ arch/x86/kvm/vmx/vmcs12.h | 36 +++++++ arch/x86/kvm/vmx/vmcs_shadow_fields.h | 4 + arch/x86/kvm/vmx/vmx.h | 41 ++++++++ 8 files changed, 255 insertions(+), 2 deletions(-) diff --git a/Documentation/virt/kvm/x86/nested-vmx.rst b/Documentation/virt= /kvm/x86/nested-vmx.rst index e64ef231f310..87fa9f3877ab 100644 --- a/Documentation/virt/kvm/x86/nested-vmx.rst +++ b/Documentation/virt/kvm/x86/nested-vmx.rst @@ -218,6 +218,24 @@ struct shadow_vmcs is ever changed. u16 host_gs_selector; u16 host_tr_selector; u64 secondary_vm_exit_controls; + u64 guest_ia32_fred_config; + u64 guest_ia32_fred_rsp1; + u64 guest_ia32_fred_rsp2; + u64 guest_ia32_fred_rsp3; + u64 guest_ia32_fred_stklvls; + u64 guest_ia32_fred_ssp1; + u64 guest_ia32_fred_ssp2; + u64 guest_ia32_fred_ssp3; + u64 host_ia32_fred_config; + u64 host_ia32_fred_rsp1; + u64 host_ia32_fred_rsp2; + u64 host_ia32_fred_rsp3; + u64 host_ia32_fred_stklvls; + u64 host_ia32_fred_ssp1; + u64 host_ia32_fred_ssp2; + u64 host_ia32_fred_ssp3; + u64 injected_event_data; + u64 original_event_data; }; =20 =20 diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index c9f00b6594d9..86e6d4b14011 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -83,6 +83,11 @@ static inline bool cpu_has_vmx_basic_no_hw_errcode(void) return vmcs_config.basic & VMX_BASIC_NO_HW_ERROR_CODE_CC; } =20 +static inline bool cpu_has_vmx_nested_exception(void) +{ + return vmcs_config.basic & VMX_BASIC_NESTED_EXCEPTION; +} + static inline bool cpu_has_virtual_nmis(void) { return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS && diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index e4de8372b9f9..0cb9a2e43ad2 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -705,6 +705,9 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct= kvm_vcpu *vcpu, =20 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); + + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, + MSR_IA32_FRED_RSP0, MSR_TYPE_RW); #endif nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW); @@ -1291,9 +1294,11 @@ static int vmx_restore_vmx_basic(struct vcpu_vmx *vm= x, u64 data) const u64 feature_bits =3D VMX_BASIC_DUAL_MONITOR_TREATMENT | VMX_BASIC_INOUT | VMX_BASIC_TRUE_CTLS | - VMX_BASIC_NO_HW_ERROR_CODE_CC; + VMX_BASIC_NO_HW_ERROR_CODE_CC | + VMX_BASIC_NESTED_EXCEPTION; =20 - const u64 reserved_bits =3D GENMASK_ULL(63, 57) | + const u64 reserved_bits =3D GENMASK_ULL(63, 59) | + BIT_ULL(57) | GENMASK_ULL(47, 45) | BIT_ULL(31); =20 @@ -2545,6 +2550,8 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx= , struct loaded_vmcs *vmcs0 vmcs12->vm_entry_instruction_len); vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, vmcs12->guest_interruptibility_info); + if (cpu_has_vmx_fred()) + vmcs_write64(INJECTED_EVENT_DATA, vmcs12->injected_event_data); vmx->loaded_vmcs->nmi_known_unmasked =3D !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); } else { @@ -2699,6 +2706,17 @@ static void prepare_vmcs02_rare(struct vcpu_vmx *vmx= , struct vmcs12 *vmcs12) vmcs12->guest_ssp, vmcs12->guest_ssp_tbl); =20 set_cr4_guest_host_mask(vmx); + + if (nested_cpu_load_guest_fred_state(vmcs12)) { + vmcs_write64(GUEST_IA32_FRED_CONFIG, vmcs12->guest_ia32_fred_config); + vmcs_write64(GUEST_IA32_FRED_RSP1, vmcs12->guest_ia32_fred_rsp1); + vmcs_write64(GUEST_IA32_FRED_RSP2, vmcs12->guest_ia32_fred_rsp2); + vmcs_write64(GUEST_IA32_FRED_RSP3, vmcs12->guest_ia32_fred_rsp3); + vmcs_write64(GUEST_IA32_FRED_STKLVLS, vmcs12->guest_ia32_fred_stklvls); + vmcs_write64(GUEST_IA32_FRED_SSP1, vmcs12->guest_ia32_fred_ssp1); + vmcs_write64(GUEST_IA32_FRED_SSP2, vmcs12->guest_ia32_fred_ssp2); + vmcs_write64(GUEST_IA32_FRED_SSP3, vmcs12->guest_ia32_fred_ssp3); + } } =20 /* @@ -2765,6 +2783,18 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, str= uct vmcs12 *vmcs12, vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); } =20 + if (!vmx->nested.nested_run_pending || + !nested_cpu_load_guest_fred_state(vmcs12)) { + vmcs_write64(GUEST_IA32_FRED_CONFIG, vmx->nested.pre_vmenter_fred_config= ); + vmcs_write64(GUEST_IA32_FRED_RSP1, vmx->nested.pre_vmenter_fred_rsp1); + vmcs_write64(GUEST_IA32_FRED_RSP2, vmx->nested.pre_vmenter_fred_rsp2); + vmcs_write64(GUEST_IA32_FRED_RSP3, vmx->nested.pre_vmenter_fred_rsp3); + vmcs_write64(GUEST_IA32_FRED_STKLVLS, vmx->nested.pre_vmenter_fred_stklv= ls); + vmcs_write64(GUEST_IA32_FRED_SSP1, vmx->nested.pre_vmenter_fred_ssp1); + vmcs_write64(GUEST_IA32_FRED_SSP2, vmx->nested.pre_vmenter_fred_ssp2); + vmcs_write64(GUEST_IA32_FRED_SSP3, vmx->nested.pre_vmenter_fred_ssp3); + } + vcpu->arch.tsc_offset =3D kvm_calc_nested_tsc_offset( vcpu->arch.l1_tsc_offset, vmx_get_l2_tsc_offset(vcpu), @@ -3679,6 +3709,18 @@ enum nvmx_vmentry_status nested_vmx_enter_non_root_m= ode(struct kvm_vcpu *vcpu, &vmx->nested.pre_vmenter_ssp, &vmx->nested.pre_vmenter_ssp_tbl); =20 + if (!vmx->nested.nested_run_pending || + !nested_cpu_load_guest_fred_state(vmcs12)) { + vmx->nested.pre_vmenter_fred_config =3D vmcs_read64(GUEST_IA32_FRED_CONF= IG); + vmx->nested.pre_vmenter_fred_rsp1 =3D vmcs_read64(GUEST_IA32_FRED_RSP1); + vmx->nested.pre_vmenter_fred_rsp2 =3D vmcs_read64(GUEST_IA32_FRED_RSP2); + vmx->nested.pre_vmenter_fred_rsp3 =3D vmcs_read64(GUEST_IA32_FRED_RSP3); + vmx->nested.pre_vmenter_fred_stklvls =3D vmcs_read64(GUEST_IA32_FRED_STK= LVLS); + vmx->nested.pre_vmenter_fred_ssp1 =3D vmcs_read64(GUEST_IA32_FRED_SSP1); + vmx->nested.pre_vmenter_fred_ssp2 =3D vmcs_read64(GUEST_IA32_FRED_SSP2); + vmx->nested.pre_vmenter_fred_ssp3 =3D vmcs_read64(GUEST_IA32_FRED_SSP3); + } + /* * Overwrite vmcs01.GUEST_CR3 with L1's CR3 if EPT is disabled *and* * nested early checks are disabled. In the event of a "late" VM-Fail, @@ -3986,6 +4028,8 @@ static void vmcs12_save_pending_event(struct kvm_vcpu= *vcpu, u32 idt_vectoring; unsigned int nr; =20 + vmcs12->original_event_data =3D 0; + /* * Per the SDM, VM-Exits due to double and triple faults are never * considered to occur during event delivery, even if the double/triple @@ -4024,6 +4068,13 @@ static void vmcs12_save_pending_event(struct kvm_vcp= u *vcpu, vcpu->arch.exception.error_code; } =20 + if ((vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) && + (vmcs12->guest_cr4 & X86_CR4_FRED) && + (vcpu->arch.exception.nested)) + idt_vectoring |=3D VECTORING_INFO_NESTED_EXCEPTION_MASK; + + vmcs12->original_event_data =3D vcpu->arch.exception.event_data; + vmcs12->idt_vectoring_info_field =3D idt_vectoring; } else if (vcpu->arch.nmi_injected) { vmcs12->idt_vectoring_info_field =3D @@ -4766,6 +4817,26 @@ static void sync_vmcs02_to_vmcs12(struct kvm_vcpu *v= cpu, struct vmcs12 *vmcs12) vmcs_read_cet_state(&vmx->vcpu, &vmcs12->guest_s_cet, &vmcs12->guest_ssp, &vmcs12->guest_ssp_tbl); + + vmx->nested.fred_msr_at_vmexit.fred_config =3D vmcs_read64(GUEST_IA32_FRE= D_CONFIG); + vmx->nested.fred_msr_at_vmexit.fred_rsp1 =3D vmcs_read64(GUEST_IA32_FRED_= RSP1); + vmx->nested.fred_msr_at_vmexit.fred_rsp2 =3D vmcs_read64(GUEST_IA32_FRED_= RSP2); + vmx->nested.fred_msr_at_vmexit.fred_rsp3 =3D vmcs_read64(GUEST_IA32_FRED_= RSP3); + vmx->nested.fred_msr_at_vmexit.fred_stklvls =3D vmcs_read64(GUEST_IA32_FR= ED_STKLVLS); + vmx->nested.fred_msr_at_vmexit.fred_ssp1 =3D vmcs_read64(GUEST_IA32_FRED_= SSP1); + vmx->nested.fred_msr_at_vmexit.fred_ssp2 =3D vmcs_read64(GUEST_IA32_FRED_= SSP2); + vmx->nested.fred_msr_at_vmexit.fred_ssp3 =3D vmcs_read64(GUEST_IA32_FRED_= SSP3); + + if (nested_cpu_save_guest_fred_state(vmcs12)) { + vmcs12->guest_ia32_fred_config =3D vmx->nested.fred_msr_at_vmexit.fred_c= onfig; + vmcs12->guest_ia32_fred_rsp1 =3D vmx->nested.fred_msr_at_vmexit.fred_rsp= 1; + vmcs12->guest_ia32_fred_rsp2 =3D vmx->nested.fred_msr_at_vmexit.fred_rsp= 2; + vmcs12->guest_ia32_fred_rsp3 =3D vmx->nested.fred_msr_at_vmexit.fred_rsp= 3; + vmcs12->guest_ia32_fred_stklvls =3D vmx->nested.fred_msr_at_vmexit.fred_= stklvls; + vmcs12->guest_ia32_fred_ssp1 =3D vmx->nested.fred_msr_at_vmexit.fred_ssp= 1; + vmcs12->guest_ia32_fred_ssp2 =3D vmx->nested.fred_msr_at_vmexit.fred_ssp= 2; + vmcs12->guest_ia32_fred_ssp3 =3D vmx->nested.fred_msr_at_vmexit.fred_ssp= 3; + } } =20 /* @@ -4810,6 +4881,21 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, st= ruct vmcs12 *vmcs12, =20 vmcs12->vm_exit_intr_info =3D exit_intr_info; vmcs12->vm_exit_instruction_len =3D exit_insn_len; + + /* + * When there is a valid original event, the exiting event is a nested + * event during delivery of the earlier original event. + * + * FRED event delivery reflects this relationship by setting the value + * of the nested exception bit of VM-exit interruption information + * (aka exiting-event identification) to that of the valid bit of the + * IDT-vectoring information (aka original-event identification). + */ + if ((vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && + (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) && + (vmcs12->guest_cr4 & X86_CR4_FRED)) + vmcs12->vm_exit_intr_info |=3D INTR_INFO_NESTED_EXCEPTION_MASK; + vmcs12->vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); =20 /* @@ -4838,6 +4924,7 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, str= uct vmcs12 *vmcs12, static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) { + struct vcpu_vmx *vmx =3D to_vmx(vcpu); enum vm_entry_failure_code ignored; struct kvm_segment seg; =20 @@ -4912,6 +4999,26 @@ static void load_vmcs12_host_state(struct kvm_vcpu *= vcpu, WARN_ON_ONCE(__kvm_emulate_msr_write(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->host_ia32_perf_global_ctrl)); =20 + if (nested_cpu_load_host_fred_state(vmcs12)) { + vmcs_write64(GUEST_IA32_FRED_CONFIG, vmcs12->host_ia32_fred_config); + vmcs_write64(GUEST_IA32_FRED_RSP1, vmcs12->host_ia32_fred_rsp1); + vmcs_write64(GUEST_IA32_FRED_RSP2, vmcs12->host_ia32_fred_rsp2); + vmcs_write64(GUEST_IA32_FRED_RSP3, vmcs12->host_ia32_fred_rsp3); + vmcs_write64(GUEST_IA32_FRED_STKLVLS, vmcs12->host_ia32_fred_stklvls); + vmcs_write64(GUEST_IA32_FRED_SSP1, vmcs12->host_ia32_fred_ssp1); + vmcs_write64(GUEST_IA32_FRED_SSP2, vmcs12->host_ia32_fred_ssp2); + vmcs_write64(GUEST_IA32_FRED_SSP3, vmcs12->host_ia32_fred_ssp3); + } else { + vmcs_write64(GUEST_IA32_FRED_CONFIG, vmx->nested.fred_msr_at_vmexit.fred= _config); + vmcs_write64(GUEST_IA32_FRED_RSP1, vmx->nested.fred_msr_at_vmexit.fred_r= sp1); + vmcs_write64(GUEST_IA32_FRED_RSP2, vmx->nested.fred_msr_at_vmexit.fred_r= sp2); + vmcs_write64(GUEST_IA32_FRED_RSP3, vmx->nested.fred_msr_at_vmexit.fred_r= sp3); + vmcs_write64(GUEST_IA32_FRED_STKLVLS, vmx->nested.fred_msr_at_vmexit.fre= d_stklvls); + vmcs_write64(GUEST_IA32_FRED_SSP1, vmx->nested.fred_msr_at_vmexit.fred_s= sp1); + vmcs_write64(GUEST_IA32_FRED_SSP2, vmx->nested.fred_msr_at_vmexit.fred_s= sp2); + vmcs_write64(GUEST_IA32_FRED_SSP3, vmx->nested.fred_msr_at_vmexit.fred_s= sp3); + } + /* Set L1 segment info according to Intel SDM 27.5.2 Loading Host Segment and Descriptor-Table Registers */ seg =3D (struct kvm_segment) { @@ -7379,6 +7486,8 @@ static void nested_vmx_setup_basic(struct nested_vmx_= msrs *msrs) msrs->basic |=3D VMX_BASIC_INOUT; if (cpu_has_vmx_basic_no_hw_errcode()) msrs->basic |=3D VMX_BASIC_NO_HW_ERROR_CODE_CC; + if (cpu_has_vmx_nested_exception()) + msrs->basic |=3D VMX_BASIC_NESTED_EXCEPTION; } =20 static void nested_vmx_setup_cr_fixed(struct nested_vmx_msrs *msrs) diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index 983484d42ebf..a99d3d83d58e 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -249,6 +249,11 @@ static inline bool nested_cpu_has_save_preemption_time= r(struct vmcs12 *vmcs12) VM_EXIT_SAVE_VMX_PREEMPTION_TIMER; } =20 +static inline bool nested_cpu_has_secondary_vm_exit_controls(struct vmcs12= *vmcs12) +{ + return vmcs12->vm_exit_controls & VM_EXIT_ACTIVATE_SECONDARY_CONTROLS; +} + static inline bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) { return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu)); @@ -269,6 +274,23 @@ static inline bool nested_cpu_has_encls_exit(struct vm= cs12 *vmcs12) return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING); } =20 +static inline bool nested_cpu_load_guest_fred_state(struct vmcs12 *vmcs12) +{ + return vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_FRED; +} + +static inline bool nested_cpu_save_guest_fred_state(struct vmcs12 *vmcs12) +{ + return nested_cpu_has_secondary_vm_exit_controls(vmcs12) && + vmcs12->secondary_vm_exit_controls & SECONDARY_VM_EXIT_SAVE_IA32_F= RED; +} + +static inline bool nested_cpu_load_host_fred_state(struct vmcs12 *vmcs12) +{ + return nested_cpu_has_secondary_vm_exit_controls(vmcs12) && + vmcs12->secondary_vm_exit_controls & SECONDARY_VM_EXIT_LOAD_IA32_F= RED; +} + /* * if fixed0[i] =3D=3D 1: val[i] must be 1 * if fixed1[i] =3D=3D 0: val[i] must be 0 diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c index 3b01175f392a..9691e709061f 100644 --- a/arch/x86/kvm/vmx/vmcs12.c +++ b/arch/x86/kvm/vmx/vmcs12.c @@ -67,6 +67,24 @@ const unsigned short vmcs12_field_offsets[] =3D { FIELD64(HOST_IA32_EFER, host_ia32_efer), FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), FIELD64(SECONDARY_VM_EXIT_CONTROLS, secondary_vm_exit_controls), + FIELD64(INJECTED_EVENT_DATA, injected_event_data), + FIELD64(ORIGINAL_EVENT_DATA, original_event_data), + FIELD64(GUEST_IA32_FRED_CONFIG, guest_ia32_fred_config), + FIELD64(GUEST_IA32_FRED_RSP1, guest_ia32_fred_rsp1), + FIELD64(GUEST_IA32_FRED_RSP2, guest_ia32_fred_rsp2), + FIELD64(GUEST_IA32_FRED_RSP3, guest_ia32_fred_rsp3), + FIELD64(GUEST_IA32_FRED_STKLVLS, guest_ia32_fred_stklvls), + FIELD64(GUEST_IA32_FRED_SSP1, guest_ia32_fred_ssp1), + FIELD64(GUEST_IA32_FRED_SSP2, guest_ia32_fred_ssp2), + FIELD64(GUEST_IA32_FRED_SSP3, guest_ia32_fred_ssp3), + FIELD64(HOST_IA32_FRED_CONFIG, host_ia32_fred_config), + FIELD64(HOST_IA32_FRED_RSP1, host_ia32_fred_rsp1), + FIELD64(HOST_IA32_FRED_RSP2, host_ia32_fred_rsp2), + FIELD64(HOST_IA32_FRED_RSP3, host_ia32_fred_rsp3), + FIELD64(HOST_IA32_FRED_STKLVLS, host_ia32_fred_stklvls), + FIELD64(HOST_IA32_FRED_SSP1, host_ia32_fred_ssp1), + FIELD64(HOST_IA32_FRED_SSP2, host_ia32_fred_ssp2), + FIELD64(HOST_IA32_FRED_SSP3, host_ia32_fred_ssp3), FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), FIELD(EXCEPTION_BITMAP, exception_bitmap), diff --git a/arch/x86/kvm/vmx/vmcs12.h b/arch/x86/kvm/vmx/vmcs12.h index 7866fdce7a23..a3853536a575 100644 --- a/arch/x86/kvm/vmx/vmcs12.h +++ b/arch/x86/kvm/vmx/vmcs12.h @@ -192,6 +192,24 @@ struct __packed vmcs12 { u16 host_tr_selector; u16 guest_pml_index; u64 secondary_vm_exit_controls; + u64 guest_ia32_fred_config; + u64 guest_ia32_fred_rsp1; + u64 guest_ia32_fred_rsp2; + u64 guest_ia32_fred_rsp3; + u64 guest_ia32_fred_stklvls; + u64 guest_ia32_fred_ssp1; + u64 guest_ia32_fred_ssp2; + u64 guest_ia32_fred_ssp3; + u64 host_ia32_fred_config; + u64 host_ia32_fred_rsp1; + u64 host_ia32_fred_rsp2; + u64 host_ia32_fred_rsp3; + u64 host_ia32_fred_stklvls; + u64 host_ia32_fred_ssp1; + u64 host_ia32_fred_ssp2; + u64 host_ia32_fred_ssp3; + u64 injected_event_data; + u64 original_event_data; }; =20 /* @@ -374,6 +392,24 @@ static inline void vmx_check_vmcs12_offsets(void) CHECK_OFFSET(host_tr_selector, 994); CHECK_OFFSET(guest_pml_index, 996); CHECK_OFFSET(secondary_vm_exit_controls, 998); + CHECK_OFFSET(guest_ia32_fred_config, 1006); + CHECK_OFFSET(guest_ia32_fred_rsp1, 1014); + CHECK_OFFSET(guest_ia32_fred_rsp2, 1022); + CHECK_OFFSET(guest_ia32_fred_rsp3, 1030); + CHECK_OFFSET(guest_ia32_fred_stklvls, 1038); + CHECK_OFFSET(guest_ia32_fred_ssp1, 1046); + CHECK_OFFSET(guest_ia32_fred_ssp2, 1054); + CHECK_OFFSET(guest_ia32_fred_ssp3, 1062); + CHECK_OFFSET(host_ia32_fred_config, 1070); + CHECK_OFFSET(host_ia32_fred_rsp1, 1078); + CHECK_OFFSET(host_ia32_fred_rsp2, 1086); + CHECK_OFFSET(host_ia32_fred_rsp3, 1094); + CHECK_OFFSET(host_ia32_fred_stklvls, 1102); + CHECK_OFFSET(host_ia32_fred_ssp1, 1110); + CHECK_OFFSET(host_ia32_fred_ssp2, 1118); + CHECK_OFFSET(host_ia32_fred_ssp3, 1126); + CHECK_OFFSET(injected_event_data, 1134); + CHECK_OFFSET(original_event_data, 1142); } =20 extern const unsigned short vmcs12_field_offsets[]; diff --git a/arch/x86/kvm/vmx/vmcs_shadow_fields.h b/arch/x86/kvm/vmx/vmcs_= shadow_fields.h index cad128d1657b..da338327c2b3 100644 --- a/arch/x86/kvm/vmx/vmcs_shadow_fields.h +++ b/arch/x86/kvm/vmx/vmcs_shadow_fields.h @@ -74,6 +74,10 @@ SHADOW_FIELD_RW(HOST_GS_BASE, host_gs_base) /* 64-bit */ SHADOW_FIELD_RO(GUEST_PHYSICAL_ADDRESS, guest_physical_address) SHADOW_FIELD_RO(GUEST_PHYSICAL_ADDRESS_HIGH, guest_physical_address) +SHADOW_FIELD_RO(ORIGINAL_EVENT_DATA, original_event_data) +SHADOW_FIELD_RO(ORIGINAL_EVENT_DATA_HIGH, original_event_data) +SHADOW_FIELD_RW(INJECTED_EVENT_DATA, injected_event_data) +SHADOW_FIELD_RW(INJECTED_EVENT_DATA_HIGH, injected_event_data) =20 #undef SHADOW_FIELD_RO #undef SHADOW_FIELD_RW diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 733fa2ef4bea..825e68acd5e9 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -67,6 +67,37 @@ struct pt_desc { struct pt_ctx guest; }; =20 +/* + * Used to snapshot FRED MSRs that may NOT be saved to vmcs12 as specified + * in the VM-Exit controls of vmcs12 configured by L1 VMM. + * + * FRED MSRs are *always* saved into vmcs02 because KVM always sets + * SECONDARY_VM_EXIT_SAVE_IA32_FRED. However an L1 VMM may choose to clear + * this bit, resulting in FRED MSRs not being propagated to vmcs12 from + * vmcs02. When the L1 VMM sets SECONDARY_VM_EXIT_LOAD_IA32_FRED, this is + * not a problem, since KVM then immediately loads the host FRED MSRs of + * vmcs12 to the guest FRED MSRs of vmcs01. + * + * But if the L1 VMM clears SECONDARY_VM_EXIT_LOAD_IA32_FRED, KVM should + * retain the FRED MSRs, i.e., propagate the guest FRED MSRs of vmcs02 to + * the guest FRED MSRs of vmcs01. + * + * This structure stores guest FRED MSRs that an L1 VMM opts not to save + * during VM-Exits from L2 to L1. These MSRs may still be retained for + * running the L1 VMM if SECONDARY_VM_EXIT_LOAD_IA32_FRED is cleared in + * vmcs12. + */ +struct fred_msr_at_vmexit { + u64 fred_config; + u64 fred_rsp1; + u64 fred_rsp2; + u64 fred_rsp3; + u64 fred_stklvls; + u64 fred_ssp1; + u64 fred_ssp2; + u64 fred_ssp3; +}; + /* * The nested_vmx structure is part of vcpu_vmx, and holds information we = need * for correct emulation of VMX (i.e., nested VMX) on this vcpu. @@ -184,6 +215,16 @@ struct nested_vmx { u64 pre_vmenter_s_cet; u64 pre_vmenter_ssp; u64 pre_vmenter_ssp_tbl; + u64 pre_vmenter_fred_config; + u64 pre_vmenter_fred_rsp1; + u64 pre_vmenter_fred_rsp2; + u64 pre_vmenter_fred_rsp3; + u64 pre_vmenter_fred_stklvls; + u64 pre_vmenter_fred_ssp1; + u64 pre_vmenter_fred_ssp2; + u64 pre_vmenter_fred_ssp3; + + struct fred_msr_at_vmexit fred_msr_at_vmexit; =20 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ int l1_tpr_threshold; --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07353322A1A; Fri, 29 Aug 2025 15:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.137.202.136 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; cv=none; b=GlOLnP+ZXOmY5LdP02LRYboqexMhPBGBNuiRdJOeu8Upcl7T+RT9qZx07OauT2TcHq2lbGz/6YiXozZrRZHPiLXAq/HHZXeE4I/GsY6da6n9IyCASQhd1Ei13UE+/VmIA1vhfZ1FuePlCls5DvbawRwJZN6yH7vAeuERm6D6Wdg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756481592; c=relaxed/simple; bh=R3OvcTNx4qCw+JYMBbFTvH1jA3lYOMCUyQc7AWbcFCk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B/KtcwtQOc9hxXvXLMwnUVz/grDUnsB7zh8WchliscBtZ646Uv6uBpkaspzMsSbjugJnJ8YekHCrxvtbYbrG8svuup6YYVPz+pZpYV9fAUWb62/xgeg6HqePI5oX1Hpf9g9EreqWuYszlmfjB1uNolLhYTGAZXcl8yz695tIckA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com; spf=pass smtp.mailfrom=zytor.com; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b=ViHH+5Z3; arc=none smtp.client-ip=198.137.202.136 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="ViHH+5Z3" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4P2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:29 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4P2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481550; bh=NStq2uoPAwFsE+xhru2r7YtBDBQA5s2aqie6Z7C691U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ViHH+5Z36e4nMuf+Jbucx4BwSBZUUDT7ij4okp3Cf1/52Iw2kb0bMBZn3Dh0pP/bU FxFKzFsoVMxVP6/wFdhEm+iOAcs1AffrvEotpUDI+w1PYhD7hx21T25PCTrD4ohf5s wuNlZrpQ9CeMTv+crOcy1Ws/7v1vIDjGGiGJt9zVPye3oiSzDllVaQQeNeCAsnSq3g GVNbQ2LagGjCylgMA9e+R/aMHDqM921Um6recrdeh42K9x7e5t7z8HOIfCAk36sHd7 gPITs8q8gDJVzkYJEzZBTGZKpd9f8Z1g+Dy6j9b+KcEe8+zNHQNhB1pznHddiX5aai D3uWzUi0jSgoA== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 19/21] KVM: nVMX: Add FRED-related VMCS field checks Date: Fri, 29 Aug 2025 08:31:47 -0700 Message-ID: <20250829153149.2871901-20-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li As with real hardware, nested VMX validates various VMCS fields, including control and guest/host state fields. This patch adds checks for FRED-relat= ed VMCS fields to support nested FRED functionality. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. --- arch/x86/kvm/vmx/nested.c | 117 +++++++++++++++++++++++++++++++++----- 1 file changed, 104 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 0cb9a2e43ad2..b56bbac36749 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -3031,6 +3031,8 @@ static int nested_check_vm_entry_controls(struct kvm_= vcpu *vcpu, struct vmcs12 *vmcs12) { struct vcpu_vmx *vmx =3D to_vmx(vcpu); + bool fred_enabled =3D (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) && + (vmcs12->guest_cr4 & X86_CR4_FRED); =20 if (CC(!vmx_control_verify(vmcs12->vm_entry_controls, vmx->nested.msrs.entry_ctls_low, @@ -3048,22 +3050,11 @@ static int nested_check_vm_entry_controls(struct kv= m_vcpu *vcpu, u8 vector =3D intr_info & INTR_INFO_VECTOR_MASK; u32 intr_type =3D intr_info & INTR_INFO_INTR_TYPE_MASK; bool has_error_code =3D intr_info & INTR_INFO_DELIVER_CODE_MASK; + bool has_nested_exception =3D vmx->nested.msrs.basic & VMX_BASIC_NESTED_= EXCEPTION; bool urg =3D nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST); bool prot_mode =3D !urg || vmcs12->guest_cr0 & X86_CR0_PE; =20 - /* VM-entry interruption-info field: interruption type */ - if (CC(intr_type =3D=3D INTR_TYPE_RESERVED) || - CC(intr_type =3D=3D INTR_TYPE_OTHER_EVENT && - !nested_cpu_supports_monitor_trap_flag(vcpu))) - return -EINVAL; - - /* VM-entry interruption-info field: vector */ - if (CC(intr_type =3D=3D INTR_TYPE_NMI_INTR && vector !=3D NMI_VECTOR) || - CC(intr_type =3D=3D INTR_TYPE_HARD_EXCEPTION && vector > 31) || - CC(intr_type =3D=3D INTR_TYPE_OTHER_EVENT && vector !=3D 0)) - return -EINVAL; - /* * Cannot deliver error code in real mode or if the interrupt * type is not hardware exception. For other cases, do the @@ -3088,8 +3079,28 @@ static int nested_check_vm_entry_controls(struct kvm= _vcpu *vcpu, if (CC(intr_info & INTR_INFO_RESVD_BITS_MASK)) return -EINVAL; =20 - /* VM-entry instruction length */ + /* + * When the CPU enumerates VMX nested-exception support, bit 13 + * (set to indicate a nested exception) of the intr info field + * may have value 1. Otherwise bit 13 is reserved. + */ + if (CC(!(has_nested_exception && intr_type =3D=3D INTR_TYPE_HARD_EXCEPTI= ON) && + intr_info & INTR_INFO_NESTED_EXCEPTION_MASK)) + return -EINVAL; + switch (intr_type) { + case INTR_TYPE_EXT_INTR: + break; + case INTR_TYPE_RESERVED: + return -EINVAL; + case INTR_TYPE_NMI_INTR: + if (CC(vector !=3D NMI_VECTOR)) + return -EINVAL; + break; + case INTR_TYPE_HARD_EXCEPTION: + if (CC(vector > 31)) + return -EINVAL; + break; case INTR_TYPE_SOFT_EXCEPTION: case INTR_TYPE_SOFT_INTR: case INTR_TYPE_PRIV_SW_EXCEPTION: @@ -3097,6 +3108,24 @@ static int nested_check_vm_entry_controls(struct kvm= _vcpu *vcpu, CC(vmcs12->vm_entry_instruction_len =3D=3D 0 && CC(!nested_cpu_has_zero_length_injection(vcpu)))) return -EINVAL; + break; + case INTR_TYPE_OTHER_EVENT: + switch (vector) { + case 0: + if (CC(!nested_cpu_supports_monitor_trap_flag(vcpu))) + return -EINVAL; + break; + case 1: + case 2: + if (CC(!fred_enabled)) + return -EINVAL; + if (CC(vmcs12->vm_entry_instruction_len > X86_MAX_INSTRUCTION_LENGTH)) + return -EINVAL; + break; + default: + return -EINVAL; + } + break; } } =20 @@ -3184,9 +3213,29 @@ static int nested_vmx_check_host_state(struct kvm_vc= pu *vcpu, if (ia32e) { if (CC(!(vmcs12->host_cr4 & X86_CR4_PAE))) return -EINVAL; + if (vmcs12->vm_exit_controls & VM_EXIT_ACTIVATE_SECONDARY_CONTROLS && + vmcs12->secondary_vm_exit_controls & SECONDARY_VM_EXIT_LOAD_IA32_FRE= D) { + if (CC(vmcs12->host_ia32_fred_config & + (BIT_ULL(11) | GENMASK_ULL(5, 4) | BIT_ULL(2))) || + CC(vmcs12->host_ia32_fred_rsp1 & GENMASK_ULL(5, 0)) || + CC(vmcs12->host_ia32_fred_rsp2 & GENMASK_ULL(5, 0)) || + CC(vmcs12->host_ia32_fred_rsp3 & GENMASK_ULL(5, 0)) || + CC(vmcs12->host_ia32_fred_ssp1 & GENMASK_ULL(2, 0)) || + CC(vmcs12->host_ia32_fred_ssp2 & GENMASK_ULL(2, 0)) || + CC(vmcs12->host_ia32_fred_ssp3 & GENMASK_ULL(2, 0)) || + CC(is_noncanonical_msr_address(vmcs12->host_ia32_fred_config & PAGE= _MASK, vcpu)) || + CC(is_noncanonical_msr_address(vmcs12->host_ia32_fred_rsp1, vcpu)) = || + CC(is_noncanonical_msr_address(vmcs12->host_ia32_fred_rsp2, vcpu)) = || + CC(is_noncanonical_msr_address(vmcs12->host_ia32_fred_rsp3, vcpu)) = || + CC(is_noncanonical_msr_address(vmcs12->host_ia32_fred_ssp1, vcpu)) = || + CC(is_noncanonical_msr_address(vmcs12->host_ia32_fred_ssp2, vcpu)) = || + CC(is_noncanonical_msr_address(vmcs12->host_ia32_fred_ssp3, vcpu))) + return -EINVAL; + } } else { if (CC(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) || CC(vmcs12->host_cr4 & X86_CR4_PCIDE) || + CC(vmcs12->host_cr4 & X86_CR4_FRED) || CC((vmcs12->host_rip) >> 32)) return -EINVAL; } @@ -3354,6 +3403,48 @@ static int nested_vmx_check_guest_state(struct kvm_v= cpu *vcpu, CC((vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))) return -EINVAL; =20 + if (ia32e) { + if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_FRED) { + if (CC(vmcs12->guest_ia32_fred_config & + (BIT_ULL(11) | GENMASK_ULL(5, 4) | BIT_ULL(2))) || + CC(vmcs12->guest_ia32_fred_rsp1 & GENMASK_ULL(5, 0)) || + CC(vmcs12->guest_ia32_fred_rsp2 & GENMASK_ULL(5, 0)) || + CC(vmcs12->guest_ia32_fred_rsp3 & GENMASK_ULL(5, 0)) || + CC(vmcs12->guest_ia32_fred_ssp1 & GENMASK_ULL(2, 0)) || + CC(vmcs12->guest_ia32_fred_ssp2 & GENMASK_ULL(2, 0)) || + CC(vmcs12->guest_ia32_fred_ssp3 & GENMASK_ULL(2, 0)) || + CC(is_noncanonical_msr_address(vmcs12->guest_ia32_fred_config & PAG= E_MASK, vcpu)) || + CC(is_noncanonical_msr_address(vmcs12->guest_ia32_fred_rsp1, vcpu))= || + CC(is_noncanonical_msr_address(vmcs12->guest_ia32_fred_rsp2, vcpu))= || + CC(is_noncanonical_msr_address(vmcs12->guest_ia32_fred_rsp3, vcpu))= || + CC(is_noncanonical_msr_address(vmcs12->guest_ia32_fred_ssp1, vcpu))= || + CC(is_noncanonical_msr_address(vmcs12->guest_ia32_fred_ssp2, vcpu))= || + CC(is_noncanonical_msr_address(vmcs12->guest_ia32_fred_ssp3, vcpu))) + return -EINVAL; + } + if (vmcs12->guest_cr4 & X86_CR4_FRED) { + unsigned int ss_dpl =3D VMX_AR_DPL(vmcs12->guest_ss_ar_bytes); + switch (ss_dpl) { + case 0: + if (CC(!(vmcs12->guest_cs_ar_bytes & VMX_AR_L_MASK))) + return -EINVAL; + break; + case 1: + case 2: + return -EINVAL; + case 3: + if (CC(vmcs12->guest_rflags & X86_EFLAGS_IOPL)) + return -EINVAL; + if (CC(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_STI)) + return -EINVAL; + break; + } + } + } else { + if (CC(vmcs12->guest_cr4 & X86_CR4_FRED)) + return -EINVAL; + } + if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_CET_STATE) { if (CC(!is_valid_cet_state(vcpu, vmcs12->guest_s_cet, vmcs12->guest_ssp, vmcs12->guest_ssp_tbl))) --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0183A32277B; Fri, 29 Aug 2025 15:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=zytor.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zytor.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=zytor.com header.i=@zytor.com header.b="UyezWEZN" Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 57TFVo4Q2871953 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 29 Aug 2025 08:32:30 -0700 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 57TFVo4Q2871953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025082201; t=1756481551; bh=ACzNt+u257VphxAeHF2b6irR2TsyZO3G2uTZiNtku4c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UyezWEZNPD/SoF3wjWt6pkbwyJ7gNYY9amt2CQG7phAf1zhYl/mv+2eHYyy4TLnxS xGigRq6hdPoNJf9Qrej1wdakGox+Gsu/nJZQ/qxAI0XBBIJl9OWbRqSyAeD7gD/wir m5tzf3f8qBy0iut/tzdZctT4RBuFhsmWLDKYP7zXkyBCA6TfOo0A5KaR5dowEzrrEU VC8rj/h7f17E+DPUDe2kZ6bx2Lrm9lqeJgsxwJB9S2miA+Wd7cpwYGPD5iERro7GQL CyoC34do2PW9/mOXczj6bC4kt/y46URYfS4Y+XnG4ycuFdiGGCejX/r+R0upPkSNyF 7CnHhluO00k2w== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, xin@zytor.com, luto@kernel.org, peterz@infradead.org, andrew.cooper3@citrix.com, chao.gao@intel.com, hch@infradead.org Subject: [PATCH v7 20/21] KVM: nVMX: Add prerequisites to SHADOW_FIELD_R[OW] macros Date: Fri, 29 Aug 2025 08:31:48 -0700 Message-ID: <20250829153149.2871901-21-xin@zytor.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829153149.2871901-1-xin@zytor.com> References: <20250829153149.2871901-1-xin@zytor.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xin Li Add VMX feature checks before accessing VMCS fields via SHADOW_FIELD_R[OW] macros, as some fields may not be supported on all CPUs. Functions like copy_shadow_to_vmcs12() and copy_vmcs12_to_shadow() access VMCS fields that may not exist on certain hardware, such as INJECTED_EVENT_DATA. To avoid VMREAD/VMWRITE warnings, skip syncing fields tied to unsupported VMX features. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. Change since v2: * Add __SHADOW_FIELD_R[OW] for better readability or maintability (Sean). --- arch/x86/kvm/vmx/nested.c | 79 +++++++++++++++++++-------- arch/x86/kvm/vmx/vmcs_shadow_fields.h | 41 +++++++++----- 2 files changed, 83 insertions(+), 37 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index b56bbac36749..266115525b9e 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -55,14 +55,14 @@ struct shadow_vmcs_field { u16 offset; }; static struct shadow_vmcs_field shadow_read_only_fields[] =3D { -#define SHADOW_FIELD_RO(x, y) { x, offsetof(struct vmcs12, y) }, +#define __SHADOW_FIELD_RO(x, y, c) { x, offsetof(struct vmcs12, y) }, #include "vmcs_shadow_fields.h" }; static int max_shadow_read_only_fields =3D ARRAY_SIZE(shadow_read_only_fields); =20 static struct shadow_vmcs_field shadow_read_write_fields[] =3D { -#define SHADOW_FIELD_RW(x, y) { x, offsetof(struct vmcs12, y) }, +#define __SHADOW_FIELD_RW(x, y, c) { x, offsetof(struct vmcs12, y) }, #include "vmcs_shadow_fields.h" }; static int max_shadow_read_write_fields =3D @@ -85,6 +85,17 @@ static void init_vmcs_shadow_fields(void) pr_err("Missing field from shadow_read_only_field %x\n", field + 1); =20 + switch (field) { +#define __SHADOW_FIELD_RO(x, y, c) \ + case x: \ + if (!(c)) \ + continue; \ + break; +#include "vmcs_shadow_fields.h" + default: + break; + } + clear_bit(field, vmx_vmread_bitmap); if (field & 1) #ifdef CONFIG_X86_64 @@ -110,24 +121,13 @@ static void init_vmcs_shadow_fields(void) field <=3D GUEST_TR_AR_BYTES, "Update vmcs12_write_any() to drop reserved bits from AR_BYTES"); =20 - /* - * PML and the preemption timer can be emulated, but the - * processor cannot vmwrite to fields that don't exist - * on bare metal. - */ switch (field) { - case GUEST_PML_INDEX: - if (!cpu_has_vmx_pml()) - continue; - break; - case VMX_PREEMPTION_TIMER_VALUE: - if (!cpu_has_vmx_preemption_timer()) - continue; - break; - case GUEST_INTR_STATUS: - if (!cpu_has_vmx_apicv()) - continue; +#define __SHADOW_FIELD_RW(x, y, c) \ + case x: \ + if (!(c)) \ + continue; \ break; +#include "vmcs_shadow_fields.h" default: break; } @@ -1633,8 +1633,8 @@ int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32= msr_index, u64 *pdata) /* * Copy the writable VMCS shadow fields back to the VMCS12, in case they h= ave * been modified by the L1 guest. Note, "writable" in this context means - * "writable by the guest", i.e. tagged SHADOW_FIELD_RW; the set of - * fields tagged SHADOW_FIELD_RO may or may not align with the "read-only" + * "writable by the guest", i.e. tagged __SHADOW_FIELD_RW; the set of + * fields tagged __SHADOW_FIELD_RO may or may not align with the "read-onl= y" * VM-exit information fields (which are actually writable if the vCPU is * configured to support "VMWRITE to any supported field in the VMCS"). */ @@ -1655,6 +1655,18 @@ static void copy_shadow_to_vmcs12(struct vcpu_vmx *v= mx) =20 for (i =3D 0; i < max_shadow_read_write_fields; i++) { field =3D shadow_read_write_fields[i]; + + switch (field.encoding) { +#define __SHADOW_FIELD_RW(x, y, c) \ + case x: \ + if (!(c)) \ + continue; \ + break; +#include "vmcs_shadow_fields.h" + default: + break; + } + val =3D __vmcs_readl(field.encoding); vmcs12_write_any(vmcs12, field.encoding, field.offset, val); } @@ -1689,6 +1701,23 @@ static void copy_vmcs12_to_shadow(struct vcpu_vmx *v= mx) for (q =3D 0; q < ARRAY_SIZE(fields); q++) { for (i =3D 0; i < max_fields[q]; i++) { field =3D fields[q][i]; + + switch (field.encoding) { +#define __SHADOW_FIELD_RO(x, y, c) \ + case x: \ + if (!(c)) \ + continue; \ + break; +#define __SHADOW_FIELD_RW(x, y, c) \ + case x: \ + if (!(c)) \ + continue; \ + break; +#include "vmcs_shadow_fields.h" + default: + break; + } + val =3D vmcs12_read_any(vmcs12, field.encoding, field.offset); __vmcs_writel(field.encoding, val); @@ -5997,9 +6026,10 @@ static int handle_vmread(struct kvm_vcpu *vcpu) static bool is_shadow_field_rw(unsigned long field) { switch (field) { -#define SHADOW_FIELD_RW(x, y) case x: +#define __SHADOW_FIELD_RW(x, y, c) \ + case x: \ + return c; #include "vmcs_shadow_fields.h" - return true; default: break; } @@ -6009,9 +6039,10 @@ static bool is_shadow_field_rw(unsigned long field) static bool is_shadow_field_ro(unsigned long field) { switch (field) { -#define SHADOW_FIELD_RO(x, y) case x: +#define __SHADOW_FIELD_RO(x, y, c) \ + case x: \ + return c; #include "vmcs_shadow_fields.h" - return true; default: break; } diff --git a/arch/x86/kvm/vmx/vmcs_shadow_fields.h b/arch/x86/kvm/vmx/vmcs_= shadow_fields.h index da338327c2b3..607945ada35f 100644 --- a/arch/x86/kvm/vmx/vmcs_shadow_fields.h +++ b/arch/x86/kvm/vmx/vmcs_shadow_fields.h @@ -1,14 +1,17 @@ -#if !defined(SHADOW_FIELD_RO) && !defined(SHADOW_FIELD_RW) +#if !defined(__SHADOW_FIELD_RO) && !defined(__SHADOW_FIELD_RW) BUILD_BUG_ON(1) #endif =20 -#ifndef SHADOW_FIELD_RO -#define SHADOW_FIELD_RO(x, y) +#ifndef __SHADOW_FIELD_RO +#define __SHADOW_FIELD_RO(x, y, c) #endif -#ifndef SHADOW_FIELD_RW -#define SHADOW_FIELD_RW(x, y) +#ifndef __SHADOW_FIELD_RW +#define __SHADOW_FIELD_RW(x, y, c) #endif =20 +#define SHADOW_FIELD_RO(x, y) __SHADOW_FIELD_RO(x, y, true) +#define SHADOW_FIELD_RW(x, y) __SHADOW_FIELD_RW(x, y, true) + /* * We do NOT shadow fields that are modified when L0 * traps and emulates any vmx instruction (e.g. VMPTRLD, @@ -32,8 +35,12 @@ BUILD_BUG_ON(1) */ =20 /* 16-bits */ -SHADOW_FIELD_RW(GUEST_INTR_STATUS, guest_intr_status) -SHADOW_FIELD_RW(GUEST_PML_INDEX, guest_pml_index) +__SHADOW_FIELD_RW(GUEST_INTR_STATUS, guest_intr_status, cpu_has_vmx_apicv(= )) +/* + * PML can be emulated, but the processor cannot vmwrite to the VMCS field + * GUEST_PML_INDEX that doesn't exist on bare metal. + */ +__SHADOW_FIELD_RW(GUEST_PML_INDEX, guest_pml_index, cpu_has_vmx_pml()) SHADOW_FIELD_RW(HOST_FS_SELECTOR, host_fs_selector) SHADOW_FIELD_RW(HOST_GS_SELECTOR, host_gs_selector) =20 @@ -41,9 +48,9 @@ SHADOW_FIELD_RW(HOST_GS_SELECTOR, host_gs_selector) SHADOW_FIELD_RO(VM_EXIT_REASON, vm_exit_reason) SHADOW_FIELD_RO(VM_EXIT_INTR_INFO, vm_exit_intr_info) SHADOW_FIELD_RO(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len) +SHADOW_FIELD_RO(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code) SHADOW_FIELD_RO(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field) SHADOW_FIELD_RO(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code) -SHADOW_FIELD_RO(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code) SHADOW_FIELD_RO(GUEST_CS_AR_BYTES, guest_cs_ar_bytes) SHADOW_FIELD_RO(GUEST_SS_AR_BYTES, guest_ss_ar_bytes) SHADOW_FIELD_RW(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control) @@ -54,7 +61,12 @@ SHADOW_FIELD_RW(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_= info_field) SHADOW_FIELD_RW(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len) SHADOW_FIELD_RW(TPR_THRESHOLD, tpr_threshold) SHADOW_FIELD_RW(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info) -SHADOW_FIELD_RW(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value) +/* + * The preemption timer can be emulated, but the processor cannot vmwrite = to + * the VMCS field VMX_PREEMPTION_TIMER_VALUE that doesn't exist on bare me= tal. + */ +__SHADOW_FIELD_RW(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value, + cpu_has_vmx_preemption_timer()) =20 /* Natural width */ SHADOW_FIELD_RO(EXIT_QUALIFICATION, exit_qualification) @@ -74,10 +86,13 @@ SHADOW_FIELD_RW(HOST_GS_BASE, host_gs_base) /* 64-bit */ SHADOW_FIELD_RO(GUEST_PHYSICAL_ADDRESS, guest_physical_address) SHADOW_FIELD_RO(GUEST_PHYSICAL_ADDRESS_HIGH, guest_physical_address) -SHADOW_FIELD_RO(ORIGINAL_EVENT_DATA, original_event_data) -SHADOW_FIELD_RO(ORIGINAL_EVENT_DATA_HIGH, original_event_data) -SHADOW_FIELD_RW(INJECTED_EVENT_DATA, injected_event_data) -SHADOW_FIELD_RW(INJECTED_EVENT_DATA_HIGH, injected_event_data) +__SHADOW_FIELD_RO(ORIGINAL_EVENT_DATA, original_event_data, cpu_has_vmx_fr= ed()) +__SHADOW_FIELD_RO(ORIGINAL_EVENT_DATA_HIGH, original_event_data, cpu_has_v= mx_fred()) +__SHADOW_FIELD_RW(INJECTED_EVENT_DATA, injected_event_data, cpu_has_vmx_fr= ed()) +__SHADOW_FIELD_RW(INJECTED_EVENT_DATA_HIGH, injected_event_data, cpu_has_v= mx_fred()) =20 #undef SHADOW_FIELD_RO #undef SHADOW_FIELD_RW + +#undef __SHADOW_FIELD_RO +#undef __SHADOW_FIELD_RW --=20 2.51.0 From nobody Fri Oct 3 14:29:30 2025 Received: from mail.zytor.com (terminus.zytor.com [198.137.202.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8299F32C323; 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charset="utf-8" From: Xin Li Allow nVMX FRED controls as nested FRED support is in place. Signed-off-by: Xin Li Signed-off-by: Xin Li (Intel) Tested-by: Shan Kang Tested-by: Xuelian Guo --- Change in v5: * Add TB from Xuelian Guo. --- arch/x86/kvm/vmx/nested.c | 5 +++-- arch/x86/kvm/vmx/vmx.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 266115525b9e..0b266e95db60 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -7436,7 +7436,8 @@ static void nested_vmx_setup_exit_ctls(struct vmcs_co= nfig *vmcs_conf, * advertise any feature in it to nVMX until its nVMX support * is ready. */ - msrs->secondary_exit_ctls &=3D 0; + msrs->secondary_exit_ctls &=3D SECONDARY_VM_EXIT_SAVE_IA32_FRED | + SECONDARY_VM_EXIT_LOAD_IA32_FRED; } } =20 @@ -7452,7 +7453,7 @@ static void nested_vmx_setup_entry_ctls(struct vmcs_c= onfig *vmcs_conf, VM_ENTRY_IA32E_MODE | #endif VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS | - VM_ENTRY_LOAD_CET_STATE; + VM_ENTRY_LOAD_CET_STATE | VM_ENTRY_LOAD_IA32_FRED; msrs->entry_ctls_high |=3D (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index c280e4cd4485..8d61b9b8bd9b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7964,6 +7964,7 @@ static void nested_vmx_cr_fixed1_bits_update(struct k= vm_vcpu *vcpu) =20 entry =3D kvm_find_cpuid_entry_index(vcpu, 0x7, 1); cr4_fixed1_update(X86_CR4_LAM_SUP, eax, feature_bit(LAM)); + cr4_fixed1_update(X86_CR4_FRED, eax, feature_bit(FRED)); =20 #undef cr4_fixed1_update } --=20 2.51.0