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Now change the compatibility due to few driver changes (PMU bit changes for each WDT instance and Clocks) for WDT found in FSD SoC. Signed-off-by: Varada Pavani --- .../devicetree/bindings/watchdog/samsung-wdt.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/= Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index d175ae968336..db2009654fe4 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -27,10 +27,7 @@ properties: - samsung,exynos850-wdt # for Exynos850 - samsung,exynosautov9-wdt # for Exynosautov9 - samsung,exynosautov920-wdt # for Exynosautov920 - - items: - - enum: - - tesla,fsd-wdt - - const: samsung,exynos7-wdt + - tesla,fsd-wdt =20 reg: maxItems: 1 @@ -79,6 +76,7 @@ allOf: - samsung,exynos850-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt + - tesla,fsd-wdt then: required: - samsung,syscon-phandle @@ -91,6 +89,7 @@ allOf: - samsung,exynos850-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt + - tesla,fsd-wdt then: properties: clocks: @@ -102,7 +101,7 @@ allOf: - const: watchdog - const: watchdog_src samsung,cluster-index: - enum: [0, 1] + enum: [0, 1, 2] required: - samsung,cluster-index else: --=20 2.49.0 From nobody Fri Oct 3 14:29:00 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BD7C31E114 for ; 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Fri, 29 Aug 2025 13:57:09 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.92]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4cD0FJ70Gjz6B9m5; Fri, 29 Aug 2025 13:57:08 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250829135708epcas5p1b62d44f8a712b1c865fd82d26e89896f~gQXWnylAw0508305083epcas5p1J; Fri, 29 Aug 2025 13:57:08 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250829135706epsmtip25ca5f73ca9f7b0fde2d6f80c634f7b01~gQXVB7a6l1416014160epsmtip23; Fri, 29 Aug 2025 13:57:06 +0000 (GMT) From: Varada Pavani To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: aswani.reddy@samsung.com, gost.dev@samsung.com, Varada Pavani Subject: [PATCH 2/2] arm64: dts: fsd: Fix Clock handle for WDT Date: Fri, 29 Aug 2025 19:26:43 +0530 Message-ID: <20250829135643.105406-3-v.pavani@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250829135643.105406-1-v.pavani@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250829135708epcas5p1b62d44f8a712b1c865fd82d26e89896f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250829135708epcas5p1b62d44f8a712b1c865fd82d26e89896f References: <20250829135643.105406-1-v.pavani@samsung.com> FSD SoC WDT has few changes when compared to exynos7 interms of Clocks, PMU register bits for each cluster. So use "tesla,fsd-wdt" compatibility for using correct driver data. FSD supports 2 Clocks for WDT (PCLK and CLK). - use fin_pll source Clock for all timer related calculations. - use bus Clock (IMEM_WDT0_IPCLKPORT_PCLK) to gate/ungate the register interface. Update both as per WDT UM. Signed-off-by: Varada Pavani --- arch/arm64/boot/dts/tesla/fsd.dtsi | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla= /fsd.dtsi index 690b4ed9c29b..ff031a630f10 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -624,30 +624,36 @@ pmu_system_controller: system-controller@11400000 { }; =20 watchdog_0: watchdog@100a0000 { - compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; + compatible =3D "tesla,fsd-wdt"; reg =3D <0x0 0x100a0000 0x0 0x100>; interrupts =3D ; samsung,syscon-phandle =3D <&pmu_system_controller>; - clocks =3D <&fin_pll>; - clock-names =3D "watchdog"; + clocks =3D <&clock_imem IMEM_WDT0_IPCLKPORT_PCLK>, + <&fin_pll>; + clock-names =3D "watchdog", "watchdog_src"; + samsung,cluster-index =3D <0>; }; =20 watchdog_1: watchdog@100b0000 { - compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; + compatible =3D "tesla,fsd-wdt"; reg =3D <0x0 0x100b0000 0x0 0x100>; interrupts =3D ; samsung,syscon-phandle =3D <&pmu_system_controller>; - clocks =3D <&fin_pll>; - clock-names =3D "watchdog"; + clocks =3D <&clock_imem IMEM_WDT1_IPCLKPORT_PCLK>, + <&fin_pll>; + clock-names =3D "watchdog", "watchdog_src"; + samsung,cluster-index =3D <1>; }; =20 watchdog_2: watchdog@100c0000 { - compatible =3D "tesla,fsd-wdt", "samsung,exynos7-wdt"; + compatible =3D "tesla,fsd-wdt"; reg =3D <0x0 0x100c0000 0x0 0x100>; interrupts =3D ; samsung,syscon-phandle =3D <&pmu_system_controller>; - clocks =3D <&fin_pll>; - clock-names =3D "watchdog"; + clocks =3D <&clock_imem IMEM_WDT2_IPCLKPORT_PCLK>, + <&fin_pll>; + clock-names =3D "watchdog", "watchdog_src"; + samsung,cluster-index =3D <2>; }; =20 pwm_0: pwm@14100000 { --=20 2.49.0