From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9166C2E7BDA; Fri, 29 Aug 2025 13:11:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473093; cv=none; b=FYgqEzEZ1UPuiNTyE1SeyFwRqFy6VmlY9tmYQGd26eRrMqDcAB7cjW9AvdQ6CI72AQ1WD/mk6uW+nF8kaY/scLTt/JaWUSz0hqJ9R7nXnrdtke0qrZFxc6GcwsfrE7ScYSJfL6s8IKlDtYsF5axC12NYH0EIKMjWwQ072PBN5dg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473093; c=relaxed/simple; bh=3/KqAj6SPENBeMHK838Xzt1epcWPtBMI4CsY0Xu62D0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=AGeiiozPumfWrbbdtFl8IhQ7XtOjj3AqBUSQU8ov1OC4kZAMhrntvmqeptNPonwVNLsoPDEfaEqTs5drRyuCg4QCnXMXnbcpfXCnnTyQQSgwcsng6r3MRLxznCqKSPqZJt2OhZZY3GqLCZ8wdrS2/0tvGGHN4s+lHy8xB0FL8e8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kacLKW3j; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kacLKW3j" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473091; x=1788009091; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3/KqAj6SPENBeMHK838Xzt1epcWPtBMI4CsY0Xu62D0=; b=kacLKW3jfIUaWx3HtbOo9myspSHo3rUGtEFIpNyqX+zCqqLXdtAxL50V O0uZ1w/S8rMl+ihCYJsd5DsCx+b+xNpmkDKUatcj09JUl76shnywFoOPK jAYcwXVSSXZKc6ntcCidsdzvwazBiHnCl4mz5yzk0tTLqMtZJ+2zRbNUi 0QgNNNNGHWGx+vPblyRQ/x9RjFBCgkk5LVD2NZ02GI+RMravmgTQbzXOZ vKXr5AUWqOmlVXSb93mPqrVNGqjFDYMpNqdnxhj4VPfmGONIoSxWx7s56 uYTXkJBXWWVqOFIM6AVmXG7qhleFVpDdvEHso5mcfWAw+1hHub4+QgV4A g==; X-CSE-ConnectionGUID: p3l2oRxnRnGLBeuHrj1DVQ== X-CSE-MsgGUID: l2ICkCFyT6yv06QtidcoxQ== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="58687483" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="58687483" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:31 -0700 X-CSE-ConnectionGUID: m1i8cZgXRqiu9WFN10Odcg== X-CSE-MsgGUID: obssSdZoRrmCqw2eLD7bFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="174550835" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:29 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 01/24] m68k/PCI: Use pci_enable_resources() in pcibios_enable_device() Date: Fri, 29 Aug 2025 16:10:50 +0300 Message-Id: <20250829131113.36754-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable m68k has a resource enable (check) loop in its pcibios_enable_device() which for some reason differs from pci_enable_resources(). This could lead to inconsistencies in behavior, especially now as pci_enable_resources() and the bridge window resource flags behavior are going to be altered by upcoming changes. The check for !r->start && r->end is already covered by the more generic checks done in pci_enable_resources(). The entire pcibios_enable_device() suspiciously looks copy-paste from some other arch as also indicated by the preceding comment. However, it also enables PCI_COMMAND_IO | PCI_COMMAND_MEMORY always for bridges. It is not clear why that is being done as the commit e93a6bbeb5a5 ("m68k: common PCI support definitions and code") introducing this code states "Nothing specific to any PCI implementation in any m68k class CPU hardware yet". Replace the resource enable loop with a call to pci_enable_resources() and adjust the Command Register afterwards as it's unclear if that is necessary or not so keep it for now. Signed-off-by: Ilpo J=C3=A4rvinen --- arch/m68k/kernel/pcibios.c | 39 +++++++++++--------------------------- 1 file changed, 11 insertions(+), 28 deletions(-) diff --git a/arch/m68k/kernel/pcibios.c b/arch/m68k/kernel/pcibios.c index 9504eb19d73a..e6ab3f9ff5d8 100644 --- a/arch/m68k/kernel/pcibios.c +++ b/arch/m68k/kernel/pcibios.c @@ -44,41 +44,24 @@ resource_size_t pcibios_align_resource(void *data, cons= t struct resource *res, */ int pcibios_enable_device(struct pci_dev *dev, int mask) { - struct resource *r; u16 cmd, newcmd; - int idx; + int ret; =20 - pci_read_config_word(dev, PCI_COMMAND, &cmd); - newcmd =3D cmd; - - for (idx =3D 0; idx < 6; idx++) { - /* Only set up the requested stuff */ - if (!(mask & (1 << idx))) - continue; - - r =3D dev->resource + idx; - if (!r->start && r->end) { - pr_err("PCI: Device %s not available because of resource collisions\n", - pci_name(dev)); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - newcmd |=3D PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - newcmd |=3D PCI_COMMAND_MEMORY; - } + ret =3D pci_enable_resources(dev, mask); + if (ret < 0) + return ret; =20 /* * Bridges (eg, cardbus bridges) need to be fully enabled */ - if ((dev->class >> 16) =3D=3D PCI_BASE_CLASS_BRIDGE) + if ((dev->class >> 16) =3D=3D PCI_BASE_CLASS_BRIDGE) { + pci_read_config_word(dev, PCI_COMMAND, &cmd); newcmd |=3D PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - - - if (newcmd !=3D cmd) { - pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n", - pci_name(dev), cmd, newcmd); - pci_write_config_word(dev, PCI_COMMAND, newcmd); + if (newcmd !=3D cmd) { + pr_info("PCI: enabling bridge %s (0x%04x -> 0x%04x)\n", + pci_name(dev), cmd, newcmd); + pci_write_config_word(dev, PCI_COMMAND, newcmd); + } } return 0; } --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ED002F83B7; Fri, 29 Aug 2025 13:11:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="58687488" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="58687488" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:38 -0700 X-CSE-ConnectionGUID: JnLYhS0yS7OPZkWUIsP1cw== X-CSE-MsgGUID: dSv00wODTY6Hb56C5tdNNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="174550837" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:36 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 02/24] sparc/PCI: Remove pcibios_enable_device() as they do nothing extra Date: Fri, 29 Aug 2025 16:10:51 +0300 Message-Id: <20250829131113.36754-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Under arch/sparc/ there are multiple copies of pcibios_enable_device() but none of those seem to do anything extra beyond what pci_enable_resources() is supposed to do. These functions could lead to inconsistencies in behavior, especially now as pci_enable_resources() and the bridge window resource flags behavior are going to be altered by upcoming changes. Remove all pcibios_enable_device() from arch/sparc/ so that PCI core can simply call into pci_enable_resources() instead using its __weak version of pcibios_enable_device(). Signed-off-by: Ilpo J=C3=A4rvinen --- arch/sparc/kernel/leon_pci.c | 27 --------------------------- arch/sparc/kernel/pci.c | 27 --------------------------- arch/sparc/kernel/pcic.c | 27 --------------------------- 3 files changed, 81 deletions(-) diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c index 8de6646e9ce8..10934dfa987a 100644 --- a/arch/sparc/kernel/leon_pci.c +++ b/arch/sparc/kernel/leon_pci.c @@ -60,30 +60,3 @@ void leon_pci_init(struct platform_device *ofdev, struct= leon_pci_info *info) pci_assign_unassigned_resources(); pci_bus_add_devices(root_bus); } - -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - struct resource *res; - u16 cmd, oldcmd; - int i; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - oldcmd =3D cmd; - - pci_dev_for_each_resource(dev, res, i) { - /* Only set up the requested stuff */ - if (!(mask & (1<flags & IORESOURCE_IO) - cmd |=3D PCI_COMMAND_IO; - if (res->flags & IORESOURCE_MEM) - cmd |=3D PCI_COMMAND_MEMORY; - } - - if (cmd !=3D oldcmd) { - pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index ddac216a2aff..a9448088e762 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -722,33 +722,6 @@ struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *= pbm, return bus; } =20 -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - struct resource *res; - u16 cmd, oldcmd; - int i; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - oldcmd =3D cmd; - - pci_dev_for_each_resource(dev, res, i) { - /* Only set up the requested stuff */ - if (!(mask & (1<flags & IORESOURCE_IO) - cmd |=3D PCI_COMMAND_IO; - if (res->flags & IORESOURCE_MEM) - cmd |=3D PCI_COMMAND_MEMORY; - } - - if (cmd !=3D oldcmd) { - pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - /* Platform support for /proc/bus/pci/X/Y mmap()s. */ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vm= a) { diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c index 25fe0a061732..3d54ad5656a4 100644 --- a/arch/sparc/kernel/pcic.c +++ b/arch/sparc/kernel/pcic.c @@ -641,33 +641,6 @@ void pcibios_fixup_bus(struct pci_bus *bus) } } =20 -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - struct resource *res; - u16 cmd, oldcmd; - int i; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - oldcmd =3D cmd; - - pci_dev_for_each_resource(dev, res, i) { - /* Only set up the requested stuff */ - if (!(mask & (1<flags & IORESOURCE_IO) - cmd |=3D PCI_COMMAND_IO; - if (res->flags & IORESOURCE_MEM) - cmd |=3D PCI_COMMAND_MEMORY; - } - - if (cmd !=3D oldcmd) { - pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - /* Makes compiler happy */ static volatile int pcic_timer_dummy; =20 --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14CF72EBDF4; Fri, 29 Aug 2025 13:11:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="58687493" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:46 -0700 X-CSE-ConnectionGUID: g8Lt4dy7QYOk/04BYPW2fw== X-CSE-MsgGUID: pCvGApl+QqW81c5iGZ24Og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="174550855" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:43 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Thomas Bogendoerfer Subject: [PATCH v2 03/24] MIPS: PCI: Use pci_enable_resources() Date: Fri, 29 Aug 2025 16:10:52 +0300 Message-Id: <20250829131113.36754-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci-legacy.c under MIPS has a copy of pci_enable_resources() named as pcibios_enable_resources(). Having own copy of same functionality could lead to inconsistencies in behavior, especially now as pci_enable_resources() and the bridge window resource flags behavior are going to be altered by upcoming changes. The check for !r->start && r->end is already covered by the more generic checks done in pci_enable_resources(). Call pci_enable_resources() from MIPS's pcibios_enable_device() and remove pcibios_enable_resources(). Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Thomas Bogendoerfer --- arch/mips/pci/pci-legacy.c | 38 ++------------------------------------ 1 file changed, 2 insertions(+), 36 deletions(-) diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c index 66898fd182dc..d04b7c1294b6 100644 --- a/arch/mips/pci/pci-legacy.c +++ b/arch/mips/pci/pci-legacy.c @@ -249,45 +249,11 @@ static int __init pcibios_init(void) =20 subsys_initcall(pcibios_init); =20 -static int pcibios_enable_resources(struct pci_dev *dev, int mask) -{ - u16 cmd, old_cmd; - int idx; - struct resource *r; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd =3D cmd; - pci_dev_for_each_resource(dev, r, idx) { - /* Only set up the requested stuff */ - if (!(mask & (1<flags & (IORESOURCE_IO | IORESOURCE_MEM))) - continue; - if ((idx =3D=3D PCI_ROM_RESOURCE) && - (!(r->flags & IORESOURCE_ROM_ENABLE))) - continue; - if (!r->start && r->end) { - pci_err(dev, - "can't enable device: resource collisions\n"); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |=3D PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |=3D PCI_COMMAND_MEMORY; - } - if (cmd !=3D old_cmd) { - pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - int pcibios_enable_device(struct pci_dev *dev, int mask) { - int err =3D pcibios_enable_resources(dev, mask); + int err; =20 + err =3D pci_enable_resources(dev, mask); if (err < 0) return err; =20 --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A3102EBDF4; Fri, 29 Aug 2025 13:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473116; cv=none; b=Dsyx8uhiTuPmgJKsNLPPUdS9tZpNEkeBbpnj+bjZYPBdJ4n+aisT8uJFflji0BOASP9mhhROLqPs7w1/XjxPzE+DUX2nbg35DTzFBOBuP8YsXU/5zL5Z3DPUvVb62fmrj1O/3tCFcGJdMc8PtyxKQLdQfn5uc9GLxp5ofw+EV+4= ARC-Message-Signature: i=1; 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d="scan'208";a="174550876" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:51 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 04/24] PCI: Move find_bus_resource_of_type() earlier Date: Fri, 29 Aug 2025 16:10:53 +0300 Message-Id: <20250829131113.36754-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Move find_bus_resource_of_type() earlier in setup-bus.c to be able to call it in upcoming changes. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 56 ++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index def29506700e..4097d8703b8f 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -140,6 +140,34 @@ static void restore_dev_resource(struct pci_dev_resour= ce *dev_res) res->flags =3D dev_res->flags; } =20 +/* + * Helper function for sizing routines. Assigned resources have non-NULL + * parent resource. + * + * Return first unassigned resource of the correct type. If there is none, + * return first assigned resource of the correct type. If none of the + * above, return NULL. + * + * Returning an assigned resource of the correct type allows the caller to + * distinguish between already assigned and no resource of the correct typ= e. + */ +static struct resource *find_bus_resource_of_type(struct pci_bus *bus, + unsigned long type_mask, + unsigned long type) +{ + struct resource *r, *r_assigned =3D NULL; + + pci_bus_for_each_resource(bus, r) { + if (r =3D=3D &ioport_resource || r =3D=3D &iomem_resource) + continue; + if (r && (r->flags & type_mask) =3D=3D type && !r->parent) + return r; + if (r && (r->flags & type_mask) =3D=3D type && !r_assigned) + r_assigned =3D r; + } + return r_assigned; +} + static bool pdev_resources_assignable(struct pci_dev *dev) { u16 class =3D dev->class >> 8, command; @@ -876,34 +904,6 @@ static void pci_bridge_check_ranges(struct pci_bus *bu= s) } } =20 -/* - * Helper function for sizing routines. Assigned resources have non-NULL - * parent resource. - * - * Return first unassigned resource of the correct type. If there is none, - * return first assigned resource of the correct type. If none of the - * above, return NULL. - * - * Returning an assigned resource of the correct type allows the caller to - * distinguish between already assigned and no resource of the correct typ= e. - */ -static struct resource *find_bus_resource_of_type(struct pci_bus *bus, - unsigned long type_mask, - unsigned long type) -{ - struct resource *r, *r_assigned =3D NULL; - - pci_bus_for_each_resource(bus, r) { - if (r =3D=3D &ioport_resource || r =3D=3D &iomem_resource) - continue; - if (r && (r->flags & type_mask) =3D=3D type && !r->parent) - return r; - if (r && (r->flags & type_mask) =3D=3D type && !r_assigned) - r_assigned =3D r; - } - return r_assigned; -} - static resource_size_t calculate_iosize(resource_size_t size, resource_size_t min_size, resource_size_t size1, --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4667D31A061; Fri, 29 Aug 2025 13:12:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473122; cv=none; b=V1HISAEuurtYiRE6lezUl/wi2Ec4NqLjHo6jdSelvAx/S3hyczh5ug/yZ9wklFahTM6qnILNg8E0zAD58UPL2aeio6Eetu/jROHWIha9xnAhwbq1y/DvVdkMmVh++bykVfoESPRmmk6u5tEb9Po7xptEeM5YU0Wsy1Y8faOMgCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473122; c=relaxed/simple; bh=rM82OhwHo/iGvjxvD6YHBNxc60cvUbkFuOCHsZoW6bo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=SXQOAwse3EzId3LFqciRNwfWMxN3syrd4i6X0QHnz0LMCa27FKKehow/GCD6mbToWWk1TlKPLZCe2ypB18YxGtNQ6Pfb3IUK9JiKrxvPae3yTjj+Zqfz2Q1gYLAAnyTk/eKM8AAkD+vOZQyGa0C9asD6JeEoy18EP4DMVv2bzWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ESWKBIeA; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ESWKBIeA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473121; x=1788009121; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rM82OhwHo/iGvjxvD6YHBNxc60cvUbkFuOCHsZoW6bo=; b=ESWKBIeAVc27ud5ysGmkEBzNfVSvxebk5yIcRp0VcP+JOD2mnApwIzIb 90wlEtFqk27GLjz9i9GRCaAGNd/Us/vKC5M7iaXONrTFWkKr+3+hn0I0d FmEMhjTgToz+FE+2g9zflLL5jQvvyt94Nub+HWIQn+iLfLStB2AQt+zDd KjXr38C4itWyNG/RGpI2DFADIPa5U4OLnfZgUFxpHQb46AlvpGro7Yp56 VsMtbFCszJrEvqxIUv6eokp4X7gKO8mdOoUv3p5jJ/rmELdgK9AVhPiFX RmWLc8U6THHvZvokwd6cL4HOcsHqCMJvnXh1+i4xZHNY6HaapDCCV2y74 Q==; X-CSE-ConnectionGUID: A8qww1a2QAexn7zP7KXv5A== X-CSE-MsgGUID: iPVoOP3mT/CydS2G8EJq0Q== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="62402913" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="62402913" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:01 -0700 X-CSE-ConnectionGUID: zVL1JTMPTiO/sF4Viilkow== X-CSE-MsgGUID: 9k2+iqqbRDqRFeb0dmu83A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="169946724" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:11:59 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 05/24] PCI: Refactor find_bus_resource_of_type() logic checks Date: Fri, 29 Aug 2025 16:10:54 +0300 Message-Id: <20250829131113.36754-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Reorder the logic checks in find_bus_resource_of_type() to simplify them. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 4097d8703b8f..c5fc4e2825be 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -158,11 +158,15 @@ static struct resource *find_bus_resource_of_type(str= uct pci_bus *bus, struct resource *r, *r_assigned =3D NULL; =20 pci_bus_for_each_resource(bus, r) { - if (r =3D=3D &ioport_resource || r =3D=3D &iomem_resource) + if (!r || r =3D=3D &ioport_resource || r =3D=3D &iomem_resource) continue; - if (r && (r->flags & type_mask) =3D=3D type && !r->parent) + + if ((r->flags & type_mask) !=3D type) + continue; + + if (!r->parent) return r; - if (r && (r->flags & type_mask) =3D=3D type && !r_assigned) + if (!r_assigned) r_assigned =3D r; } return r_assigned; --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AD382F49F2; Fri, 29 Aug 2025 13:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473130; cv=none; b=UPxYphTT77sshNMtWB3f8SZm8j1d3PtHhMZPFHd5GMn4wkzNtJ+6lNM53iD6oY3W0B+3GGWrwePdI6JyFIVFKOOI8qo5XjjgqhJKLnIyCujITgAx/5yfRGDvlsQzynBRASPRMpVa3SoY+HWRWz7BQOWTHV7QlFsKufcx70DvhmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473130; c=relaxed/simple; bh=I3FGPEn/i7AK7bt+/cpWmKyssU10lHLDyKd8Od9xfOg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=qN0pM2dn9qr2F/39XQ2wzNN7gNPKwwrPcFqUc7On5PvV56pIjWmScUubBDRmZCsU7BFHWHo3NZiieuwNnXtB+xnAE9YKFOGdeijfVh0II3Rcl37SsxOionY365uNnxpow89dlnRi3VIGb+dnyj8w9o6uPFB2NQ9AcfSQiLpSBfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iwsuzt2U; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iwsuzt2U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473129; x=1788009129; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I3FGPEn/i7AK7bt+/cpWmKyssU10lHLDyKd8Od9xfOg=; b=iwsuzt2UNPUu4Pb0xFgbi9dfi2PVFGglwU/BGzxBBV8W4ZJEqvnr6Sho unKdGK3+f5AbFDbuByy+iY7v4mblYIVLv78qeyXiPghv6kdsBYogVVXPP 0ozY7c/oZCSq90Zsf/5Q6HwiFRKj1DABWdHMs1h2qImGyKbYhFxUQrnP/ 3tzjaKzy2IpguzMRIJj6AqveVLpE0P4XrchpMuZrw2rNdzMFuhXFwgYg6 pUe9PJj37JQzo3lhqnLEFh2xWLCjzM1JHVRJyFQ1Ej+wXanEq0n/9/yPH tRPMbuH2hVp8hgbUHN3oMGkEnEeNHHdxYKtDhstUZ8DSII7sCv1fhzXJs g==; X-CSE-ConnectionGUID: /PoSBU8gTue6rQXqa86Few== X-CSE-MsgGUID: 4bwW+RwhSpCIEmqBZYmA/Q== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="62402918" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="62402918" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:08 -0700 X-CSE-ConnectionGUID: w7aRY5S4Q3ay3f/yvzLc8Q== X-CSE-MsgGUID: 5kxbP4nUSdaI/FWDyTcp8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="169946727" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:07 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 06/24] PCI: Always claim bridge window before its setup Date: Fri, 29 Aug 2025 16:10:55 +0300 Message-Id: <20250829131113.36754-7-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable When the claim of a resource fails for the full range in pci_claim_bridge_resource(), clipping the resource to a smaller size is attempted. If clipping is successful, the new bridge window is programmed and only as the last step the code attempts to claim the resource again. The order of the last two steps is slightly illogical and inconsistent with the assignment call chains. If claiming the bridge window after clipping fails, the bridge window that was set up is left in place. Rework the logic such that the bridge window is claimed before calling the relevant bridge setup function. This make the behavior consistent with resource fitting call chains that always assign the bridge window before programming it. If claiming the bridge window fails, the clipped bridge window is no longer set up but pci_claim_bridge_resource() returns without writing the bridge window at all. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index c5fc4e2825be..b477f68b236c 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -857,9 +857,16 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, = int i) if ((bridge->class >> 8) !=3D PCI_CLASS_BRIDGE_PCI) return 0; =20 + if (i > PCI_BRIDGE_PREF_MEM_WINDOW) + return -EINVAL; + + /* Try to clip the resource and claim the smaller window */ if (!pci_bus_clip_resource(bridge, i)) return -EINVAL; /* Clipping didn't change anything */ =20 + if (!pci_claim_resource(bridge, i)) + return -EINVAL; + switch (i) { case PCI_BRIDGE_IO_WINDOW: pci_setup_bridge_io(bridge); @@ -874,10 +881,7 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, = int i) return -EINVAL; } =20 - if (pci_claim_resource(bridge, i) =3D=3D 0) - return 0; /* Claimed a smaller window */ - - return -EINVAL; + return 0; } =20 /* --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4AFD31A563; Fri, 29 Aug 2025 13:12:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473137; cv=none; b=BzdzjpTCG9Z9F68eJzR3xR806qlrhDlHVfGMGU3DBq8KL5B1p5vzK7hVs/8LBXHiOnEwGTYmmAq5A2HKmjj/ptXQagrHWkwSUHaj8cPq4tGfT+ZyyL4pmwzTRc3vEQ8HSngPgg4ToNnJSpJdUsIS+bDhSO8jVHQ1pf0+7QnfRcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473137; c=relaxed/simple; bh=o67wBBtDb3ifV2Ku79cWn/DFcDwLVFbBIY5IplZQPDU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=JN3uwhNVsmOfG6k03vdCOCWQhrBNiiJrkiExd28kCx232C7pd1YI08Twi08OtfS9hV7OhlGYb9jQRMp9754r7fJH2mCKwu+V8hoNZBfzVKzMaKN2Hqzk5H6PGLqAeo8OGCkcMVtLcNxu8WHoJIt4MwdrG2hiFBWcdxg7NY8Y2tY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WF01qQwG; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WF01qQwG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473136; x=1788009136; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o67wBBtDb3ifV2Ku79cWn/DFcDwLVFbBIY5IplZQPDU=; b=WF01qQwGR/+hBrlQP7Wra/5DC57jydi98bWTkSxxxTNSago6Rsc66My9 BwdY9jsWCbsdl1tBuUnUN7A0mJMC5WANbeRvcIEUt5Ro2BBLdbdjzFR1X rnrri6HN8fAyqqB+YFzix3rYrJCraUyyanHq8q4z7Xuktj4zQDbeN1jJS CmaDmxKWznHsF2sJjSjAXfkAspqLySUvtLt3lptTctcFIP4nciFuj+Kur 8/cSci5uVwfRyZF4E0lSdR4JM9av5AZOAVFzCZYV8tFWfCN0CDLfqaJyv SzOMztciuTBGQyFC4py557G16OHVTVYN9+eo0jWSSjNPXSsWOhjTwuEb2 A==; X-CSE-ConnectionGUID: BVnD9JH8Q6+pncC6ARpe+A== X-CSE-MsgGUID: OpqDwbyNQf2WUugG99o25w== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="62402929" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="62402929" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:15 -0700 X-CSE-ConnectionGUID: 9KO3Y+OyT+Gc6Zg9wJFMZQ== X-CSE-MsgGUID: f6S0P4YKTD+3+vf5XljP4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="169946732" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:14 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 07/24] PCI: Disable non-claimed bridge window Date: Fri, 29 Aug 2025 16:10:56 +0300 Message-Id: <20250829131113.36754-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable If clipping or claiming the bridge window fails, the bridge window is left in a state that does not match the kernel's view on what the bridge window is. Disable the bridge window by writing the magic disable value into the Base and Limit Registers if clipping or claiming failed. To detect if claiming the resource was successful, add res->parent checks into the bridge setup functions. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index b477f68b236c..6bdc1af887da 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -660,7 +660,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[0]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->flags & IORESOURCE_IO) { + if (res->parent && res->flags & IORESOURCE_IO) { /* * The IO resource is allocated a range twice as large as it * would normally need. This allows us to set both IO regs. @@ -674,7 +674,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[1]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->flags & IORESOURCE_IO) { + if (res->parent && res->flags & IORESOURCE_IO) { pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, region.start); @@ -684,7 +684,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[2]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->flags & IORESOURCE_MEM) { + if (res->parent && res->flags & IORESOURCE_MEM) { pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, region.start); @@ -694,7 +694,7 @@ void pci_setup_cardbus(struct pci_bus *bus) =20 res =3D bus->resource[3]; pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->flags & IORESOURCE_MEM) { + if (res->parent && res->flags & IORESOURCE_MEM) { pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, region.start); @@ -735,7 +735,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge) res =3D &bridge->resource[PCI_BRIDGE_IO_WINDOW]; res_name =3D pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW); pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->flags & IORESOURCE_IO) { + if (res->parent && res->flags & IORESOURCE_IO) { pci_read_config_word(bridge, PCI_IO_BASE, &l); io_base_lo =3D (region.start >> 8) & io_mask; io_limit_lo =3D (region.end >> 8) & io_mask; @@ -767,7 +767,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridg= e) res =3D &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; res_name =3D pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW); pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->flags & IORESOURCE_MEM) { + if (res->parent && res->flags & IORESOURCE_MEM) { l =3D (region.start >> 16) & 0xfff0; l |=3D region.end & 0xfff00000; pci_info(bridge, " %s %pR\n", res_name, res); @@ -796,7 +796,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *= bridge) res =3D &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; res_name =3D pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW); pcibios_resource_to_bus(bridge->bus, ®ion, res); - if (res->flags & IORESOURCE_PREFETCH) { + if (res->parent && res->flags & IORESOURCE_PREFETCH) { l =3D (region.start >> 16) & 0xfff0; l |=3D region.end & 0xfff00000; if (res->flags & IORESOURCE_MEM_64) { @@ -848,6 +848,8 @@ static void pci_setup_bridge(struct pci_bus *bus) =20 int pci_claim_bridge_resource(struct pci_dev *bridge, int i) { + int ret =3D -EINVAL; + if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) return 0; =20 @@ -861,11 +863,8 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, = int i) return -EINVAL; =20 /* Try to clip the resource and claim the smaller window */ - if (!pci_bus_clip_resource(bridge, i)) - return -EINVAL; /* Clipping didn't change anything */ - - if (!pci_claim_resource(bridge, i)) - return -EINVAL; + if (pci_bus_clip_resource(bridge, i)) + ret =3D pci_claim_resource(bridge, i); =20 switch (i) { case PCI_BRIDGE_IO_WINDOW: @@ -881,7 +880,7 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, i= nt i) return -EINVAL; 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X-CSE-ConnectionGUID: E9RDQISpQ6eCXUZ2keFpIg== X-CSE-MsgGUID: Tz07TQGJSvmMG76PTY1m7w== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="62402942" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="62402942" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:23 -0700 X-CSE-ConnectionGUID: gsmww7FNQYaqAeh/lNoqzw== X-CSE-MsgGUID: DsXhnaoSQgGCfeKPIVYyOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="169946736" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:21 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 08/24] PCI: Use pci_release_resource() instead of release_resource() Date: Fri, 29 Aug 2025 16:10:57 +0300 Message-Id: <20250829131113.36754-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable A few places in setup-bus.c call release_resource() directly and end up duplicating functionality from pci_release_resource() such as parent check, logging, and clearing the resource. Worse yet, the way the resource is cleared is inconsistent between different sites. Convert release_resource() calls into pci_release_resource() to remove code duplication. This will also make the resource start, end, and flags behavior consistent, i.e., start address is cleared, and only IORESOURCE_UNSET is asserted for the resource. While at it, eliminate the unnecessary initialization of idx variable in pci_bridge_release_resources(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 46 +++++++++++++---------------------------- drivers/pci/setup-res.c | 11 +++++++--- include/linux/pci.h | 2 +- 3 files changed, 23 insertions(+), 36 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 6bdc1af887da..b62465665abc 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -473,8 +473,6 @@ static void __assign_resources_sorted(struct list_head = *head, struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; struct resource *res; struct pci_dev *dev; - const char *res_name; - int idx; unsigned long fail_type; resource_size_t add_align, align; =20 @@ -582,14 +580,7 @@ static void __assign_resources_sorted(struct list_head= *head, res =3D dev_res->res; dev =3D dev_res->dev; =20 - if (!res->parent) - continue; - - idx =3D pci_resource_num(dev, res); - res_name =3D pci_resource_name(dev, idx); - pci_dbg(dev, "%s %pR: releasing\n", res_name, res); - - release_resource(res); + pci_release_resource(dev, pci_resource_num(dev, res)); restore_dev_resource(dev_res); } /* Restore start/end/flags from saved list */ @@ -1732,7 +1723,7 @@ static void pci_bridge_release_resources(struct pci_b= us *bus, struct resource *r; unsigned int old_flags; struct resource *b_res; - int idx =3D 1; + int idx, ret; =20 b_res =3D &dev->resource[PCI_BRIDGE_RESOURCES]; =20 @@ -1766,21 +1757,18 @@ static void pci_bridge_release_resources(struct pci= _bus *bus, =20 /* If there are children, release them all */ release_child_resources(r); - if (!release_resource(r)) { - type =3D old_flags =3D r->flags & PCI_RES_TYPE_MASK; - pci_info(dev, "resource %d %pR released\n", - PCI_BRIDGE_RESOURCES + idx, r); - /* Keep the old size */ - resource_set_range(r, 0, resource_size(r)); - r->flags =3D 0; =20 - /* Avoiding touch the one without PREF */ - if (type & IORESOURCE_PREFETCH) - type =3D IORESOURCE_PREFETCH; - __pci_setup_bridge(bus, type); - /* For next child res under same bridge */ - r->flags =3D old_flags; - } + type =3D old_flags =3D r->flags & PCI_RES_TYPE_MASK; + ret =3D pci_release_resource(dev, PCI_BRIDGE_RESOURCES + idx); + if (ret) + return; + + /* Avoiding touch the one without PREF */ + if (type & IORESOURCE_PREFETCH) + type =3D IORESOURCE_PREFETCH; + __pci_setup_bridge(bus, type); + /* For next child res under same bridge */ + r->flags =3D old_flags; } =20 enum release_type { @@ -2425,7 +2413,6 @@ int pci_reassign_bridge_resources(struct pci_dev *bri= dge, unsigned long type) for (i =3D PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END; i++) { struct resource *res =3D &bridge->resource[i]; - const char *res_name =3D pci_resource_name(bridge, i); =20 if ((res->flags ^ type) & PCI_RES_TYPE_MASK) continue; @@ -2438,12 +2425,7 @@ int pci_reassign_bridge_resources(struct pci_dev *br= idge, unsigned long type) if (ret) goto cleanup; =20 - pci_info(bridge, "%s %pR: releasing\n", res_name, res); - - if (res->parent) - release_resource(res); - res->start =3D 0; - res->end =3D 0; + pci_release_resource(bridge, i); break; } if (i =3D=3D PCI_BRIDGE_RESOURCE_END) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index d2b3ed51e880..0468c058b598 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -406,20 +406,25 @@ int pci_reassign_resource(struct pci_dev *dev, int re= sno, return 0; } =20 -void pci_release_resource(struct pci_dev *dev, int resno) +int pci_release_resource(struct pci_dev *dev, int resno) { struct resource *res =3D pci_resource_n(dev, resno); const char *res_name =3D pci_resource_name(dev, resno); + int ret; =20 if (!res->parent) - return; + return 0; =20 pci_info(dev, "%s %pR: releasing\n", res_name, res); =20 - release_resource(res); + ret =3D release_resource(res); + if (ret) + return ret; res->end =3D resource_size(res) - 1; res->start =3D 0; res->flags |=3D IORESOURCE_UNSET; + + return 0; } EXPORT_SYMBOL(pci_release_resource); =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 59876de13860..275df4058767 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1417,7 +1417,7 @@ void pci_reset_secondary_bus(struct pci_dev *dev); void pcibios_reset_secondary_bus(struct pci_dev *dev); void pci_update_resource(struct pci_dev *dev, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); -void pci_release_resource(struct pci_dev *dev, int resno); +int pci_release_resource(struct pci_dev *dev, int resno); static inline int pci_rebar_bytes_to_size(u64 bytes) { bytes =3D roundup_pow_of_two(bytes); --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C726E31B11E; Fri, 29 Aug 2025 13:12:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473152; cv=none; b=IjQ748DZu2t9Zg+0zlrQwayVNaGT9eALJ8VyAe4iPA9q9BipaBcvxosqkltGUKfELgHlzDh8jgxMBHrZlBqraWvnJ64y4ytN3nmNXkml2UN50lLDz7Eqr0LK8PrONuYrUwCyZKKyo7taUQzOBtw9ksjFL50PPK5VfeOEYQscwO8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473152; c=relaxed/simple; bh=Eo72xAv7jghx9O6Fsf3ThNl0hq7XmmdALUKezO79nNI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; 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29 Aug 2025 06:12:28 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 09/24] PCI: Enable bridge even if bridge window fails to assign Date: Fri, 29 Aug 2025 16:10:58 +0300 Message-Id: <20250829131113.36754-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable A normal PCI bridge has multiple bridge windows and not all of them are always required by devices underneath the bridge. If a Root Port or bridge does not have a device underneath, no bridge windows get assigned. Yet, pci_enable_resources() is set to fail indiscriminantly on any resource assignment failure if the resource is not known to be optional. In practice, the code in pci_enable_resources() is currently largely dormant. The kernel sets resource flags to zero for any unused bridge window and resets flags to zero in case of an resource assignment failure, which short-circuits pci_enable_resources() because of this check: if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) continue; However, an upcoming change to resource flags will alter how bridge window resource flags behave activating these long dormants checks in pci_enable_resources(). While complex logic could be built to selectively enable a bridge only under some conditions, a few versions of such logic were tried during development of this change and none of them worked satisfactorily. Thus, I just gave up and decided to enable any bridge regardless of the bridge windows as there seems to be no clear benefit from not enabling it, but a major downside as pcieport will not be probed for the bridge if it's not enabled. Therefore, change pci_enable_resources() to not check if bridge window resources remain unassigned. Resource assignment failures are pretty noisy already so there is no need to log that for bridge windows in pci_enable_resources(). Ignoring bridge window failures hopefully prevents an obvious source of regressions when the upcoming change that no longer clears resource flags for bridge windows is enacted. I've hit this problem even during my own testing on multiple occasions so I expect it to be a quite common problem. This can always be revisited later if somebody thinks the enable check for bridges is not strict enough, but expect a mind-boggling number of regressions from such a change. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-res.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 0468c058b598..4e0e60256f04 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -527,22 +527,26 @@ int pci_enable_resources(struct pci_dev *dev, int mas= k) if (pci_resource_is_optional(dev, i)) continue; =20 - if (r->flags & IORESOURCE_UNSET) { - pci_err(dev, "%s %pR: not assigned; can't enable device\n", - r_name, r); - return -EINVAL; + if (i < PCI_BRIDGE_RESOURCES) { + if (r->flags & IORESOURCE_UNSET) { + pci_err(dev, "%s %pR: not assigned; can't enable device\n", + r_name, r); + return -EINVAL; + } + + if (!r->parent) { + pci_err(dev, "%s %pR: not claimed; can't enable device\n", + r_name, r); + return -EINVAL; + } } =20 - if (!r->parent) { - pci_err(dev, "%s %pR: not claimed; can't enable device\n", - r_name, r); - return -EINVAL; + if (r->parent) { + if (r->flags & IORESOURCE_IO) + cmd |=3D PCI_COMMAND_IO; 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d="scan'208";a="174733738" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:35 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 10/24] PCI: Preserve bridge window resource type flags Date: Fri, 29 Aug 2025 16:10:59 +0300 Message-Id: <20250829131113.36754-11-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable When a bridge window is found unused or fails to assign, the flags of the associated resource are cleared. Clearing flags is problematic as it also removes the type information of the resource which is needed later. Thus, always preserve the bridge window type flags and use IORESOURCE_UNSET and IORESOURCE_DISABLED to indicate the status of the bridge window. Also, when initializing resources, make sure all valid bridge windows do get their type flags set. Change various places that relied on resource flags being cleared to check for IORESOURCE_UNSET and IORESOURCE_DISABLED to allow bridge window resource to retain their type flags. Add pdev_resource_assignable() and pdev_resource_should_fit() helpers to filter out disabled bridge windows during resource fitting; the latter combines more common checks into the helper. When reading the bridge windows from the registers, instead of leaving the resource flags cleared for bridge windows that are not enabled, always set up the flags and set IORESOURCE_UNSET | IORESOURCE_DISABLED as needed. When resource fitting or assignment fails for a bridge window resource, or the bridge window is not needed, mark the resource with IORESOURCE_UNSET or IORESOURCE_DISABLED, respectively. Use dummy zero resource in resource_show() for backwards compatibility as lspci will otherwise misrepresent disabled bridge windows. This change fixes an issue which highlights the importance of keeping the resource type flags intact: At the end of __assign_resources_sorted(), reset_resource() is called, previously clearing the flags. Later, pci_prepare_next_assign_round() attempted to release bridge resources using pci_bus_release_bridge_resources() that calls into pci_bridge_release_resources() that assumes type flags are still present. As type flags were cleared, IORESOURCE_MEM_64 was not set leading to resources under an incorrect bridge window to be released (idx =3D 1 instead of idx =3D 2). While the assignments performed later covered this problem so that the wrongly released resources got assigned in the end, it was still causing extra release+assign pairs. There are other reasons why the resource flags should be retained in upcoming changes too. Removing the flag reset for non-bridge window resource is left as future work, in part because it has a much higher regression potential due to pci_enable_resources() that will start to work also for those resources then and due to what endpoint drivers might assume about resources. Despite the Fixes tag, backporting this (at least any time soon) is highly discouraged. The issue fixed is borderline cosmetic as the later assignments normally cover the problem entirely. Also there might be non-obvious dependencies. Fixes: 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to 6= 4-bit resources") Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/bus.c | 3 ++ drivers/pci/pci-sysfs.c | 7 ++++ drivers/pci/probe.c | 25 +++++++++--- drivers/pci/setup-bus.c | 89 +++++++++++++++++++++++++++-------------- drivers/pci/setup-res.c | 3 ++ 5 files changed, 90 insertions(+), 37 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index b77fd30bbfd9..58b5388423ee 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -204,6 +204,9 @@ static int pci_bus_alloc_from_region(struct pci_bus *bu= s, struct resource *res, if (!r) continue; =20 + if (r->flags & (IORESOURCE_UNSET|IORESOURCE_DISABLED)) + continue; + /* type_mask must match */ if ((res->flags ^ r->flags) & type_mask) continue; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 5eea14c1f7f5..162a5241c7f7 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -177,6 +177,13 @@ static ssize_t resource_show(struct device *dev, struc= t device_attribute *attr, =20 for (i =3D 0; i < max; i++) { struct resource *res =3D &pci_dev->resource[i]; + struct resource zerores =3D {}; + + /* For backwards compatibility */ + if (i >=3D PCI_BRIDGE_RESOURCES && i <=3D PCI_BRIDGE_RESOURCE_END && + res->flags & (IORESOURCE_UNSET | IORESOURCE_DISABLED)) + res =3D &zerores; + pci_resource_to_user(pci_dev, i, res, &start, &end); len +=3D sysfs_emit_at(buf, len, "0x%016llx 0x%016llx 0x%016llx\n", (unsigned long long)start, diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index f41128f91ca7..f31d27c7708a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -419,13 +419,17 @@ static void pci_read_bridge_io(struct pci_dev *dev, s= truct resource *res, limit |=3D ((unsigned long) io_limit_hi << 16); } =20 + res->flags =3D (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; + if (base <=3D limit) { - res->flags =3D (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; region.start =3D base; region.end =3D limit + io_granularity - 1; pcibios_bus_to_resource(dev->bus, res, ®ion); if (log) pci_info(dev, " bridge window %pR\n", res); + } else { + resource_set_range(res, 0, 0); + res->flags |=3D IORESOURCE_UNSET | IORESOURCE_DISABLED; } } =20 @@ -440,13 +444,18 @@ static void pci_read_bridge_mmio(struct pci_dev *dev,= struct resource *res, pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); base =3D ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; limit =3D ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; + + res->flags =3D (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_ME= M; + if (base <=3D limit) { - res->flags =3D (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_M= EM; region.start =3D base; region.end =3D limit + 0xfffff; pcibios_bus_to_resource(dev->bus, res, ®ion); if (log) pci_info(dev, " bridge window %pR\n", res); + } else { + resource_set_range(res, 0, 0); + res->flags |=3D IORESOURCE_UNSET | IORESOURCE_DISABLED; } } =20 @@ -489,16 +498,20 @@ static void pci_read_bridge_mmio_pref(struct pci_dev = *dev, struct resource *res, return; } =20 + res->flags =3D (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | IORESOURCE_MEM | + IORESOURCE_PREFETCH; + if (res->flags & PCI_PREF_RANGE_TYPE_64) + res->flags |=3D IORESOURCE_MEM_64; + if (base <=3D limit) { - res->flags =3D (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | - IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (res->flags & PCI_PREF_RANGE_TYPE_64) - res->flags |=3D IORESOURCE_MEM_64; region.start =3D base; region.end =3D limit + 0xfffff; pcibios_bus_to_resource(dev->bus, res, ®ion); if (log) pci_info(dev, " bridge window %pR\n", res); + } else { + resource_set_range(res, 0, 0); + res->flags |=3D IORESOURCE_UNSET | IORESOURCE_DISABLED; } } =20 diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index b62465665abc..70b210ed200d 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -190,6 +190,31 @@ static bool pdev_resources_assignable(struct pci_dev *= dev) return true; } =20 +static bool pdev_resource_assignable(struct pci_dev *dev, struct resource = *res) +{ + int idx =3D pci_resource_num(dev, res); + + if (!res->flags) + return false; + + if (idx >=3D PCI_BRIDGE_RESOURCES && idx <=3D PCI_BRIDGE_RESOURCE_END && + res->flags & IORESOURCE_DISABLED) + return false; + + return true; +} + +static bool pdev_resource_should_fit(struct pci_dev *dev, struct resource = *res) +{ + if (res->parent) + return false; + + if (res->flags & IORESOURCE_PCI_FIXED) + return false; + + return pdev_resource_assignable(dev, res); +} + /* Sort resources by alignment */ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *hea= d) { @@ -205,10 +230,7 @@ static void pdev_sort_resources(struct pci_dev *dev, s= truct list_head *head) resource_size_t r_align; struct list_head *n; =20 - if (r->flags & IORESOURCE_PCI_FIXED) - continue; - - if (!(r->flags) || r->parent) + if (!pdev_resource_should_fit(dev, r)) continue; =20 r_align =3D pci_resource_alignment(dev, r); @@ -257,8 +279,15 @@ bool pci_resource_is_optional(const struct pci_dev *de= v, int resno) return false; } =20 -static inline void reset_resource(struct resource *res) +static inline void reset_resource(struct pci_dev *dev, struct resource *re= s) { + int idx =3D pci_resource_num(dev, res); + + if (idx >=3D PCI_BRIDGE_RESOURCES && idx <=3D PCI_BRIDGE_RESOURCE_END) { + res->flags |=3D IORESOURCE_UNSET; + return; + } + res->start =3D 0; res->end =3D 0; res->flags =3D 0; @@ -610,7 +639,7 @@ static void __assign_resources_sorted(struct list_head = *head, 0 /* don't care */); } =20 - reset_resource(res); + reset_resource(dev, res); } =20 free_list(head); @@ -1014,8 +1043,11 @@ static void pbus_size_io(struct pci_bus *bus, resour= ce_size_t min_size, =20 if (r->parent || !(r->flags & IORESOURCE_IO)) continue; - r_size =3D resource_size(r); =20 + if (!pdev_resource_assignable(dev, r)) + continue; + + r_size =3D resource_size(r); if (r_size < SZ_1K) /* Might be re-aligned for ISA */ size +=3D r_size; @@ -1034,6 +1066,9 @@ static void pbus_size_io(struct pci_bus *bus, resourc= e_size_t min_size, size0 =3D calculate_iosize(size, min_size, size1, 0, 0, resource_size(b_res), min_align); =20 + if (size0) + b_res->flags &=3D ~IORESOURCE_DISABLED; + size1 =3D size0; if (realloc_head && (add_size > 0 || children_add_size > 0)) { size1 =3D calculate_iosize(size, min_size, size1, add_size, @@ -1045,13 +1080,14 @@ static void pbus_size_io(struct pci_bus *bus, resou= rce_size_t min_size, if (bus->self && (b_res->start || b_res->end)) pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", b_res, &bus->busn_res); - b_res->flags =3D 0; + b_res->flags |=3D IORESOURCE_DISABLED; return; } =20 resource_set_range(b_res, min_align, size0); b_res->flags |=3D IORESOURCE_STARTALIGN; if (bus->self && size1 > size0 && realloc_head) { + b_res->flags &=3D ~IORESOURCE_DISABLED; add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n", @@ -1198,11 +1234,13 @@ static int pbus_size_mem(struct pci_bus *bus, unsig= ned long mask, const char *r_name =3D pci_resource_name(dev, i); resource_size_t r_size; =20 - if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) || - !pdev_resources_assignable(dev) || - ((r->flags & mask) !=3D type && - (r->flags & mask) !=3D type2 && - (r->flags & mask) !=3D type3)) + if (!pdev_resources_assignable(dev) || + !pdev_resource_should_fit(dev, r)) + continue; + + if ((r->flags & mask) !=3D type && + (r->flags & mask) !=3D type2 && + (r->flags & mask) !=3D type3) continue; r_size =3D resource_size(r); =20 @@ -1253,6 +1291,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigne= d long mask, min_align =3D max(min_align, win_align); size0 =3D calculate_memsize(size, min_size, 0, 0, resource_size(b_res), m= in_align); =20 + if (size0) + b_res->flags &=3D ~IORESOURCE_DISABLED; + if (bus->self && size0 && !pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type, size0, min_align)) { @@ -1287,13 +1328,14 @@ static int pbus_size_mem(struct pci_bus *bus, unsig= ned long mask, if (bus->self && (b_res->start || b_res->end)) pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", b_res, &bus->busn_res); - b_res->flags =3D 0; + b_res->flags |=3D IORESOURCE_DISABLED; return 0; } =20 resource_set_range(b_res, min_align, size0); b_res->flags |=3D IORESOURCE_STARTALIGN; if (bus->self && size1 > size0 && realloc_head) { + b_res->flags &=3D ~IORESOURCE_DISABLED; add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %l= lx\n", b_res, &bus->busn_res, @@ -1721,7 +1763,6 @@ static void pci_bridge_release_resources(struct pci_b= us *bus, { struct pci_dev *dev =3D bus->self; struct resource *r; - unsigned int old_flags; struct resource *b_res; int idx, ret; =20 @@ -1758,17 +1799,15 @@ static void pci_bridge_release_resources(struct pci= _bus *bus, /* If there are children, release them all */ release_child_resources(r); =20 - type =3D old_flags =3D r->flags & PCI_RES_TYPE_MASK; ret =3D pci_release_resource(dev, PCI_BRIDGE_RESOURCES + idx); if (ret) return; =20 + type =3D r->flags & PCI_RES_TYPE_MASK; /* Avoiding touch the one without PREF */ if (type & IORESOURCE_PREFETCH) type =3D IORESOURCE_PREFETCH; __pci_setup_bridge(bus, type); - /* For next child res under same bridge */ - r->flags =3D old_flags; } =20 enum release_type { @@ -2246,21 +2285,9 @@ static void pci_prepare_next_assign_round(struct lis= t_head *fail_head, } =20 /* Restore size and flags */ - list_for_each_entry(fail_res, fail_head, list) { - struct resource *res =3D fail_res->res; - struct pci_dev *dev =3D fail_res->dev; - int idx =3D pci_resource_num(dev, res); - + list_for_each_entry(fail_res, fail_head, list) restore_dev_resource(fail_res); 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X-CSE-ConnectionGUID: II88PwZSR8uPsQtvk6yX1g== X-CSE-MsgGUID: 9lGyjND6TvqHc+/ZFMSrWg== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="62576096" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="62576096" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:45 -0700 X-CSE-ConnectionGUID: cHJkLA6NQWOmlbaFzEJArg== X-CSE-MsgGUID: dRNr5SJhStqkF6smQ+2bWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="174733744" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:42 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 11/24] PCI: Add defines for bridge window indexing Date: Fri, 29 Aug 2025 16:11:00 +0300 Message-Id: <20250829131113.36754-12-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable include/linux/pci.h provides PCI_BRIDGE_{IO,MEM,PREF_MEM}_WINDOW defines, however, they're based on the resource array indexing in the pci_dev struct. The struct pci_bus also has pointers to those same resources but they start from zeroth index. Add PCI_BUS_BRIDGE_{IO,MEM,PREF_MEM}_WINDOW defines to get rid of literal indexing. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 4 ++++ drivers/pci/probe.c | 10 +++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 34f65d69662e..1dc8a8066761 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -81,6 +81,10 @@ struct pcie_tlp_log; #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 =20 +#define PCI_BUS_BRIDGE_IO_WINDOW 0 +#define PCI_BUS_BRIDGE_MEM_WINDOW 1 +#define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; =20 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index f31d27c7708a..eaeb66bec433 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -598,9 +598,13 @@ void pci_read_bridge_bases(struct pci_bus *child) for (i =3D 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) child->resource[i] =3D &dev->resource[PCI_BRIDGE_RESOURCES+i]; =20 - pci_read_bridge_io(child->self, child->resource[0], false); - pci_read_bridge_mmio(child->self, child->resource[1], false); - pci_read_bridge_mmio_pref(child->self, child->resource[2], false); + pci_read_bridge_io(child->self, + child->resource[PCI_BUS_BRIDGE_IO_WINDOW], false); + pci_read_bridge_mmio(child->self, + child->resource[PCI_BUS_BRIDGE_MEM_WINDOW], false); + pci_read_bridge_mmio_pref(child->self, + child->resource[PCI_BUS_BRIDGE_PREF_MEM_WINDOW], + false); =20 if (!dev->transparent) return; --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D5902E7BDA; Fri, 29 Aug 2025 13:12:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473173; cv=none; b=sZkuglEtZINu3Jq9CM6XXxx30I4MkMRsn9yO5cYZ99MuGgaVFgW4l/fw1zG2/2pc2/j6VkBsPvuyZvcooeiSFDVbJIp49NbPyS42eFNHG4Vaj+F3t8Jbhv29Al9nb++CKipVZMH+5wbylQ6KroqNaEZrWjHWPboMlk5KkDMl6fk= ARC-Message-Signature: i=1; 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d="scan'208";a="174733745" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:50 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 12/24] PCI: Add bridge window selection functions Date: Fri, 29 Aug 2025 16:11:01 +0300 Message-Id: <20250829131113.36754-13-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Various places in the PCI core code independently decide into which bridge window a child resource should be placed. It is hard to see whether these decisions always end up in agreement, especially in the corner cases, and in some places it requires complex logic to pass multiple resource types and/or bridge windows around. Add pbus_select_window() and pbus_select_window_for_type() for cases where the former cannot be used so that eventually the same helper can be used to select the bridge window everywhere. Using the same function ensures the selected bridge window remains always the same and it can be easily recalculated in-situ allowing simplifying the interfaces between internal functions in upcoming changes. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 2 + drivers/pci/setup-bus.c | 101 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 1dc8a8066761..cbd40f05c39c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -385,6 +385,8 @@ static inline int pci_resource_num(const struct pci_dev= *dev, return resno; } =20 +struct resource *pbus_select_window(struct pci_bus *bus, + const struct resource *res); void pci_reassigndev_resource_alignment(struct pci_dev *dev); void pci_disable_bridge_window(struct pci_dev *dev); struct pci_bus *pci_bus_get(struct pci_bus *bus); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 70b210ed200d..913fd41e1d0d 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -172,6 +172,107 @@ static struct resource *find_bus_resource_of_type(str= uct pci_bus *bus, return r_assigned; } =20 +/** + * pbus_select_window_for_type - Select bridge window for a resource type + * @bus: PCI bus + * @type: Resource type (resource flags can be passed as is) + * + * Select the bridge window based on a resource @type. + * + * For memory resources, the selection is done as follows: + * + * Any non-prefetchable resource is put into the non-prefetchable window. + * + * If there is no prefetchable MMIO window, put all memory resources into = the + * non-prefetchable window. + * + * If there's a 64-bit prefetchable MMIO window, put all 64-bit prefetchab= le + * resources into it and place 32-bit prefetchable memory into the + * non-prefetchable window. + * + * Otherwise, put all prefetchable resources into the prefetchable window. + * + * Return: the bridge window resource or NULL if no bridge window is found. + */ +static struct resource *pbus_select_window_for_type(struct pci_bus *bus, + unsigned long type) +{ + int iores_type =3D type & IORESOURCE_TYPE_BITS; /* w/o 64bit & pref */ + struct resource *mmio, *mmio_pref, *win; + + type &=3D PCI_RES_TYPE_MASK; /* with 64bit & pref */ + + if ((iores_type !=3D IORESOURCE_IO) && (iores_type !=3D IORESOURCE_MEM)) + return NULL; + + if (pci_is_root_bus(bus)) { + win =3D find_bus_resource_of_type(bus, type, type); + if (win) + return win; + + type &=3D ~IORESOURCE_MEM_64; + win =3D find_bus_resource_of_type(bus, type, type); + if (win) + return win; + + type &=3D ~IORESOURCE_PREFETCH; + return find_bus_resource_of_type(bus, type, type); + } + + switch (iores_type) { + case IORESOURCE_IO: + return pci_bus_resource_n(bus, PCI_BUS_BRIDGE_IO_WINDOW); + + case IORESOURCE_MEM: + mmio =3D pci_bus_resource_n(bus, PCI_BUS_BRIDGE_MEM_WINDOW); + mmio_pref =3D pci_bus_resource_n(bus, PCI_BUS_BRIDGE_PREF_MEM_WINDOW); + + if (!(type & IORESOURCE_PREFETCH) || + !(mmio_pref->flags & IORESOURCE_MEM)) + return mmio; + + if ((type & IORESOURCE_MEM_64) || + !(mmio_pref->flags & IORESOURCE_MEM_64)) + return mmio_pref; + + return mmio; + default: + return NULL; + } +} + +/** + * pbus_select_window - Select bridge window for a resource + * @bus: PCI bus + * @res: Resource + * + * Select the bridge window for @res. If the resource is already assigned, + * return the current bridge window. + * + * For memory resources, the selection is done as follows: + * + * Any non-prefetchable resource is put into the non-prefetchable window. + * + * If there is no prefetchable MMIO window, put all memory resources into = the + * non-prefetchable window. + * + * If there's a 64-bit prefetchable MMIO window, put all 64-bit prefetchab= le + * resources into it and place 32-bit prefetchable memory into the + * non-prefetchable window. + * + * Otherwise, put all prefetchable resources into the prefetchable window. + * + * Return: the bridge window resource or NULL if no bridge window is found. + */ +struct resource *pbus_select_window(struct pci_bus *bus, + const struct resource *res) +{ + if (res->parent) + return res->parent; + + return pbus_select_window_for_type(bus, res->flags); +} + static bool pdev_resources_assignable(struct pci_dev *dev) { u16 class =3D dev->class >> 8, command; --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CB1E31AF29; Fri, 29 Aug 2025 13:12:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473181; cv=none; b=mUtZrsEkfj8TcaCqSdDadRcKmQngm3L4Y8lzpg6hPM7Gmvn9WOpUrh7rl6P6dz0zrpSMF1NATgpfN6BtbLqNCgJXyNRIMerbFKqs1rbIl/Rx3fn8Fj88LvIwOArINZYCWN9bd9f3JoSKF20z7qixtLFf3Nkvpmh6L2dP9ONSWwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473181; c=relaxed/simple; bh=ncIGZH0YgUz4aIK0xB5ReVsHWKkCKIQ51Z//CtFD9/Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=fcFDiCD+x2bDmqJR4+Z+P+gn3FKBiqa2CpJJt9H1FaF9af9i/04DniXvUZFN+lfznOVm0amqDrppGKXMt9f4GHM0U1BEEMJjcFPcm1KtjUgBkoOH3xzCPZCHDUmcb+nEqa5TQFYIsoaZSm3Csze144xeQMRqXi3r9tRhRGyIi3s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dK2ZGe97; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dK2ZGe97" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473180; x=1788009180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ncIGZH0YgUz4aIK0xB5ReVsHWKkCKIQ51Z//CtFD9/Y=; b=dK2ZGe97QdCUjWs9OrS2AZMDVQ8pamX/sHNvyZ+wzhZw8PuO2fXnBPQA aehOQF92lh0OmqzrITI9sNxFtI2XFKk1931WoIsyydZIoUV4U9ErGrVh4 sl+QvmGp/HWFeV2yNsju6FA8B6LrxUXI1zipAvIjSVy8qk7+V+DB7JQN5 j0rQcxkAHKzuBN6YR7oCR6YV/XPwgrj/N+sNWE7npFOi4LsHfzKxteW/x Tf0WhOYLyJvM46U9Xg3iO4LYUj/HMef6zWHAg+ViInJA1KRLqH60jpSoa h/S+IwlShmWa2WKFpGGMAGh36uXtDMi9FjrguuvofxfBmmBcG1GiyJ11Z w==; X-CSE-ConnectionGUID: taaEgf9jQs+Db3O9joaBqg== X-CSE-MsgGUID: /JKGCkEJQYKnZTAcf3SfMw== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="62576120" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="62576120" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:59 -0700 X-CSE-ConnectionGUID: nSRZTtfLQayp2HFSYtK/jQ== X-CSE-MsgGUID: +QR1nEcuRLuwD32oo28Utw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="174733748" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:12:57 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 13/24] PCI: Fix finding bridge window in pci_reassign_bridge_resources() Date: Fri, 29 Aug 2025 16:11:02 +0300 Message-Id: <20250829131113.36754-14-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_reassign_bridge_resources() walks upwards in the PCI bus hierarchy, locates the relevant bridge window on each level using flags check, and attempts to release the bridge window. The flags-based check is fragile due to various fallbacks in the bridge window selection logic. As such, the algorithm might not locate the correct bridge window. Refactor pci_reassign_bridge_resources() to determine the correct bridge window using pbus_select_window(), which contains logic to handle all fallback cases correctly. Change function prefix to pbus as it now inputs struct bus and resource for which to locate the bridge window. The main purpose is to make bridge window selection logic consistent across the entire PCI core (one step at a time). While this technically also fixes the commit 8bb705e3e79d ("PCI: Add pci_resize_resource() for resizing BARs") making the bridge window walk algorithm more robust, the normal setup having a 64-bit resizable BAR underneath bridge(s) with 64-bit prefetchable windows does not need to use any fallbacks. As such, the practical impact is low (requiring BAR resize use case and a non-typical bridge device). The way to detect if unrelated resource failed again is left to use the type based approximation which should not behave worse than before. Fixes: 8bb705e3e79d ("PCI: Add pci_resize_resource() for resizing BARs") Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 2 +- drivers/pci/setup-bus.c | 38 ++++++++++++++++++-------------------- drivers/pci/setup-res.c | 2 +- 3 files changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index cbd40f05c39c..0d96a9141227 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -334,7 +334,7 @@ struct device *pci_get_host_bridge_device(struct pci_de= v *dev); void pci_put_host_bridge_device(struct device *dev); =20 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); -int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long ty= pe); +int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *r= es); int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resourc= e_size_t add_size, resource_size_t align); =20 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 913fd41e1d0d..4b08b9cecab3 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2522,10 +2522,16 @@ void pci_assign_unassigned_bridge_resources(struct = pci_dev *bridge) } EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); =20 -int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long ty= pe) +/* + * Walk to the root bus, find the bridge window relevant for @res and + * release it when possible. If the bridge window contains assigned + * resources, it cannot be released. + */ +int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *r= es) { + unsigned long type =3D res->flags; struct pci_dev_resource *dev_res; - struct pci_dev *next; + struct pci_dev *bridge; LIST_HEAD(saved); LIST_HEAD(added); LIST_HEAD(failed); @@ -2534,33 +2540,25 @@ int pci_reassign_bridge_resources(struct pci_dev *b= ridge, unsigned long type) =20 down_read(&pci_bus_sem); =20 - /* Walk to the root hub, releasing bridge BARs when possible */ - next =3D bridge; - do { - bridge =3D next; - for (i =3D PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END; - i++) { - struct resource *res =3D &bridge->resource[i]; - - if ((res->flags ^ type) & PCI_RES_TYPE_MASK) - continue; + while (!pci_is_root_bus(bus)) { + bridge =3D bus->self; + res =3D pbus_select_window(bus, res); + if (!res) + break; =20 - /* Ignore BARs which are still in use */ - if (res->child) - continue; + i =3D pci_resource_num(bridge, res); =20 + /* Ignore BARs which are still in use */ + if (!res->child) { ret =3D add_to_list(&saved, bridge, res, 0, 0); if (ret) goto cleanup; =20 pci_release_resource(bridge, i); - break; } - if (i =3D=3D PCI_BRIDGE_RESOURCE_END) - break; =20 - next =3D bridge->bus ? bridge->bus->self : NULL; - } while (next); + bus =3D bus->parent; + } =20 if (list_empty(&saved)) { up_read(&pci_bus_sem); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 21f77e5c647c..c3ba4ccecd43 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -496,7 +496,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) =20 /* Check if the new config works by trying to assign everything. */ if (dev->bus->self) { - ret =3D pci_reassign_bridge_resources(dev->bus->self, res->flags); + ret =3D pbus_reassign_bridge_resources(dev->bus, res); if (ret) goto error_resize; } --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E34E929D267; Fri, 29 Aug 2025 13:13:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473188; cv=none; b=IWkbUYintc27jZRjymQ1RwGx11PoSDmKxzapyUTXR+/gZAPCPpaTKIoSvtingUfmuimgPAz1ySVpSzwX73yOV1NFwqgvrP5pUBazunUVJFrymwxJdwiVCK4trEo1TiqJZtBnQNiuYzbmZQOffYByHMZS63l/aNtZNIWooQA0B6A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473188; c=relaxed/simple; bh=YAtXaIrqxIsPbnTVDScJPvQkrTlHwC25VBd/X8muHHw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=eMKu483v432R1ELJOME5qGRWDb5DASo2DEfvDUJxoC/0QPk4HoTnZopr5UrFzVSgDB5dBjyxUJERkU6eDhcCbRb/80A68qW0njxduvCzQy6wUnIDKpnEhiZ2q/A3wmkJHr7jLJjFwnQcVOwk0c2iG8HNI0l5XztWdNdE+aJ9bSM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=U+8fR+kF; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U+8fR+kF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473187; x=1788009187; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YAtXaIrqxIsPbnTVDScJPvQkrTlHwC25VBd/X8muHHw=; b=U+8fR+kF/pIABhDZ5IzyX4s/O4Nlm7tI/Ur+Oq+KSy3XyjjW5iqx9M31 6R98zgp5rM1ITwC8DhYfxPgFGOo8DDSWa/bnEmmjSwaxq8RfJYWSZNoPs Zh2nqW8DeJbAzCyn75NkPLgBW83GUptRNX+dbc81R9qfMxVJOGqPt3aki cWV+hyNgNF3FyelMYUuNKmXjjCSW7/cbJe33UeYcxuR9M7emYiaI0pnRd l8zAUxAT0Ir6ipO9HzfYSJxUAb/lgFKN9wHT9OFnrs7ZhL6f06EJC7CHG +77yMbOLJKjvykBbJn/fPvf3yaLIxjxcWh7kDkzu8HkANrl8+MuUFK6Fq Q==; X-CSE-ConnectionGUID: ihqhxOxmSYO/7annjSroig== X-CSE-MsgGUID: VhueZqINQXuf4nO/NU25RQ== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="62576129" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="62576129" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:06 -0700 X-CSE-ConnectionGUID: 13Yue80OQL6kD1r017javA== X-CSE-MsgGUID: 1/heaiDbTTOEc07fs6Zupw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="174733754" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:04 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 14/24] PCI: Warn if bridge window cannot be released when resizing BAR Date: Fri, 29 Aug 2025 16:11:03 +0300 Message-Id: <20250829131113.36754-15-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable BAR resizing calls to pci_reassign_bridge_resources(), which attempts to release any upstream bridge window to allow them to accommodate the new BAR size. The release can only be performed if there are no other child resources for the bridge window. Previously the code continued silently when other child resources were detected. Add pci_warn() to inform user that a bridge window could not be released because of child resources. As a small bridge window is often the reason why BAR resize fails, this warning will help to pinpoint to the cause. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 4b08b9cecab3..47f1a4747607 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2555,6 +2555,12 @@ int pbus_reassign_bridge_resources(struct pci_bus *b= us, struct resource *res) goto cleanup; =20 pci_release_resource(bridge, i); + } else { + const char *res_name =3D pci_resource_name(bridge, i); + + pci_warn(bridge, + "%s %pR: was not released (still contains assigned resources)\n", + res_name, res); } =20 bus =3D bus->parent; --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEB1C29D267; Fri, 29 Aug 2025 13:13:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473197; cv=none; b=bugMxO7l7HhTBKkImqfhc43n/Mo7hj9R+XCiEyblP1z6ugQhNdJXqXiTwgUel/0z88ZycYoE7Gwd5EufiWd9sQxXibm4zsW8RXRWC3x74kZV3G1/R2Bl0GwNOTU3EPVNXfy90jNs7yo6Tr7162tGmsnzfeYJHPhtBzRJKUF6xHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473197; c=relaxed/simple; bh=8RJJHwoV7RWSqBYUoUcIWbmCK3tDJ2a9+TXbWu1rw7I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=jHS+kBqi3k6ssxDlNCFEGPGxBrsh8VQCmEvK58jmuQn10BQje0y0SKD6eKdHG7btMznGhlq6tU/V6Ep/7ct/Gw6QjaJIQ+A3bT3Z5+m8rU2qK5aX+qw/cMRtyIGQeJPpljBEqC9Bu+lC/GkpE2tpJq0IQLGxV9uZx3jKHixgG9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UPG2cd+7; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UPG2cd+7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473196; x=1788009196; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8RJJHwoV7RWSqBYUoUcIWbmCK3tDJ2a9+TXbWu1rw7I=; b=UPG2cd+7pJPrQcOp3x7nbiubkTtJa+X36fYe8Z1Ilr1CzsUks0izX37s WWNE5lvVyaVWjwUuaOXIhlAJWx/toIcbAcEsvXVWisFt10Aehe5qf+rxs glV6OjDdmwmuwMDXywKr0T71w+tzipz94kb6o1vioZJNOlT4dPnyxx+D1 r+dKg8az4c+82OPBxSmd9PZ2TmxwEX1Q+LEg6MsGJdW9Q3uhqns12CfYt ZdYX7I4HovnC765KsQ5CQjM7bhQJzGUo8OA1HBNzodj9uJuGbBwnqFf5I bujBaQ0N7oEkPIrvSr33UChom9eXKAx/8u1RhmhRTdljfgBNhw3n8CNyP Q==; X-CSE-ConnectionGUID: e5WyPq6oQcG60pB2PI7HjQ== X-CSE-MsgGUID: Y9pzfUrQRt6XTzcU3VoIPA== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="62587466" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="62587466" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:14 -0700 X-CSE-ConnectionGUID: DVycP/aOSbyPdNGUHTw9EA== X-CSE-MsgGUID: L2ssu3wARGuMLL5LtX7WeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="175656769" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:11 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 15/24] PCI: Use pbus_select_window() during BAR resize Date: Fri, 29 Aug 2025 16:11:04 +0300 Message-Id: <20250829131113.36754-16-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Prior to a BAR resize, __resource_resize_store() loops through the normal resources of the PCI device and releases those that match to the flags of the BAR to be resized. This is necessary to allow resizing also the upstream bridge window as only childless bridge windows can be resized. While the flags check (mostly) works (if corner cases are ignored), the more straightforward way is to check if the resources share the bridge window. Change __resource_resize_store() to do the check using pbus_select_window(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci-sysfs.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 162a5241c7f7..ce3923c4aa80 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1562,13 +1562,19 @@ static ssize_t __resource_resize_store(struct devic= e *dev, int n, const char *buf, size_t count) { struct pci_dev *pdev =3D to_pci_dev(dev); - unsigned long size, flags; + struct pci_bus *bus =3D pdev->bus; + struct resource *b_win, *res; + unsigned long size; int ret, i; u16 cmd; =20 if (kstrtoul(buf, 0, &size) < 0) return -EINVAL; =20 + b_win =3D pbus_select_window(bus, pci_resource_n(pdev, n)); + if (!b_win) + return -EINVAL; + device_lock(dev); if (dev->driver || pci_num_vf(pdev)) { ret =3D -EBUSY; @@ -1588,19 +1594,19 @@ static ssize_t __resource_resize_store(struct devic= e *dev, int n, pci_write_config_word(pdev, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMORY); =20 - flags =3D pci_resource_flags(pdev, n); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert pbus_size_io() to use pbus_select_window_for_type(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 47f1a4747607..a21d6367e525 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1122,8 +1122,7 @@ static void pbus_size_io(struct pci_bus *bus, resourc= e_size_t min_size, struct list_head *realloc_head) { struct pci_dev *dev; - struct resource *b_res =3D find_bus_resource_of_type(bus, IORESOURCE_IO, - IORESOURCE_IO); + struct resource *b_res =3D pbus_select_window_for_type(bus, IORESOURCE_IO= ); resource_size_t size =3D 0, size0 =3D 0, size1 =3D 0; resource_size_t children_add_size =3D 0; resource_size_t min_align, align; --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8753031DD8C; Fri, 29 Aug 2025 13:13:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473210; cv=none; b=aEhUwnaUHerrE12p3IBL+QLFcLPqd6ESh3Uw7JHrk8KtVtdowqH5QOeut03WVEED/SkNwZ99cmqseFIk0xOKgXz2cuo0GsUjlhe9rwHJBgY+Bqfz3q9SNr9J6mFv6wh3J9twu15rh3A7DtYr0ILgR6wEqz2TfjEdcPv2u2l7NTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473210; c=relaxed/simple; bh=hKFs7q8kFAwGpFS94xbAyKK07PxLfWSk+RCo81+5mq4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=OehoB1Zb50yMx3F35l85VsNGJHbCl9PGFxgnQHH5iMvrcpiP9GsorT2qYNpERqjbMNgJ6QeyjHr9Y+sNkdJhK/29Yy+NdZjgUiMwNvJrUmNJVewg4vYa24BXqoAwy2mQknc4uiKr5tzwLBr+Y6DTY0WvFZSGDhfWOo6umrGNd+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lT7gYvGD; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lT7gYvGD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473210; x=1788009210; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hKFs7q8kFAwGpFS94xbAyKK07PxLfWSk+RCo81+5mq4=; b=lT7gYvGD1ige8VbCgq5BAAMSDBs4AhRinS+fIgqJjIeve9JZ/ciA3ezo pA49f5w3xEUFyz7CIW3E8vf/XYR3zzrGhX0mZX6uFsHJ3fFlSmx3PoT3L FpKwRYncPV/VJblac6LB1RFZNebSkN+7xHax1zLb+w2hm6Fg4L0mNTdvh +3RMZbdFGPMj9Zwedx0gewtMjA7XBVuMF2mZm+TZU+DZdLsnePQCF6vEt IwNTDqsyIod0QKWEZR08wfMRow7H5mlAlt2JPntWhPszxoi/PaUbQ6lXJ mGhdhgp/5tV8DheVUu84nvwA/VUk0iib+N+wLVPQAEzmMfjcil5veFVZm Q==; X-CSE-ConnectionGUID: D2kD9+zIR6Sbsysts8O5GA== X-CSE-MsgGUID: RZxL9oHyQH+jWFXy46OrKw== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="62587483" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="62587483" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:29 -0700 X-CSE-ConnectionGUID: X86hfhkTSX66MU4WG8si0Q== X-CSE-MsgGUID: YDjUKg3mQVKRjWB8pG3byA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="175656784" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:26 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 17/24] PCI: Rename resource variable from r to res Date: Fri, 29 Aug 2025 16:11:06 +0300 Message-Id: <20250829131113.36754-18-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Resource is going to be passed in as argument aften an upcoming change. Rename the struct resource variable from "r" to "res" to avoid using one letter variable name in a function argument. This rename is made separately to reduce churn in the upcoming change. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index a21d6367e525..5ec446c2b779 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1241,24 +1241,24 @@ static bool pbus_upstream_space_available(struct pc= i_bus *bus, unsigned long mas .align =3D align, }; struct pci_bus *downstream =3D bus; - struct resource *r; + struct resource *res; =20 while ((bus =3D bus->parent)) { if (pci_is_root_bus(bus)) break; =20 - pci_bus_for_each_resource(bus, r) { - if (!r || !r->parent || (r->flags & mask) !=3D type) + pci_bus_for_each_resource(bus, res) { + if (!res || !res->parent || (res->flags & mask) !=3D type) continue; =20 - if (resource_size(r) >=3D size) { + if (resource_size(res) >=3D size) { struct resource gap =3D {}; =20 - if (find_resource_space(r, &gap, size, &constraint) =3D=3D 0) { + if (find_resource_space(res, &gap, size, &constraint) =3D=3D 0) { gap.flags =3D type; pci_dbg(bus->self, "Assigned bridge window %pR to %pR free space at %pR\n", - r, &bus->busn_res, &gap); + res, &bus->busn_res, &gap); return true; } } @@ -1266,7 +1266,7 @@ static bool pbus_upstream_space_available(struct pci_= bus *bus, unsigned long mas if (bus->self) { pci_info(bus->self, "Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s= bridging to %pR\n", - r, &bus->busn_res, + res, &bus->busn_res, (unsigned long long)size, pci_name(downstream->self), &downstream->busn_res); --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7314A3218CC; Fri, 29 Aug 2025 13:13:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473216; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable pbus_upstream_space_available() figures out the upstream bridge window resources on its own. Migrate it to use pbus_select_window(). Note: pbus_select_window() -> pbus_select_window_for_type() calls find_bus_resource_of_type() for root bus, which does not do parent check similar to what pbus_upstream_space_available() did earlier, but the difference does not matter because pbus_upstream_space_available() itself stops when it encounters the root bus. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 65 ++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 5ec446c2b779..865bacae9cac 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1221,19 +1221,20 @@ static inline resource_size_t calculate_mem_align(r= esource_size_t *aligns, /** * pbus_upstream_space_available - Check no upstream resource limits alloc= ation * @bus: The bus - * @mask: Mask the resource flag, then compare it with type - * @type: The type of resource from bridge + * @res: The resource to help select the correct bridge window * @size: The size required from the bridge window * @align: Required alignment for the resource * - * Checks that @size can fit inside the upstream bridge resources that are - * already assigned. + * Check that @size can fit inside the upstream bridge resources that are + * already assigned. Select the upstream bridge window based on the type of + * @res. * * Return: %true if enough space is available on all assigned upstream * resources. */ -static bool pbus_upstream_space_available(struct pci_bus *bus, unsigned lo= ng mask, - unsigned long type, resource_size_t size, +static bool pbus_upstream_space_available(struct pci_bus *bus, + struct resource *res, + resource_size_t size, resource_size_t align) { struct resource_constraint constraint =3D { @@ -1241,39 +1242,39 @@ static bool pbus_upstream_space_available(struct pc= i_bus *bus, unsigned long mas .align =3D align, }; struct pci_bus *downstream =3D bus; - struct resource *res; =20 while ((bus =3D bus->parent)) { if (pci_is_root_bus(bus)) break; =20 - pci_bus_for_each_resource(bus, res) { - if (!res || !res->parent || (res->flags & mask) !=3D type) - continue; - - if (resource_size(res) >=3D size) { - struct resource gap =3D {}; + res =3D pbus_select_window(bus, res); + if (!res) + return false; + if (!res->parent) + continue; =20 - if (find_resource_space(res, &gap, size, &constraint) =3D=3D 0) { - gap.flags =3D type; - pci_dbg(bus->self, - "Assigned bridge window %pR to %pR free space at %pR\n", - res, &bus->busn_res, &gap); - return true; - } - } + if (resource_size(res) >=3D size) { + struct resource gap =3D {}; =20 - if (bus->self) { - pci_info(bus->self, - "Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s= bridging to %pR\n", - res, &bus->busn_res, - (unsigned long long)size, - pci_name(downstream->self), - &downstream->busn_res); + if (find_resource_space(res, &gap, size, &constraint) =3D=3D 0) { + gap.flags =3D res->flags; + pci_dbg(bus->self, + "Assigned bridge window %pR to %pR free space at %pR\n", + res, &bus->busn_res, &gap); + return true; } + } =20 - return false; + if (bus->self) { + pci_info(bus->self, + "Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s = bridging to %pR\n", + res, &bus->busn_res, + (unsigned long long)size, + pci_name(downstream->self), + &downstream->busn_res); } + + return false; } =20 return true; @@ -1395,8 +1396,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigne= d long mask, b_res->flags &=3D ~IORESOURCE_DISABLED; =20 if (bus->self && size0 && - !pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type, - size0, min_align)) { + !pbus_upstream_space_available(bus, b_res, size0, min_align)) { relaxed_align =3D 1ULL << (max_order + __ffs(SZ_1M)); relaxed_align =3D max(relaxed_align, win_align); min_align =3D min(min_align, relaxed_align); @@ -1411,8 +1411,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigne= d long mask, resource_size(b_res), add_align); =20 if (bus->self && size1 && - !pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type, - size1, add_align)) { + !pbus_upstream_space_available(bus, b_res, size1, add_align)) { relaxed_align =3D 1ULL << (max_order + __ffs(SZ_1M)); relaxed_align =3D max(relaxed_align, win_align); min_align =3D min(min_align, relaxed_align); --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A67A31A57B; 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X-CSE-ConnectionGUID: 3NjHi6PbQdeydb/yOatrDg== X-CSE-MsgGUID: /HHRxUd8SdO8JEZ9L1pRMQ== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="62587510" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="62587510" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:43 -0700 X-CSE-ConnectionGUID: oX/DVL9AQDqqfbd2c6dOOg== X-CSE-MsgGUID: N/3i7VQ1SZGIaa4UX+LucA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="175656793" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:13:40 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 19/24] PCI: Use pbus_select_window_for_type() during mem window sizing Date: Fri, 29 Aug 2025 16:11:08 +0300 Message-Id: <20250829131113.36754-20-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable __pci_bus_size_bridges() goes to great lengths of helping pbus_size_mem() in which types it should put into a particular bridge window, requiring passing up to three resource type into pbus_size_mem(). Instead of having complex logic in __pci_bus_size_bridges() and a non-straightforward interface between those functions, use pbus_select_window_for_type() and pbus_select_window() to find the correct bridge window and compare if the resources belong to that window. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 111 +++++++++------------------------------- 1 file changed, 24 insertions(+), 87 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 865bacae9cac..720159bca54d 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1284,24 +1284,22 @@ static bool pbus_upstream_space_available(struct pc= i_bus *bus, * pbus_size_mem() - Size the memory window of a given bus * * @bus: The bus - * @mask: Mask the resource flag, then compare it with type - * @type: The type of free resource from bridge - * @type2: Second match type - * @type3: Third match type + * @type: The type of bridge resource * @min_size: The minimum memory window that must be allocated * @add_size: Additional optional memory window * @realloc_head: Track the additional memory window on this list * - * Calculate the size of the bus and minimal alignment which guarantees - * that all child resources fit in this size. + * Calculate the size of the bus resource for @type and minimal alignment + * which guarantees that all child resources fit in this size. * - * Return -ENOSPC if there's no available bus resource of the desired - * type. Otherwise, set the bus resource start/end to indicate the - * required size, add things to realloc_head (if supplied), and return 0. + * Set the bus resource start/end to indicate the required size if there an + * available unassigned bus resource of the desired @type. + * + * Add optional resource requests to the @realloc_head list if it is + * supplied. */ -static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, - unsigned long type, unsigned long type2, - unsigned long type3, resource_size_t min_size, +static void pbus_size_mem(struct pci_bus *bus, unsigned long type, + resource_size_t min_size, resource_size_t add_size, struct list_head *realloc_head) { @@ -1309,19 +1307,18 @@ static int pbus_size_mem(struct pci_bus *bus, unsig= ned long mask, resource_size_t min_align, win_align, align, size, size0, size1 =3D 0; resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */ int order, max_order; - struct resource *b_res =3D find_bus_resource_of_type(bus, - mask | IORESOURCE_PREFETCH, type); + struct resource *b_res =3D pbus_select_window_for_type(bus, type); resource_size_t children_add_size =3D 0; resource_size_t children_add_align =3D 0; resource_size_t add_align =3D 0; resource_size_t relaxed_align; =20 if (!b_res) - return -ENOSPC; + return; =20 /* If resource is already assigned, nothing more to do */ if (b_res->parent) - return 0; + return; =20 memset(aligns, 0, sizeof(aligns)); max_order =3D 0; @@ -1338,11 +1335,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsign= ed long mask, if (!pdev_resources_assignable(dev) || !pdev_resource_should_fit(dev, r)) continue; - - if ((r->flags & mask) !=3D type && - (r->flags & mask) !=3D type2 && - (r->flags & mask) !=3D type3) + if (b_res !=3D pbus_select_window(bus, r)) continue; + r_size =3D resource_size(r); =20 /* Put SRIOV requested res to the optional list */ @@ -1428,7 +1423,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigne= d long mask, pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", b_res, &bus->busn_res); b_res->flags |=3D IORESOURCE_DISABLED; - return 0; + return; } =20 resource_set_range(b_res, min_align, size0); @@ -1441,7 +1436,6 @@ static int pbus_size_mem(struct pci_bus *bus, unsigne= d long mask, (unsigned long long) (size1 - size0), (unsigned long long) add_align); } - return 0; } =20 unsigned long pci_cardbus_resource_alignment(struct resource *res) @@ -1546,12 +1540,11 @@ static void pci_bus_size_cardbus(struct pci_bus *bu= s, void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc= _head) { struct pci_dev *dev; - unsigned long mask, prefmask, type2 =3D 0, type3 =3D 0; resource_size_t additional_io_size =3D 0, additional_mmio_size =3D 0, additional_mmio_pref_size =3D 0; struct resource *pref; struct pci_host_bridge *host; - int hdr_type, ret; + int hdr_type; =20 list_for_each_entry(dev, &bus->devices, bus_list) { struct pci_bus *b =3D dev->subordinate; @@ -1601,71 +1594,15 @@ void __pci_bus_size_bridges(struct pci_bus *bus, st= ruct list_head *realloc_head) pbus_size_io(bus, realloc_head ? 0 : additional_io_size, additional_io_size, realloc_head); =20 - /* - * If there's a 64-bit prefetchable MMIO window, compute - * the size required to put all 64-bit prefetchable - * resources in it. - */ - mask =3D IORESOURCE_MEM; - prefmask =3D IORESOURCE_MEM | IORESOURCE_PREFETCH; - if (pref && (pref->flags & IORESOURCE_MEM_64)) { - prefmask |=3D IORESOURCE_MEM_64; - ret =3D pbus_size_mem(bus, prefmask, prefmask, - prefmask, prefmask, - realloc_head ? 0 : additional_mmio_pref_size, - additional_mmio_pref_size, realloc_head); - - /* - * If successful, all non-prefetchable resources - * and any 32-bit prefetchable resources will go in - * the non-prefetchable window. - */ - if (ret =3D=3D 0) { - mask =3D prefmask; - type2 =3D prefmask & ~IORESOURCE_MEM_64; - type3 =3D prefmask & ~IORESOURCE_PREFETCH; - } - } - - /* - * If there is no 64-bit prefetchable window, compute the - * size required to put all prefetchable resources in the - * 32-bit prefetchable window (if there is one). - */ - if (!type2) { - prefmask &=3D ~IORESOURCE_MEM_64; - ret =3D pbus_size_mem(bus, prefmask, prefmask, - prefmask, prefmask, - realloc_head ? 0 : additional_mmio_pref_size, - additional_mmio_pref_size, realloc_head); - - /* - * If successful, only non-prefetchable resources - * will go in the non-prefetchable window. - */ - if (ret =3D=3D 0) - mask =3D prefmask; - else - additional_mmio_size +=3D additional_mmio_pref_size; - - type2 =3D type3 =3D IORESOURCE_MEM; + if (pref) { + pbus_size_mem(bus, + IORESOURCE_MEM | IORESOURCE_PREFETCH | + (pref->flags & IORESOURCE_MEM_64), + realloc_head ? 0 : additional_mmio_pref_size, + additional_mmio_pref_size, realloc_head); } =20 - /* - * Compute the size required to put everything else in the - * non-prefetchable window. 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The code is essentially the same for all of them and therefore repeated three times with different variable names. Refactor pci_bus_distribute_available_resources() to take an array. This is complicated slightly by the function taking advantage of passing the struct as value, which cannot be done for arrays in C. Therefore, copy the data into a local array in the stack in the first loop. Variable names are (hopefully) improved slightly as well. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 162 ++++++++++++++++++---------------------- include/linux/pci.h | 3 +- 2 files changed, 74 insertions(+), 91 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 720159bca54d..3bc329b1b923 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2059,15 +2059,16 @@ static void remove_dev_resource(struct resource *av= ail, struct pci_dev *dev, avail->start =3D min(avail->start + tmp, avail->end + 1); } =20 -static void remove_dev_resources(struct pci_dev *dev, struct resource *io, - struct resource *mmio, - struct resource *mmio_pref) +static void remove_dev_resources(struct pci_dev *dev, + struct resource available[PCI_P2P_BRIDGE_RESOURCE_NUM]) { + struct resource *mmio_pref =3D &available[PCI_BUS_BRIDGE_PREF_MEM_WINDOW]; struct resource *res; =20 pci_dev_for_each_resource(dev, res) { if (resource_type(res) =3D=3D IORESOURCE_IO) { - remove_dev_resource(io, dev, res); + remove_dev_resource(&available[PCI_BUS_BRIDGE_IO_WINDOW], + dev, res); } else if (resource_type(res) =3D=3D IORESOURCE_MEM) { =20 /* @@ -2081,10 +2082,13 @@ static void remove_dev_resources(struct pci_dev *de= v, struct resource *io, */ if ((res->flags & IORESOURCE_PREFETCH) && ((res->flags & IORESOURCE_MEM_64) =3D=3D - (mmio_pref->flags & IORESOURCE_MEM_64))) - remove_dev_resource(mmio_pref, dev, res); - else - remove_dev_resource(mmio, dev, res); + (mmio_pref->flags & IORESOURCE_MEM_64))) { + remove_dev_resource(&available[PCI_BUS_BRIDGE_PREF_MEM_WINDOW], + dev, res); + } else { + remove_dev_resource(&available[PCI_BUS_BRIDGE_MEM_WINDOW], + dev, res); + } } } } @@ -2099,45 +2103,39 @@ static void remove_dev_resources(struct pci_dev *de= v, struct resource *io, * shared with the bridges. */ static void pci_bus_distribute_available_resources(struct pci_bus *bus, - struct list_head *add_list, - struct resource io, - struct resource mmio, - struct resource mmio_pref) + struct list_head *add_list, + struct resource available_in[PCI_P2P_BRIDGE_RESOURCE_NUM]) { + struct resource available[PCI_P2P_BRIDGE_RESOURCE_NUM]; unsigned int normal_bridges =3D 0, hotplug_bridges =3D 0; - struct resource *io_res, *mmio_res, *mmio_pref_res; struct pci_dev *dev, *bridge =3D bus->self; - resource_size_t io_per_b, mmio_per_b, mmio_pref_per_b, align; + resource_size_t per_bridge[PCI_P2P_BRIDGE_RESOURCE_NUM]; + resource_size_t align; + int i; =20 - io_res =3D &bridge->resource[PCI_BRIDGE_IO_WINDOW]; - mmio_res =3D &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; - mmio_pref_res =3D &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; + for (i =3D 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { + struct resource *res =3D pci_bus_resource_n(bus, i); =20 - /* - * The alignment of this bridge is yet to be considered, hence it must - * be done now before extending its bridge window. - */ - align =3D pci_resource_alignment(bridge, io_res); - if (!io_res->parent && align) - io.start =3D min(ALIGN(io.start, align), io.end + 1); - - align =3D pci_resource_alignment(bridge, mmio_res); - if (!mmio_res->parent && align) - mmio.start =3D min(ALIGN(mmio.start, align), mmio.end + 1); + available[i] =3D available_in[i]; =20 - align =3D pci_resource_alignment(bridge, mmio_pref_res); - if (!mmio_pref_res->parent && align) - mmio_pref.start =3D min(ALIGN(mmio_pref.start, align), - mmio_pref.end + 1); + /* + * The alignment of this bridge is yet to be considered, + * hence it must be done now before extending its bridge + * window. + */ + align =3D pci_resource_alignment(bridge, res); + if (!res->parent && align) + available[i].start =3D min(ALIGN(available[i].start, align), + available[i].end + 1); =20 - /* - * Now that we have adjusted for alignment, update the bridge window - * resources to fill as much remaining resource space as possible. - */ - adjust_bridge_window(bridge, io_res, add_list, resource_size(&io)); - adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio)); - adjust_bridge_window(bridge, mmio_pref_res, add_list, - resource_size(&mmio_pref)); + /* + * Now that we have adjusted for alignment, update the + * bridge window resources to fill as much remaining + * resource space as possible. + */ + adjust_bridge_window(bridge, res, add_list, + resource_size(&available[i])); + } =20 /* * Calculate how many hotplug bridges and normal bridges there @@ -2161,7 +2159,7 @@ static void pci_bus_distribute_available_resources(st= ruct pci_bus *bus, */ list_for_each_entry(dev, &bus->devices, bus_list) { if (!dev->is_virtfn) - remove_dev_resources(dev, &io, &mmio, &mmio_pref); + remove_dev_resources(dev, available); } =20 /* @@ -2173,16 +2171,9 @@ static void pci_bus_distribute_available_resources(s= truct pci_bus *bus, * split between non-hotplug bridges. This is to allow possible * hotplug bridges below them to get the extra space as well. */ - if (hotplug_bridges) { - io_per_b =3D div64_ul(resource_size(&io), hotplug_bridges); - mmio_per_b =3D div64_ul(resource_size(&mmio), hotplug_bridges); - mmio_pref_per_b =3D div64_ul(resource_size(&mmio_pref), - hotplug_bridges); - } else { - io_per_b =3D div64_ul(resource_size(&io), normal_bridges); - mmio_per_b =3D div64_ul(resource_size(&mmio), normal_bridges); - mmio_pref_per_b =3D div64_ul(resource_size(&mmio_pref), - normal_bridges); + for (i =3D 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { + per_bridge[i] =3D div64_ul(resource_size(&available[i]), + hotplug_bridges ?: normal_bridges); } =20 for_each_pci_bridge(dev, bus) { @@ -2195,49 +2186,41 @@ static void pci_bus_distribute_available_resources(= struct pci_bus *bus, if (hotplug_bridges && !dev->is_hotplug_bridge) continue; =20 - res =3D &dev->resource[PCI_BRIDGE_IO_WINDOW]; + for (i =3D 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { + res =3D pci_bus_resource_n(bus, i); =20 - /* - * Make sure the split resource space is properly aligned - * for bridge windows (align it down to avoid going above - * what is available). - */ - align =3D pci_resource_alignment(dev, res); - resource_set_size(&io, ALIGN_DOWN_IF_NONZERO(io_per_b, align)); - - /* - * The x_per_b holds the extra resource space that can be - * added for each bridge but there is the minimal already - * reserved as well so adjust x.start down accordingly to - * cover the whole space. - */ - io.start -=3D resource_size(res); - - res =3D &dev->resource[PCI_BRIDGE_MEM_WINDOW]; - align =3D pci_resource_alignment(dev, res); - resource_set_size(&mmio, - ALIGN_DOWN_IF_NONZERO(mmio_per_b,align)); - mmio.start -=3D resource_size(res); + /* + * Make sure the split resource space is properly + * aligned for bridge windows (align it down to + * avoid going above what is available). + */ + align =3D pci_resource_alignment(dev, res); + resource_set_size(&available[i], + ALIGN_DOWN_IF_NONZERO(per_bridge[i], + align)); =20 - res =3D &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; - align =3D pci_resource_alignment(dev, res); - resource_set_size(&mmio_pref, - ALIGN_DOWN_IF_NONZERO(mmio_pref_per_b, align)); - mmio_pref.start -=3D resource_size(res); + /* + * The per_bridge holds the extra resource space + * that can be added for each bridge but there is + * the minimal already reserved as well so adjust + * x.start down accordingly to cover the whole + * space. + */ + available[i].start -=3D resource_size(res); + } =20 - pci_bus_distribute_available_resources(b, add_list, io, mmio, - mmio_pref); + pci_bus_distribute_available_resources(b, add_list, available); =20 - io.start +=3D io.end + 1; - mmio.start +=3D mmio.end + 1; - mmio_pref.start +=3D mmio_pref.end + 1; + for (i =3D 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) + available[i].start +=3D available[i].end + 1; } } =20 static void pci_bridge_distribute_available_resources(struct pci_dev *brid= ge, struct list_head *add_list) { - struct resource available_io, available_mmio, available_mmio_pref; + struct resource *res, available[PCI_P2P_BRIDGE_RESOURCE_NUM]; + unsigned int i; =20 if (!bridge->is_hotplug_bridge) return; @@ -2245,14 +2228,13 @@ static void pci_bridge_distribute_available_resourc= es(struct pci_dev *bridge, pci_dbg(bridge, "distributing available resources\n"); =20 /* Take the initial extra resources from the hotplug port */ - available_io =3D bridge->resource[PCI_BRIDGE_IO_WINDOW]; - available_mmio =3D bridge->resource[PCI_BRIDGE_MEM_WINDOW]; - available_mmio_pref =3D bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; + for (i =3D 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) { + res =3D pci_resource_n(bridge, PCI_BRIDGE_RESOURCES + i); + available[i] =3D *res; + } =20 pci_bus_distribute_available_resources(bridge->subordinate, - add_list, available_io, - available_mmio, - available_mmio_pref); + add_list, available); } =20 static bool pci_bridge_resources_not_assigned(struct pci_dev *dev) diff --git a/include/linux/pci.h b/include/linux/pci.h index 275df4058767..723e9cede69d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -119,7 +119,8 @@ enum { #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) =20 /* Total number of bridge resources for P2P and CardBus */ -#define PCI_BRIDGE_RESOURCE_NUM 4 +#define PCI_P2P_BRIDGE_RESOURCE_NUM 3 +#define PCI_BRIDGE_RESOURCE_NUM 4 =20 /* Resources assigned to buses behind the bridge */ PCI_BRIDGE_RESOURCES, --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E9BB322550; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Convert remove_dev_resources() to use pbus_select_window(). As 'available' is not the real resources, the index has to be adjusted as only bridge resource counterparts are present in the 'available' array. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 34 +++++++++------------------------- 1 file changed, 9 insertions(+), 25 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 3bc329b1b923..cb91c6cb4d32 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2062,34 +2062,18 @@ static void remove_dev_resource(struct resource *av= ail, struct pci_dev *dev, static void remove_dev_resources(struct pci_dev *dev, struct resource available[PCI_P2P_BRIDGE_RESOURCE_NUM]) { - struct resource *mmio_pref =3D &available[PCI_BUS_BRIDGE_PREF_MEM_WINDOW]; - struct resource *res; + struct resource *res, *b_win; + int idx; =20 pci_dev_for_each_resource(dev, res) { - if (resource_type(res) =3D=3D IORESOURCE_IO) { - remove_dev_resource(&available[PCI_BUS_BRIDGE_IO_WINDOW], - dev, res); - } else if (resource_type(res) =3D=3D IORESOURCE_MEM) { + b_win =3D pbus_select_window(dev->bus, res); + if (!b_win) + continue; =20 - /* - * Make sure prefetchable memory is reduced from - * the correct resource. Specifically we put 32-bit - * prefetchable memory in non-prefetchable window - * if there is a 64-bit prefetchable window. - * - * See comments in __pci_bus_size_bridges() for - * more information. - */ - if ((res->flags & IORESOURCE_PREFETCH) && - ((res->flags & IORESOURCE_MEM_64) =3D=3D - (mmio_pref->flags & IORESOURCE_MEM_64))) { - remove_dev_resource(&available[PCI_BUS_BRIDGE_PREF_MEM_WINDOW], - dev, res); - } else { - remove_dev_resource(&available[PCI_BUS_BRIDGE_MEM_WINDOW], - dev, res); - } - } + idx =3D pci_resource_num(dev->bus->self, b_win); + idx -=3D PCI_BRIDGE_RESOURCES; + + remove_dev_resource(&available[idx], dev, res); } } =20 --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA18E322777; Fri, 29 Aug 2025 13:14:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473246; cv=none; b=XDTNamPzXk3WHIFjqn6EzteajhWrPloG40Xy4PnRnEtpzQx8kJWrmxsxdMPdVSbSKvXkw5iYwbNUcvJhGr2EUY77nU3r0tXMo4BBDNuyeF3m8f+qo1TtFA/HqiUceEXO++PzSI/QdhR2NdBTmVKnkcgAL9XpRvuwwmUPV7hpCv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756473246; c=relaxed/simple; bh=rA6JAfN7+EEsAzQMJHpQWq+E7QCPa259KkSycF6mlUA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=bDBFU42pxVLyeK2RIXmNET+uoMSFZW7ve1q3hDqAltcyX2TF+1yKoNRxAZLeQFZEakhxGLlHitss8mmDwltZWSYf218DOtkEWOOg+kSaZ9ZWNra6c8P3Xo3yPbEXHneBNPz3L5j2FkTDcR914CI8RLsYbTgf88X9MGGultFGspk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ESErvJ61; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ESErvJ61" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756473245; x=1788009245; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rA6JAfN7+EEsAzQMJHpQWq+E7QCPa259KkSycF6mlUA=; b=ESErvJ61zSFyEE6IhG6tsOmo7afrsVIwaAX3YZ7sEdPzA100/u7KBImy /GHTue1lSeYVneHD6A/aEVC3cwgfHQJpHH+Km1Jl0a8ScVC3+oxpsltV/ LJ6H5Non2tasakHP3R6DjZysskI1KjgBL+PHznd1AONCewV7t57R3hXQm zUIMSCOLsm/6ASn3MhW8RfPSnD7/OvyXDQLlACGm004a56QNFOikqHR2o Dyea9tKMUqNhvnXVaaWe55q0+3SYD5OtNxcXri2wINjPGTUjkn7HYzmM5 1xvrcq8mPHv1bt0bIHWkL2ba6fIoNvMXdulk0AgIquyWrBB83FbWu/C26 g==; X-CSE-ConnectionGUID: sg+e/xL6TR237sYrMNUIFw== X-CSE-MsgGUID: Z4JWtOXmSmChmscCoPrKLg== X-IronPort-AV: E=McAfee;i="6800,10657,11536"; a="58905344" X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="58905344" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:14:05 -0700 X-CSE-ConnectionGUID: DEElf8zUQXmdt01whkNJKg== X-CSE-MsgGUID: cyaA9DSiRqCOebetSvsqMg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,221,1751266800"; d="scan'208";a="169680071" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:14:02 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 22/24] PCI: Add pci_setup_one_bridge_window() Date: Fri, 29 Aug 2025 16:11:11 +0300 Message-Id: <20250829131113.36754-23-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_bridge_release_resources() contains a resource type hack to work around the unsuitable __pci_setup_bridge() interface. Extract the switch statement that picks the correct bridge window setup function from pci_claim_bridge_resource() into pci_setup_one_bridge_window() and use it also in pci_bridge_release_resources(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index cb91c6cb4d32..031ad682aca1 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -953,6 +953,23 @@ static void __pci_setup_bridge(struct pci_bus *bus, un= signed long type) pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); } =20 +static void pci_setup_one_bridge_window(struct pci_dev *bridge, int resno) +{ + switch (resno) { + case PCI_BRIDGE_IO_WINDOW: + pci_setup_bridge_io(bridge); + break; + case PCI_BRIDGE_MEM_WINDOW: + pci_setup_bridge_mmio(bridge); + break; + case PCI_BRIDGE_PREF_MEM_WINDOW: + pci_setup_bridge_mmio_pref(bridge); + break; + default: + return; + } +} + void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) { } @@ -987,19 +1004,7 @@ int pci_claim_bridge_resource(struct pci_dev *bridge,= int i) if (pci_bus_clip_resource(bridge, i)) ret =3D pci_claim_resource(bridge, i); =20 - switch (i) { - case PCI_BRIDGE_IO_WINDOW: - pci_setup_bridge_io(bridge); - break; - case PCI_BRIDGE_MEM_WINDOW: - pci_setup_bridge_mmio(bridge); - break; - case PCI_BRIDGE_PREF_MEM_WINDOW: - pci_setup_bridge_mmio_pref(bridge); - break; - default: - return -EINVAL; - } + pci_setup_one_bridge_window(bridge, i); =20 return ret; } @@ -1839,11 +1844,7 @@ static void pci_bridge_release_resources(struct pci_= bus *bus, if (ret) return; =20 - type =3D r->flags & PCI_RES_TYPE_MASK; - /* Avoiding touch the one without PREF */ - if (type & IORESOURCE_PREFETCH) - type =3D IORESOURCE_PREFETCH; - __pci_setup_bridge(bus, type); + pci_setup_one_bridge_window(dev, PCI_BRIDGE_RESOURCES + idx); } =20 enum release_type { --=20 2.39.5 From nobody Fri Oct 3 14:29:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99AF033F3; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_bus_release_bridge_resources() takes type, which is converted into a bridge window resource in pci_bridge_release_resources(). Find out the correct bridge window for resource whose assignment failed. Pass that bridge window to pci_bus_release_bridge_resources() instead of passing the type. When recursing to subordinate, check which bridge windows have to be released and recurse for each. For now, use pbus_select_window_for_type() instead of pbus_select_window() because non-bridge window resources still have their flags reset which destroys the type information from the struct resource. The struct pci_dev_resource holds a copy of the flags which are used instead. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 69 ++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 42 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 031ad682aca1..4ce747b5dea3 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1800,51 +1800,24 @@ static void __pci_bridge_assign_resources(const str= uct pci_dev *bridge, } =20 static void pci_bridge_release_resources(struct pci_bus *bus, - unsigned long type) + struct resource *b_win) { struct pci_dev *dev =3D bus->self; - struct resource *r; - struct resource *b_res; int idx, ret; =20 - b_res =3D &dev->resource[PCI_BRIDGE_RESOURCES]; - - /* - * 1. If IO port assignment fails, release bridge IO port. - * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO. - * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit, - * release bridge pref MMIO. - * 4. If pref MMIO assignment fails, and bridge pref is 32bit, - * release bridge pref MMIO. - * 5. If pref MMIO assignment fails, and bridge pref is not - * assigned, release bridge nonpref MMIO. - */ - if (type & IORESOURCE_IO) - idx =3D 0; - else if (!(type & IORESOURCE_PREFETCH)) - idx =3D 1; - else if ((type & IORESOURCE_MEM_64) && - (b_res[2].flags & IORESOURCE_MEM_64)) - idx =3D 2; - else if (!(b_res[2].flags & IORESOURCE_MEM_64) && - (b_res[2].flags & IORESOURCE_PREFETCH)) - idx =3D 2; - else - idx =3D 1; - - r =3D &b_res[idx]; - - if (!r->parent) + if (!b_win->parent) return; =20 + idx =3D pci_resource_num(dev, b_win); + /* If there are children, release them all */ - release_child_resources(r); + release_child_resources(b_win); =20 - ret =3D pci_release_resource(dev, PCI_BRIDGE_RESOURCES + idx); + ret =3D pci_release_resource(dev, idx); if (ret) return; =20 - pci_setup_one_bridge_window(dev, PCI_BRIDGE_RESOURCES + idx); + pci_setup_one_bridge_window(dev, idx); } =20 enum release_type { @@ -1857,7 +1830,7 @@ enum release_type { * a larger window later. */ static void pci_bus_release_bridge_resources(struct pci_bus *bus, - unsigned long type, + struct resource *b_win, enum release_type rel_type) { struct pci_dev *dev; @@ -1865,6 +1838,8 @@ static void pci_bus_release_bridge_resources(struct p= ci_bus *bus, =20 list_for_each_entry(dev, &bus->devices, bus_list) { struct pci_bus *b =3D dev->subordinate; + struct resource *res; + if (!b) continue; =20 @@ -1873,9 +1848,15 @@ static void pci_bus_release_bridge_resources(struct = pci_bus *bus, if ((dev->class >> 8) !=3D PCI_CLASS_BRIDGE_PCI) continue; =20 - if (rel_type =3D=3D whole_subtree) - pci_bus_release_bridge_resources(b, type, - whole_subtree); + if (rel_type !=3D whole_subtree) + continue; + + pci_bus_for_each_resource(b, res) { + if (res->parent !=3D b_win) + continue; + + pci_bus_release_bridge_resources(b, res, whole_subtree); + } } =20 if (pci_is_root_bus(bus)) @@ -1885,7 +1866,7 @@ static void pci_bus_release_bridge_resources(struct p= ci_bus *bus, return; =20 if ((rel_type =3D=3D whole_subtree) || is_leaf_bridge) - pci_bridge_release_resources(bus, type); + pci_bridge_release_resources(bus, b_win); } =20 static void pci_bus_dump_res(struct pci_bus *bus) @@ -2282,9 +2263,13 @@ static void pci_prepare_next_assign_round(struct lis= t_head *fail_head, * enough to contain child device resources. */ list_for_each_entry(fail_res, fail_head, list) { - pci_bus_release_bridge_resources(fail_res->dev->bus, - fail_res->flags & PCI_RES_TYPE_MASK, - rel_type); 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d="scan'208";a="170548409" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.225]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2025 06:14:19 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v2 24/24] PCI: Alter misleading recursion to pci_bus_release_bridge_resources() Date: Fri, 29 Aug 2025 16:11:13 +0300 Message-Id: <20250829131113.36754-25-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> References: <20250829131113.36754-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Recursing into pci_bus_release_bridge_resources() should not alter rel_type because it makes no sense to change the release type within the recursion call chain. A literal "whole_subtree" is passed into the recursion instead of "rel_type" parameter which is misleading as the release type should remain the same throughout the entire operation. This is not a correctness issue because of the preceding if () that only allows the recursion to happen if rel_type is "whole_subtree". Still, replace the non-intuitive parameter with direct passing of "rel_type". Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/setup-bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 4ce747b5dea3..d264f16772b9 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1855,7 +1855,7 @@ static void pci_bus_release_bridge_resources(struct p= ci_bus *bus, if (res->parent !=3D b_win) continue; =20 - pci_bus_release_bridge_resources(b, res, whole_subtree); + pci_bus_release_bridge_resources(b, res, rel_type); } } =20 --=20 2.39.5