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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afefcbd7047sm188662166b.51.2025.08.29.05.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 05:23:01 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Philipp Zabel , Svyatoslav Ryhel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 4/4] ARM: tegra: Add DFLL clock support for Tegra114 Date: Fri, 29 Aug 2025 15:22:34 +0300 Message-ID: <20250829122235.119745-5-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250829122235.119745-1-clamor95@gmail.com> References: <20250829122235.119745-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DFLL clock node to common Tegra114 device tree along with clocks property to cpu node. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 4caf2073c556..a2a50f959927 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include =20 / { @@ -693,6 +694,29 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells =3D <1>; }; =20 + dfll: clock@70110000 { + compatible =3D "nvidia,tegra114-dfll"; + reg =3D <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_DFLL_SOC>, + <&tegra_car TEGRA114_CLK_DFLL_REF>, + <&tegra_car TEGRA114_CLK_I2C5>; + clock-names =3D "soc", "ref", "i2c"; + resets =3D <&tegra_car TEGRA114_RST_DFLL_DVCO>; + reset-names =3D "dvco"; + #clock-cells =3D <0>; + clock-output-names =3D "dfllCPU_out"; + nvidia,droop-ctrl =3D <0x00000f00>; + nvidia,force-mode =3D <1>; + nvidia,cf =3D <10>; + nvidia,ci =3D <0>; + nvidia,cg =3D <2>; + status =3D "disabled"; + }; + mmc@78000000 { compatible =3D "nvidia,tegra114-sdhci"; reg =3D <0x78000000 0x200>; @@ -824,6 +848,15 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <0>; + + clocks =3D <&tegra_car TEGRA114_CLK_CCLK_G>, + <&tegra_car TEGRA114_CLK_CCLK_LP>, + <&tegra_car TEGRA114_CLK_PLL_X>, + <&tegra_car TEGRA114_CLK_PLL_P>, + <&dfll>; + clock-names =3D "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency =3D <300000>; }; =20 cpu1: cpu@1 { --=20 2.48.1