From nobody Fri Oct 3 15:32:56 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D707830F944; Fri, 29 Aug 2025 09:21:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756459277; cv=none; b=rrBH2spFmo4eFobLZeco3WYVKwI729dReZn/0PRRuCL7N8tDjhm0Lz6AZ11vbSKlvl6HMn16EZ++41AVSgFTO8rmIEiiH6QnnX9zQ/b9rRDEBk/6WVb8wOv9qN+i9R1ip0BONj3Ekg52nsUYznGZRWhVch8F409A7LzpxxIwcrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756459277; c=relaxed/simple; bh=dEbei+EEkdau5s/TTeThppQDbwdigYRfoH9bUxrAvGU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NWwnp+Dhxcjktu9nrjHxVrookjU+oPMRgCYuTdK290S/0MnGKxopZCuDvVm+pC+D+rCuPzhoXSSzAzdd8dgqyiWo/190zWwNQtJaDjg4fmsU3gy30+DYD6RYjzn6JXcvR82odNjXXkrYjYxJrdwT+U3wGtwymDRqXlpbZVufn+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=JHNTs6iz; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="JHNTs6iz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756459273; bh=dEbei+EEkdau5s/TTeThppQDbwdigYRfoH9bUxrAvGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JHNTs6izvTJ+Qsdir/fxvLU2yv4YZypifjN/55hopCseAxZp4z40YNR3tRO8T5xIB LfwRvTkf1Hmv2RWMY2cza1RP72kt+vQtvCcZ0TgY16cTJNqLzkjkw+OvLNiL19rjSS MpxSy3M1HR5V6+9UZpw0725iAs8x4pfw1azB/08gYr7qL0VxF81b/jg66Jh12KDqRk uchm6SuZIgmR0tuKKaxd8K3Mq7MTmAXsTOQLw3mfTyGbDM0UXL+94y3Z47ekLBHmHl uiQitIEarTRmsBIn4iUcuv0aTSVYrzknu6lSp5U5Hh9gbYiXly2aKdiToTn+OYMiJK 9ojWTa/ETzdQw== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:f5b1:db54:a11a:c333]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9120D17E12BE; Fri, 29 Aug 2025 11:21:12 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH v5 16/27] clk: mediatek: Add MT8196 pextpsys clock support Date: Fri, 29 Aug 2025 11:19:02 +0200 Message-Id: <20250829091913.131528-17-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250829091913.131528-1-laura.nao@collabora.com> References: <20250829091913.131528-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the MT8196 pextpsys clock controller, which provides clock gate control for PCIe. Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Reviewed-by: Chen-Yu Tsai # CLK_OPS_PARENT_ENABLE remo= val --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8196-pextp.c | 131 ++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8196-pextp.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index d99c39a7f10e..c977719046a4 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -1010,6 +1010,13 @@ config COMMON_CLK_MT8196 help This driver supports MediaTek MT8196 basic clocks. =20 +config COMMON_CLK_MT8196_PEXTPSYS + tristate "Clock driver for MediaTek MT8196 pextpsys" + depends on COMMON_CLK_MT8196 + default COMMON_CLK_MT8196 + help + This driver supports MediaTek MT8196 pextpsys clocks. + config COMMON_CLK_MT8196_UFSSYS tristate "Clock driver for MediaTek MT8196 ufssys" depends on COMMON_CLK_MT8196 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 1a497de00846..88f7d8a229c2 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -153,6 +153,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) +=3D clk-mt8195-= wpe.o obj-$(CONFIG_COMMON_CLK_MT8196) +=3D clk-mt8196-apmixedsys.o clk-mt8196-to= pckgen.o \ clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \ clk-mt8196-peri_ao.o +obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) +=3D clk-mt8196-pextp.o obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) +=3D clk-mt8196-ufs_ao.o obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365-apmixedsys.o clk-mt8365.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) +=3D clk-mt8365-apu.o diff --git a/drivers/clk/mediatek/clk-mt8196-pextp.c b/drivers/clk/mediatek= /clk-mt8196-pextp.c new file mode 100644 index 000000000000..3e505ecc4b6e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8196-pextp.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao + */ +#include +#include + +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "reset.h" + +#define MT8196_PEXTP_RST0_SET_OFFSET 0x8 + +static const struct mtk_gate_regs pext_cg_regs =3D { + .set_ofs =3D 0x18, + .clr_ofs =3D 0x1c, + .sta_ofs =3D 0x14, +}; + +#define GATE_PEXT(_id, _name, _parent, _shift) {\ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &pext_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr,\ + } + +static const struct mtk_gate pext_clks[] =3D { + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_TL, "pext_pm0_tl", "tl", 0), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_REF, "pext_pm0_ref", "clk26m", 1), + GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_MCU_BUS, "pext_pp0_mcu_bus", "clk26m", 6), + GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF, "pext_pp0_pextp_ref", "clk26m"= , 7), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AXI_250, "pext_pm0_axi_250", "ufs_pexpt0_= mem_sub", 12), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AHB_APB, "pext_pm0_ahb_apb", "ufs_pextp0_= axi", 13), + GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_PL_P, "pext_pm0_pl_p", "clk26m", 14), + GATE_PEXT(CLK_PEXT_PEXTP_VLP_AO_P0_LP, "pext_pextp_vlp_ao_p0_lp", "clk26m= ", 19), +}; + +static u16 pext_rst_ofs[] =3D { MT8196_PEXTP_RST0_SET_OFFSET }; + +static u16 pext_rst_idx_map[] =3D { + [MT8196_PEXTP0_RST0_PCIE0_MAC] =3D 0, + [MT8196_PEXTP0_RST0_PCIE0_PHY] =3D 1, +}; + +static const struct mtk_clk_rst_desc pext_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D pext_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pext_rst_ofs), + .rst_idx_map =3D pext_rst_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(pext_rst_idx_map), +}; + +static const struct mtk_clk_desc pext_mcd =3D { + .clks =3D pext_clks, + .num_clks =3D ARRAY_SIZE(pext_clks), + .rst_desc =3D &pext_rst_desc, +}; + +static const struct mtk_gate pext1_clks[] =3D { + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_TL, "pext1_pm1_tl", "tl_p1", 0), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_REF, "pext1_pm1_ref", "clk26m", 1), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_TL, "pext1_pm2_tl", "tl_p2", 2), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_REF, "pext1_pm2_ref", "clk26m", 3), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS, "pext1_pp1_mcu_bus", "clk26m", = 8), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF, "pext1_pp1_pextp_ref", "clk26= m", 9), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS, "pext1_pp2_mcu_bus", "clk26m", = 10), + GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF, "pext1_pp2_pextp_ref", "clk26= m", 11), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AXI_250, "pext1_pm1_axi_250", + "pextp1_usb_axi", 16), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AHB_APB, "pext1_pm1_ahb_apb", + "pextp1_usb_mem_sub", 17), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_PL_P, "pext1_pm1_pl_p", "clk26m", 18), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AXI_250, "pext1_pm2_axi_250", + "pextp1_usb_axi", 19), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AHB_APB, "pext1_pm2_ahb_apb", + "pextp1_usb_mem_sub", 20), + GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_PL_P, "pext1_pm2_pl_p", "clk26m", 21), + GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P1_LP, "pext1_pextp_vlp_ao_p1_lp", "clk2= 6m", 26), + GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P2_LP, "pext1_pextp_vlp_ao_p2_lp", "clk2= 6m", 27), +}; + +static u16 pext1_rst_idx_map[] =3D { + [MT8196_PEXTP1_RST0_PCIE1_MAC] =3D 0, + [MT8196_PEXTP1_RST0_PCIE1_PHY] =3D 1, + [MT8196_PEXTP1_RST0_PCIE2_MAC] =3D 8, + [MT8196_PEXTP1_RST0_PCIE2_PHY] =3D 9, +}; + +static const struct mtk_clk_rst_desc pext1_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D pext_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pext_rst_ofs), + .rst_idx_map =3D pext1_rst_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(pext1_rst_idx_map), +}; + +static const struct mtk_clk_desc pext1_mcd =3D { + .clks =3D pext1_clks, + .num_clks =3D ARRAY_SIZE(pext1_clks), + .rst_desc =3D &pext1_rst_desc, +}; + +static const struct of_device_id of_match_clk_mt8196_pextp[] =3D { + { .compatible =3D "mediatek,mt8196-pextp0cfg-ao", .data =3D &pext_mcd }, + { .compatible =3D "mediatek,mt8196-pextp1cfg-ao", .data =3D &pext1_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_pextp); + +static struct platform_driver clk_mt8196_pextp_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8196-pextp", + .of_match_table =3D of_match_clk_mt8196_pextp, + }, +}; + +module_platform_driver(clk_mt8196_pextp_drv); +MODULE_DESCRIPTION("MediaTek MT8196 PCIe transmit phy clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5