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charset="utf-8" This adds debugfs entries and trace events to provide detailed debugging information. These enhancements help diagnose issues and improve debugging capabilities for the Wave6 core driver. Signed-off-by: Nas Chung Tested-by: Ming Qian --- .../platform/chips-media/wave6/wave6-trace.h | 286 ++++++++++++++++++ .../chips-media/wave6/wave6-vpu-dbg.c | 225 ++++++++++++++ .../chips-media/wave6/wave6-vpu-dbg.h | 14 + 3 files changed, 525 insertions(+) create mode 100644 drivers/media/platform/chips-media/wave6/wave6-trace.h create mode 100644 drivers/media/platform/chips-media/wave6/wave6-vpu-dbg.c create mode 100644 drivers/media/platform/chips-media/wave6/wave6-vpu-dbg.h diff --git a/drivers/media/platform/chips-media/wave6/wave6-trace.h b/drive= rs/media/platform/chips-media/wave6/wave6-trace.h new file mode 100644 index 000000000000..74227a059ca8 --- /dev/null +++ b/drivers/media/platform/chips-media/wave6/wave6-trace.h @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave6 series multi-standard codec IP - wave6 driver tracer + * + * Copyright (C) 2025 CHIPS&MEDIA INC + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM wave6 + +#if !defined(__WAVE6_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) +#define __WAVE6_TRACE_H__ + +#include +#include + +DECLARE_EVENT_CLASS(register_access, + TP_PROTO(struct device *dev, u32 addr, u32 value), + TP_ARGS(dev, addr, value), + TP_STRUCT__entry(__string(name, dev_name(dev)) + __field(u32, addr) + __field(u32, value)), + TP_fast_assign(__assign_str(name); + __entry->addr =3D addr; + __entry->value =3D value;), + TP_printk("%s:0x%03x 0x%08x", + __get_str(name), __entry->addr, __entry->value)); + +DEFINE_EVENT(register_access, writel, + TP_PROTO(struct device *dev, u32 addr, u32 value), + TP_ARGS(dev, addr, value)); +DEFINE_EVENT(register_access, readl, + TP_PROTO(struct device *dev, u32 addr, u32 value), + TP_ARGS(dev, addr, value)); + +TRACE_EVENT(send_command, + TP_PROTO(struct vpu_core_device *core, u32 id, u32 std, u32 cmd), + TP_ARGS(core, id, std, cmd), + TP_STRUCT__entry(__string(name, dev_name(core->dev)) + __field(u32, id) + __field(u32, std) + __field(u32, cmd)), + TP_fast_assign(__assign_str(name); + __entry->id =3D id; + __entry->std =3D std; + __entry->cmd =3D cmd;), + TP_printk("%s: inst id %d, std 0x%x, cmd 0x%x", + __get_str(name), __entry->id, + __entry->std, __entry->cmd)); + +TRACE_EVENT(irq, + TP_PROTO(struct vpu_core_device *core, u32 irq), + TP_ARGS(core, irq), + TP_STRUCT__entry(__string(name, dev_name(core->dev)) + __field(u32, irq)), + TP_fast_assign(__assign_str(name); + __entry->irq =3D irq;), + TP_printk("%s: irq 0x%x", __get_str(name), __entry->irq)); + +TRACE_EVENT(set_state, + TP_PROTO(struct vpu_instance *inst, u32 state), + TP_ARGS(inst, state), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __string(cur_state, wave6_vpu_instance_state_name(inst->state)) + __string(nxt_state, wave6_vpu_instance_state_name(state))), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __assign_str(cur_state); + __assign_str(nxt_state);), + TP_printk("%s: inst[%d] set state %s -> %s", + __get_str(name), __entry->id, + __get_str(cur_state), __get_str(nxt_state))); + +DECLARE_EVENT_CLASS(inst_internal, + TP_PROTO(struct vpu_instance *inst, bool is_out), + TP_ARGS(inst, is_out), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __string(type, is_out ? "output" : "capture") + __field(u32, pixelformat) + __field(u32, width) + __field(u32, height) + __field(u32, buf_cnt_src) + __field(u32, buf_cnt_dst) + __field(u32, processed_cnt) + __field(u32, error_cnt)), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __assign_str(type); + __entry->pixelformat =3D is_out ? inst->src_fmt.pixelformat : + inst->dst_fmt.pixelformat; + __entry->width =3D is_out ? inst->src_fmt.width : + inst->dst_fmt.width; + __entry->height =3D is_out ? inst->src_fmt.height : + inst->dst_fmt.height; + __entry->buf_cnt_src =3D inst->queued_src_buf_num; + __entry->buf_cnt_dst =3D inst->queued_dst_buf_num; + __entry->processed_cnt =3D inst->processed_buf_num; + __entry->error_cnt =3D inst->error_buf_num;), + TP_printk("%s: inst[%d] %s %c%c%c%c %dx%d, input %d, %d, process %d,= error %d", + __get_str(name), __entry->id, __get_str(type), + __entry->pixelformat, + __entry->pixelformat >> 8, + __entry->pixelformat >> 16, + __entry->pixelformat >> 24, + __entry->width, __entry->height, + __entry->buf_cnt_src, __entry->buf_cnt_dst, + __entry->processed_cnt, __entry->error_cnt)); + +DEFINE_EVENT(inst_internal, start_streaming, + TP_PROTO(struct vpu_instance *inst, bool is_out), + TP_ARGS(inst, is_out)); + +DEFINE_EVENT(inst_internal, stop_streaming, + TP_PROTO(struct vpu_instance *inst, bool is_out), + TP_ARGS(inst, is_out)); + +TRACE_EVENT(dec_pic, + TP_PROTO(struct vpu_instance *inst, u32 srcidx, u32 size), + TP_ARGS(inst, srcidx, size), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __field(u32, srcidx) + __field(u32, start) + __field(u32, size)), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __entry->srcidx =3D srcidx; + __entry->start =3D inst->codec_info->dec_info.stream_rd_ptr; + __entry->size =3D size;), + TP_printk("%s: inst[%d] src[%2d] %8x, %d", + __get_str(name), __entry->id, + __entry->srcidx, __entry->start, __entry->size)); + +TRACE_EVENT(source_change, + TP_PROTO(struct vpu_instance *inst, struct dec_seq_info *info), + TP_ARGS(inst, info), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __field(u32, width) + __field(u32, height) + __field(u32, profile) + __field(u32, level) + __field(u32, tier) + __field(u32, min_fb_cnt) + __field(u32, disp_delay) + __field(u32, quantization) + __field(u32, colorspace) + __field(u32, xfer_func) + __field(u32, ycbcr_enc)), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __entry->width =3D info->pic_width, + __entry->height =3D info->pic_height, + __entry->profile =3D info->profile, + __entry->level =3D info->level; + __entry->tier =3D info->tier; + __entry->min_fb_cnt =3D info->min_frame_buffer_count; + __entry->disp_delay =3D info->frame_buf_delay; + __entry->quantization =3D inst->quantization; + __entry->colorspace =3D inst->colorspace; + __entry->xfer_func =3D inst->xfer_func; + __entry->ycbcr_enc =3D inst->ycbcr_enc;), + TP_printk("%s: inst[%d] %dx%d profile %d %d %d min_fb %d delay %d col= or %d %d %d %d", + __get_str(name), __entry->id, + __entry->width, __entry->height, + __entry->profile, __entry->level, __entry->tier, + __entry->min_fb_cnt, __entry->disp_delay, + __entry->quantization, __entry->colorspace, + __entry->xfer_func, __entry->ycbcr_enc)); + +TRACE_EVENT(dec_done, + TP_PROTO(struct vpu_instance *inst, struct dec_output_info *info), + TP_ARGS(inst, info), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __field(u32, dec_flag) + __field(u32, dec_poc) + __field(u32, disp_flag) + __field(u32, disp_cnt) + __field(u32, rel_cnt) + __field(u32, src_ch) + __field(u32, eos) + __field(u32, error) + __field(u32, warn)), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __entry->dec_flag =3D info->frame_decoded; + __entry->dec_poc =3D info->decoded_poc; + __entry->disp_flag =3D info->frame_display; + __entry->disp_cnt =3D info->disp_frame_num; + __entry->rel_cnt =3D info->release_disp_frame_num; + __entry->src_ch =3D info->notification_flags & DEC_NOTI_FLAG_SEQ_CHA= NGE; + __entry->eos =3D info->stream_end; + __entry->error =3D info->error_reason; + __entry->warn =3D info->warn_info;), + TP_printk("%s: inst[%d] dec %d %d disp %d(%d) rel %d src_ch %d eos %d= error 0x%x 0x%x", + __get_str(name), __entry->id, + __entry->dec_flag, __entry->dec_poc, + __entry->disp_flag, __entry->disp_cnt, + __entry->rel_cnt, + __entry->src_ch, __entry->eos, + __entry->error, __entry->warn)); + +TRACE_EVENT(enc_pic, + TP_PROTO(struct vpu_instance *inst, struct enc_param *param), + TP_ARGS(inst, param), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __field(u32, srcidx) + __field(u32, buf_y) + __field(u32, buf_cb) + __field(u32, buf_cr) + __field(u32, stride) + __field(u32, buf_strm) + __field(u32, size_strm) + __field(u32, force_type_enable) + __field(u32, force_type) + __field(u32, end_flag)), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __entry->srcidx =3D param->src_idx; + __entry->buf_y =3D param->source_frame->buf_y; + __entry->buf_cb =3D param->source_frame->buf_cb; + __entry->buf_cr =3D param->source_frame->buf_cr; + __entry->stride =3D param->source_frame->stride; + __entry->buf_strm =3D param->pic_stream_buffer_addr; + __entry->size_strm =3D param->pic_stream_buffer_size; + __entry->force_type_enable =3D param->force_pic; + __entry->force_type =3D param->force_pic_type; + __entry->end_flag =3D param->src_end;), + TP_printk("%s: inst[%d] src[%2d] %8x %8x %8x(%d) dst %8x(%d) force ty= pe %d(%d) end %d", + __get_str(name), __entry->id, __entry->srcidx, + __entry->buf_y, __entry->buf_cb, __entry->buf_cr, + __entry->stride, __entry->buf_strm, __entry->size_strm, + __entry->force_type_enable, __entry->force_type, + __entry->end_flag)); + +TRACE_EVENT(enc_done, + TP_PROTO(struct vpu_instance *inst, struct enc_output_info *info), + TP_ARGS(inst, info), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __field(u32, srcidx) + __field(u32, frmidx) + __field(u32, size) + __field(u32, type) + __field(u32, avg_qp)), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __entry->srcidx =3D info->enc_src_idx; + __entry->frmidx =3D info->recon_frame_index; + __entry->size =3D info->bitstream_size; + __entry->type =3D info->pic_type; + __entry->avg_qp =3D info->avg_ctu_qp;), + TP_printk("%s: inst[%d] src %d, frame %d, size %d, type %d, qp %d, eo= s %d", + __get_str(name), __entry->id, + __entry->srcidx, __entry->frmidx, + __entry->size, __entry->type, __entry->avg_qp, + __entry->frmidx =3D=3D RECON_IDX_FLAG_ENC_END)); + +TRACE_EVENT(s_ctrl, + TP_PROTO(struct vpu_instance *inst, struct v4l2_ctrl *ctrl), + TP_ARGS(inst, ctrl), + TP_STRUCT__entry(__string(name, dev_name(inst->dev->dev)) + __field(u32, id) + __string(ctrl_name, ctrl->name) + __field(u32, val)), + TP_fast_assign(__assign_str(name); + __entry->id =3D inst->id; + __assign_str(ctrl_name); + __entry->val =3D ctrl->val;), + TP_printk("%s: inst[%d] %s =3D %d", + __get_str(name), __entry->id, + __get_str(ctrl_name), __entry->val)); + +#endif /* __WAVE6_TRACE_H__ */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE wave6-trace + +/* This part must be outside protection */ +#include diff --git a/drivers/media/platform/chips-media/wave6/wave6-vpu-dbg.c b/dri= vers/media/platform/chips-media/wave6/wave6-vpu-dbg.c new file mode 100644 index 000000000000..7f04060f0aea --- /dev/null +++ b/drivers/media/platform/chips-media/wave6/wave6-vpu-dbg.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave6 series multi-standard codec IP - debug interface + * + * Copyright (C) 2025 CHIPS&MEDIA INC + */ + +#include +#include +#include "wave6-vpu-core.h" +#include "wave6-vpu-dbg.h" + +static int wave6_vpu_dbg_instance(struct seq_file *s, void *data) +{ + struct vpu_instance *inst =3D s->private; + struct vpu_performance_info *perf =3D &inst->performance; + struct vb2_queue *vq; + char str[128]; + int num; + s64 tmp; + s64 fps; + + if (!inst->v4l2_fh.m2m_ctx) + return 0; + + num =3D scnprintf(str, sizeof(str), "[%s]\n", + inst->type =3D=3D VPU_INST_TYPE_DEC ? "Decoder" : "Encoder"); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), "%s : product 0x%x, fw_ver %d.%d.%d(r= %d), hw_ver 0x%x\n", + dev_name(inst->dev->dev), + inst->dev->attr.product_code, + FW_VERSION_MAJOR(inst->dev->attr.fw_version), + FW_VERSION_MINOR(inst->dev->attr.fw_version), + FW_VERSION_REL(inst->dev->attr.fw_version), + inst->dev->attr.fw_revision, + inst->dev->attr.hw_version); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), "state =3D %s\n", + wave6_vpu_instance_state_name(inst->state)); + if (seq_write(s, str, num)) + return 0; + + vq =3D v4l2_m2m_get_src_vq(inst->v4l2_fh.m2m_ctx); + num =3D scnprintf(str, sizeof(str), + "output (%2d, %2d): fmt =3D %c%c%c%c %d x %d, %d;\n", + vb2_is_streaming(vq), + vb2_get_num_buffers(vq), + inst->src_fmt.pixelformat, + inst->src_fmt.pixelformat >> 8, + inst->src_fmt.pixelformat >> 16, + inst->src_fmt.pixelformat >> 24, + inst->src_fmt.width, + inst->src_fmt.height, + vq->last_buffer_dequeued); + if (seq_write(s, str, num)) + return 0; + + vq =3D v4l2_m2m_get_dst_vq(inst->v4l2_fh.m2m_ctx); + num =3D scnprintf(str, sizeof(str), + "capture(%2d, %2d): fmt =3D %c%c%c%c %d x %d, %d;\n", + vb2_is_streaming(vq), + vb2_get_num_buffers(vq), + inst->dst_fmt.pixelformat, + inst->dst_fmt.pixelformat >> 8, + inst->dst_fmt.pixelformat >> 16, + inst->dst_fmt.pixelformat >> 24, + inst->dst_fmt.width, + inst->dst_fmt.height, + vq->last_buffer_dequeued); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), "crop: (%d, %d) %d x %d\n", + inst->crop.left, + inst->crop.top, + inst->crop.width, + inst->crop.height); + if (seq_write(s, str, num)) + return 0; + + if (inst->scaler_info.enable) { + num =3D scnprintf(str, sizeof(str), "scale: %d x %d\n", + inst->scaler_info.width, inst->scaler_info.height); + if (seq_write(s, str, num)) + return 0; + } + + num =3D scnprintf(str, sizeof(str), + "queued src %d, dst %d, process %d, sequence %d, error %d, drain %d:%d\= n", + inst->queued_src_buf_num, + inst->queued_dst_buf_num, + inst->processed_buf_num, + inst->sequence, + inst->error_buf_num, + inst->v4l2_fh.m2m_ctx->out_q_ctx.buffered, + inst->eos); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), "fps"); + if (seq_write(s, str, num)) + return 0; + tmp =3D MSEC_PER_SEC * inst->processed_buf_num; + if (perf->ts_last > perf->ts_first + NSEC_PER_MSEC) { + fps =3D DIV_ROUND_CLOSEST(tmp, (perf->ts_last - perf->ts_first) / NSEC_P= ER_MSEC); + num =3D scnprintf(str, sizeof(str), " actual: %lld;", fps); + if (seq_write(s, str, num)) + return 0; + } + if (perf->total_sw_time) { + fps =3D DIV_ROUND_CLOSEST(tmp, perf->total_sw_time / NSEC_PER_MSEC); + num =3D scnprintf(str, sizeof(str), " sw: %lld;", fps); + if (seq_write(s, str, num)) + return 0; + } + if (perf->total_hw_time) { + fps =3D DIV_ROUND_CLOSEST(tmp, perf->total_hw_time / NSEC_PER_MSEC); + num =3D scnprintf(str, sizeof(str), " hw: %lld", fps); + if (seq_write(s, str, num)) + return 0; + } + num =3D scnprintf(str, sizeof(str), "\n"); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), + "latency(ms) first: %llu.%06llu, max %llu.%06llu, setup %llu.%06llu\n", + perf->latency_first / NSEC_PER_MSEC, + perf->latency_first % NSEC_PER_MSEC, + perf->latency_max / NSEC_PER_MSEC, + perf->latency_max % NSEC_PER_MSEC, + (perf->ts_first - perf->ts_start) / NSEC_PER_MSEC, + (perf->ts_first - perf->ts_start) % NSEC_PER_MSEC); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), + "process frame time(ms) min: %llu.%06llu, max %llu.%06llu\n", + perf->min_process_time / NSEC_PER_MSEC, + perf->min_process_time % NSEC_PER_MSEC, + perf->max_process_time / NSEC_PER_MSEC, + perf->max_process_time % NSEC_PER_MSEC); + if (seq_write(s, str, num)) + return 0; + + if (inst->type =3D=3D VPU_INST_TYPE_DEC) { + num =3D scnprintf(str, sizeof(str), "%s order\n", + inst->disp_mode =3D=3D DISP_MODE_DISP_ORDER ? "display" : "decode"); + if (seq_write(s, str, num)) + return 0; + } else { + struct enc_info *p_enc_info =3D &inst->codec_info->enc_info; + struct enc_codec_param *param =3D &p_enc_info->open_param.codec_param; + + num =3D scnprintf(str, sizeof(str), "profile %d, level %d, tier %d\n", + param->profile, param->level, param->tier); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), "frame_rate %d, idr_period %d, intra= _period %d\n", + param->frame_rate, param->idr_period, param->intra_period); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), "rc %d, mode %d, bitrate %d\n", + param->en_rate_control, + param->rc_mode, + param->bitrate); + if (seq_write(s, str, num)) + return 0; + + num =3D scnprintf(str, sizeof(str), + "qp %d, i_qp [%d, %d], p_qp [%d, %d], b_qp [%d, %d]\n", + param->qp, + param->min_qp_i, param->max_qp_i, + param->min_qp_p, param->max_qp_p, + param->min_qp_b, param->max_qp_b); + if (seq_write(s, str, num)) + return 0; + } + + return 0; +} + +static int wave6_vpu_dbg_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, wave6_vpu_dbg_instance, inode->i_private); +} + +static const struct file_operations wave6_vpu_dbg_fops =3D { + .owner =3D THIS_MODULE, + .open =3D wave6_vpu_dbg_open, + .release =3D single_release, + .read =3D seq_read, +}; + +int wave6_vpu_create_dbgfs_file(struct vpu_instance *inst) +{ + char name[64]; + + if (WARN_ON(!inst || !inst->dev || IS_ERR_OR_NULL(inst->dev->debugfs))) + return -EINVAL; + + scnprintf(name, sizeof(name), "instance.%d", inst->id); + inst->debugfs =3D debugfs_create_file((const char *)name, + VERIFY_OCTAL_PERMISSIONS(0444), + inst->dev->debugfs, + inst, + &wave6_vpu_dbg_fops); + + return 0; +} + +void wave6_vpu_remove_dbgfs_file(struct vpu_instance *inst) +{ + if (WARN_ON(!inst || !inst->debugfs)) + return; + + debugfs_remove(inst->debugfs); + inst->debugfs =3D NULL; +} diff --git a/drivers/media/platform/chips-media/wave6/wave6-vpu-dbg.h b/dri= vers/media/platform/chips-media/wave6/wave6-vpu-dbg.h new file mode 100644 index 000000000000..6453eb2de76f --- /dev/null +++ b/drivers/media/platform/chips-media/wave6/wave6-vpu-dbg.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave6 series multi-standard codec IP - debug interface + * + * Copyright (C) 2025 CHIPS&MEDIA INC + */ + +#ifndef __WAVE6_VPU_DBG_H__ +#define __WAVE6_VPU_DBG_H__ + +int wave6_vpu_create_dbgfs_file(struct vpu_instance *inst); +void wave6_vpu_remove_dbgfs_file(struct vpu_instance *inst); + +#endif /* __WAVE6_VPU_DBG_H__ */ --=20 2.31.1