From nobody Fri Oct 3 14:29:34 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96BBB2153E1 for ; Fri, 29 Aug 2025 05:32:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756445570; cv=none; b=RMiyUa3mJD//+fIqOX1aw6GplYWI4tpbMSG6oUQmrZLB7jdFQvuQ/yf+Jfz4f6diQXCdu/kw2KabmivPzG6JSmiE/PoG1jpvkMWEwc4sjJudW9eJfEPebc7NB4oxPlqcMrhQgXY95p5q0KUAhaX/q/yE5bF5zILrNRjfLr0ZXZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756445570; c=relaxed/simple; bh=qhzqJB8xjjx7hDGsiqNEPrBT+3QQAgj7yc0dso5UGtc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Content-Type; b=iR9Ahq0BghKHe08kq9CnXltKiHV7alImcJisVj/LdqXBtmzcTL9QDrh6DCS+YD5tx+ckql4LYCR8qUP5qdNoiDGw2nMj6Qf2PCRxskJ4BGGdVlFWsuwR41HG45m2e+Vc0rA8GJhwL3t+Ajt3wJmUWpvsI4AEDuGd6+sPdZUiIlk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=OmNaOEqw; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="OmNaOEqw" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-24457ef983fso34128525ad.0 for ; Thu, 28 Aug 2025 22:32:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1756445568; x=1757050368; darn=vger.kernel.org; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=tpvVsEm8uCiz3vvKLatxB4dMae1DpSClGqRKsbH6ivQ=; b=OmNaOEqwUX4zzmqypzZDqE2uAnksfqCHIzxygyQAq5haJ4u6WZ63EtsGRBQu12KrxP 2dRemGavE6ULbFS85GzdsVrsBJH1Ms+E0lMz1ABbRcQ/wIOkdLT/B/pPG3dEhCm1m1LB 6Jnndt+jx2fyVLj1UYX2yY4WQcqFCvhxyuMN+4sPZsKC0PnC+WKno/wGCURtQHLoenCq VWiHpkKWn+iJf4tX6/poYyaz96AqNmOMJOsb4EiAzJ+IzNMZIaBpRYBrITE2rq70YoBl 3H4dN+kswFIRb+Cc5egxp3c+9TZLw1hyLWV0vYa/CUvXjtLkeiF6UmHQ6Ovl19kh5gRO tQ8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756445568; x=1757050368; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=tpvVsEm8uCiz3vvKLatxB4dMae1DpSClGqRKsbH6ivQ=; b=Bl12f9xtYhzM7rcyCOTuu2LBzcvbwDomwBZcoz0Ks7c2QlRhbYD2JmiUDczkpll/1i oARRP98fRfK1uV9XM0Fjw2rboVmserm18g5wPkYqVsCCBd/H17RCbTT+cFVnQuVjcPS6 8B0zBTQpXSAVwqGiEhA04odO73YkHkh1KNyaPXz8XelMDiwQZwworWOGfhJgo4ymsehc eX5A4sU8Zn7AZIN0A/EcrI0vGHn3D1VbK8aZ1fzEdCVSzQ/qt/viS5WFBK8mHD4W34DG M9noBDeRmRvYgIPbX0lS7CBwl/LAtiS87/nmt8kVhcQpLdv86SSmjNueJWL1B6gvXk/y xDkA== X-Forwarded-Encrypted: i=1; AJvYcCXQ/MtL3yohM5zVuWiT8GRk3u7cCl9hEMd6TZps8R1u4pIdEw1lGTzU/5y3azgex+rT1TZ5+NDOw4DIaLU=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6yEZec/A16105ud9cxj0I9JCzw0efSAvNRzIUlI40TMDW3RSA 00C0Kwg1UwD5GPjrh38DFoBvOp6fnjw0LgaxgWevSQgGAcpCkM91QSzIsABH1LOPP+V9tg0w+8j arsoRipr0bQ== X-Google-Smtp-Source: AGHT+IEuURIFdhc60Y7oiueRhiGe3lniJZNN2qIl7eyAybDR/lYTz6yTkgMcOHrIV8zSjhUwXzxVb1x9NUmN X-Received: from plry17.prod.google.com ([2002:a17:902:b491:b0:248:6b51:1364]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:1a43:b0:246:adf0:c32e with SMTP id d9443c01a7336-246adf0c686mr237822065ad.40.1756445567979; Thu, 28 Aug 2025 22:32:47 -0700 (PDT) Date: Thu, 28 Aug 2025 22:32:33 -0700 In-Reply-To: <20250829053235.21994-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250829053235.21994-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.318.gd7df087d1a-goog Message-ID: <20250829053235.21994-2-irogers@google.com> Subject: [PATCH v5 1/3] perf jevents: Add collection of topdown like metrics for arm64 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Leo Yan Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Metrics are created using legacy, common and recommended events. As events may be missing a TryEvent function will give None if an event is missing. To workaround missing JSON events for cortex-a53, sysfs encodings are used. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arm64_metrics.py | 148 ++++++++++++++++++++++++- 1 file changed, 144 insertions(+), 4 deletions(-) diff --git a/tools/perf/pmu-events/arm64_metrics.py b/tools/perf/pmu-events= /arm64_metrics.py index c9aa2d827a82..067ebbad1adf 100755 --- a/tools/perf/pmu-events/arm64_metrics.py +++ b/tools/perf/pmu-events/arm64_metrics.py @@ -1,14 +1,152 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) -from metric import (JsonEncodeMetric, JsonEncodeMetricGroupDescriptions, L= oadEvents, - MetricGroup) +from metric import (d_ratio, Event, JsonEncodeMetric, JsonEncodeMetricGrou= pDescriptions, + LoadEvents, Metric, MetricGroup) import argparse import json import os +from typing import Optional =20 # Global command line arguments. _args =3D None =20 +def Arm64Topdown() -> MetricGroup: + """Returns a MetricGroup representing ARM64 topdown like metrics.""" + def TryEvent(name: str) -> Optional[Event]: + # Skip an event if not in the json files. + try: + return Event(name) + except: + return None + # ARM models like a53 lack JSON for INST_RETIRED but have the + # architetural standard event in sysfs. Use the PMU name to identify + # the sysfs event. + pmu_name =3D f'armv8_{_args.model.replace("-", "_")}' + ins =3D Event("instructions") + ins_ret =3D Event("INST_RETIRED", f"{pmu_name}/inst_retired/") + cycles =3D Event("cycles") + stall_fe =3D TryEvent("STALL_FRONTEND") + stall_be =3D TryEvent("STALL_BACKEND") + br_ret =3D TryEvent("BR_RETIRED") + br_mp_ret =3D TryEvent("BR_MIS_PRED_RETIRED") + dtlb_walk =3D TryEvent("DTLB_WALK") + itlb_walk =3D TryEvent("ITLB_WALK") + l1d_tlb =3D TryEvent("L1D_TLB") + l1i_tlb =3D TryEvent("L1I_TLB") + l1d_refill =3D Event("L1D_CACHE_REFILL", f"{pmu_name}/l1d_cache_refill/") + l2d_refill =3D Event("L2D_CACHE_REFILL", f"{pmu_name}/l2d_cache_refill/") + l1i_refill =3D Event("L1I_CACHE_REFILL", f"{pmu_name}/l1i_cache_refill/") + l1d_access =3D Event("L1D_CACHE", f"{pmu_name}/l1d_cache/") + l2d_access =3D Event("L2D_CACHE", f"{pmu_name}/l2d_cache/") + llc_access =3D TryEvent("LL_CACHE_RD") + l1i_access =3D Event("L1I_CACHE", f"{pmu_name}/l1i_cache/") + llc_miss_rd =3D TryEvent("LL_CACHE_MISS_RD") + ase_spec =3D TryEvent("ASE_SPEC") + ld_spec =3D TryEvent("LD_SPEC") + st_spec =3D TryEvent("ST_SPEC") + vfp_spec =3D TryEvent("VFP_SPEC") + dp_spec =3D TryEvent("DP_SPEC") + br_immed_spec =3D TryEvent("BR_IMMED_SPEC") + br_indirect_spec =3D TryEvent("BR_INDIRECT_SPEC") + br_ret_spec =3D TryEvent("BR_RETURN_SPEC") + crypto_spec =3D TryEvent("CRYPTO_SPEC") + inst_spec =3D TryEvent("INST_SPEC") + + return MetricGroup("lpm_topdown", [ + MetricGroup("lpm_topdown_tl", [ + Metric("lpm_topdown_tl_ipc", "Instructions per cycle", d_ratio( + ins, cycles), "insn/cycle"), + Metric("lpm_topdown_tl_stall_fe_rate", "Frontend stalls to all c= ycles", + d_ratio(stall_fe, cycles), "100%") if stall_fe else None, + Metric("lpm_topdown_tl_stall_be_rate", "Backend stalls to all cy= cles", + d_ratio(stall_be, cycles), "100%") if stall_be else None, + ]), + MetricGroup("lpm_topdown_fe_bound", [ + MetricGroup("lpm_topdown_fe_br", [ + Metric("lpm_topdown_fe_br_mp_per_insn", + "Branch mispredicts per instruction retired", + d_ratio(br_mp_ret, ins_ret), "br/insn") if br_mp_ret = else None, + Metric("lpm_topdown_fe_br_ins_rate", + "Branches per instruction retired", d_ratio( + br_ret, ins_ret), "100%") if br_ret else None, + Metric("lpm_topdown_fe_br_mispredict", + "Branch mispredicts per branch instruction", + d_ratio(br_mp_ret, br_ret), "100%") if (br_mp_ret and= br_ret) else None, + ]), + MetricGroup("lpm_topdown_fe_itlb", [ + Metric("lpm_topdown_fe_itlb_walks", "Itlb walks per insn", + d_ratio(itlb_walk, ins_ret), "walk/insn"), + Metric("lpm_topdown_fe_itlb_walk_rate", "Itlb walks per L1I = TLB access", + d_ratio(itlb_walk, l1i_tlb) if l1i_tlb else None, "10= 0%"), + ]) if itlb_walk else None, + MetricGroup("lpm_topdown_fe_icache", [ + Metric("lpm_topdown_fe_icache_l1i_per_insn", + "L1I cache refills per instruction", + d_ratio(l1i_refill, ins_ret), "l1i/insn"), + Metric("lpm_topdown_fe_icache_l1i_miss_rate", + "L1I cache refills per L1I cache access", + d_ratio(l1i_refill, l1i_access), "100%"), + ]), + ]), + MetricGroup("lpm_topdown_be_bound", [ + MetricGroup("lpm_topdown_be_dtlb", [ + Metric("lpm_topdown_be_dtlb_walks", "Dtlb walks per instruct= ion", + d_ratio(dtlb_walk, ins_ret), "walk/insn"), + Metric("lpm_topdown_be_dtlb_walk_rate", "Dtlb walks per L1D = TLB access", + d_ratio(dtlb_walk, l1d_tlb) if l1d_tlb else None, "10= 0%"), + ]) if dtlb_walk else None, + MetricGroup("lpm_topdown_be_mix", [ + Metric("lpm_topdown_be_mix_ld", "Percentage of load instruct= ions", + d_ratio(ld_spec, inst_spec), "100%") if ld_spec else = None, + Metric("lpm_topdown_be_mix_st", "Percentage of store instruc= tions", + d_ratio(st_spec, inst_spec), "100%") if st_spec else = None, + Metric("lpm_topdown_be_mix_simd", "Percentage of SIMD instru= ctions", + d_ratio(ase_spec, inst_spec), "100%") if ase_spec els= e None, + Metric("lpm_topdown_be_mix_fp", + "Percentage of floating point instructions", + d_ratio(vfp_spec, inst_spec), "100%") if vfp_spec els= e None, + Metric("lpm_topdown_be_mix_dp", + "Percentage of data processing instructions", + d_ratio(dp_spec, inst_spec), "100%") if dp_spec else = None, + Metric("lpm_topdown_be_mix_crypto", + "Percentage of data processing instructions", + d_ratio(crypto_spec, inst_spec), "100%") if crypto_sp= ec else None, + Metric( + "lpm_topdown_be_mix_br", "Percentage of branch instructi= ons", + d_ratio(br_immed_spec + br_indirect_spec + br_ret_spec, + inst_spec), "100%") if br_immed_spec and br_indi= rect_spec and br_ret_spec else None, + ], description=3D"Breakdown of instructions by type. Counts incl= ude both useful and wasted speculative instructions" + ) if inst_spec else None, + MetricGroup("lpm_topdown_be_dcache", [ + MetricGroup("lpm_topdown_be_dcache_l1", [ + Metric("lpm_topdown_be_dcache_l1_per_insn", + "L1D cache refills per instruction", + d_ratio(l1d_refill, ins_ret), "refills/insn"), + Metric("lpm_topdown_be_dcache_l1_miss_rate", + "L1D cache refills per L1D cache access", + d_ratio(l1d_refill, l1d_access), "100%") + ]), + MetricGroup("lpm_topdown_be_dcache_l2", [ + Metric("lpm_topdown_be_dcache_l2_per_insn", + "L2D cache refills per instruction", + d_ratio(l2d_refill, ins_ret), "refills/insn"), + Metric("lpm_topdown_be_dcache_l2_miss_rate", + "L2D cache refills per L2D cache access", + d_ratio(l2d_refill, l2d_access), "100%") + ]), + MetricGroup("lpm_topdown_be_dcache_llc", [ + Metric("lpm_topdown_be_dcache_llc_per_insn", + "Last level cache misses per instruction", + d_ratio(llc_miss_rd, ins_ret), "miss/insn"), + Metric("lpm_topdown_be_dcache_llc_miss_rate", + "Last level cache misses per last level cache acc= ess", + d_ratio(llc_miss_rd, llc_access), "100%") + ]) if llc_miss_rd and llc_access else None, + ]), + ]), + ]) + + def main() -> None: global _args =20 @@ -29,11 +167,13 @@ def main() -> None: ) _args =3D parser.parse_args() =20 - all_metrics =3D MetricGroup("",[]) - directory =3D f"{_args.events_path}/arm64/{_args.vendor}/{_args.model}/" LoadEvents(directory) =20 + all_metrics =3D MetricGroup("",[ + Arm64Topdown(), + ]) + if _args.metricgroups: print(JsonEncodeMetricGroupDescriptions(all_metrics)) else: --=20 2.51.0.318.gd7df087d1a-goog From nobody Fri Oct 3 14:29:34 2025 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94829220686 for ; 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Thu, 28 Aug 2025 22:32:49 -0700 (PDT) Date: Thu, 28 Aug 2025 22:32:34 -0700 In-Reply-To: <20250829053235.21994-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250829053235.21994-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.318.gd7df087d1a-goog Message-ID: <20250829053235.21994-3-irogers@google.com> Subject: [PATCH v5 2/3] perf jevents: Add cycles breakdown metric for arm64/AMD/Intel From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Leo Yan Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Breakdown cycles to user, kernel and guest. Add a common_metrics.py file for such metrics. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/Build | 2 +- tools/perf/pmu-events/amd_metrics.py | 3 +++ tools/perf/pmu-events/arm64_metrics.py | 2 ++ tools/perf/pmu-events/common_metrics.py | 18 ++++++++++++++++++ tools/perf/pmu-events/intel_metrics.py | 2 ++ tools/perf/pmu-events/metric.py | 1 + 6 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 tools/perf/pmu-events/common_metrics.py diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build index 366cd720659a..b2c557ad9964 100644 --- a/tools/perf/pmu-events/Build +++ b/tools/perf/pmu-events/Build @@ -43,7 +43,7 @@ $(LEGACY_CACHE_JSON): $(LEGACY_CACHE_PY) $(call rule_mkdir) $(Q)$(call echo-cmd,gen)$(PYTHON) $(LEGACY_CACHE_PY) > $@ =20 -GEN_METRIC_DEPS :=3D pmu-events/metric.py +GEN_METRIC_DEPS :=3D pmu-events/metric.py pmu-events/common_metrics.py =20 # Generate AMD Json ZENS =3D $(shell ls -d pmu-events/arch/x86/amdzen*) diff --git a/tools/perf/pmu-events/amd_metrics.py b/tools/perf/pmu-events/a= md_metrics.py index d51f4c3fe0cb..2252894633b0 100755 --- a/tools/perf/pmu-events/amd_metrics.py +++ b/tools/perf/pmu-events/amd_metrics.py @@ -4,6 +4,7 @@ from metric import (d_ratio, has_event, max, Event, JsonEnc= odeMetric, JsonEncodeMetricGroupDescriptions, Literal, LoadEvents, Metric, MetricGroup, Select) import argparse +from common_metrics import Cycles import json import math import os @@ -594,6 +595,7 @@ def AmdUpc() -> Metric: return Metric("lpm_upc", "Micro-ops retired per core cycle (higher is be= tter)", upc, "uops/cycle") =20 + def Idle() -> Metric: cyc =3D Event("msr/mperf/") tsc =3D Event("msr/tsc/") @@ -676,6 +678,7 @@ def main() -> None: AmdSwpf(), AmdUopCache(), AmdUpc(), + Cycles(), Idle(), Rapl(), UncoreL3(), diff --git a/tools/perf/pmu-events/arm64_metrics.py b/tools/perf/pmu-events= /arm64_metrics.py index 067ebbad1adf..5e9b37693a8d 100755 --- a/tools/perf/pmu-events/arm64_metrics.py +++ b/tools/perf/pmu-events/arm64_metrics.py @@ -3,6 +3,7 @@ from metric import (d_ratio, Event, JsonEncodeMetric, JsonEncodeMetricGrou= pDescriptions, LoadEvents, Metric, MetricGroup) import argparse +from common_metrics import Cycles import json import os from typing import Optional @@ -172,6 +173,7 @@ def main() -> None: =20 all_metrics =3D MetricGroup("",[ Arm64Topdown(), + Cycles(), ]) =20 if _args.metricgroups: diff --git a/tools/perf/pmu-events/common_metrics.py b/tools/perf/pmu-event= s/common_metrics.py new file mode 100644 index 000000000000..6a44e5756cbb --- /dev/null +++ b/tools/perf/pmu-events/common_metrics.py @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) +from metric import (d_ratio, Event, Metric, MetricGroup) + +def Cycles() -> MetricGroup: + cyc_k =3D Event("cpu\-cycles:kHh") # exclude user and guest + cyc_g =3D Event("cpu\-cycles:G") # exclude host + cyc_u =3D Event("cpu\-cycles:uH") # exclude kernel, hypervisor and guest + cyc =3D cyc_k + cyc_g + cyc_u + + return MetricGroup("lpm_cycles", [ + Metric("lpm_cycles_total", "Total number of cycles", cyc, "cycles"), + Metric("lpm_cycles_user", "User cycles as a percentage of all cycles= ", + d_ratio(cyc_u, cyc), "100%"), + Metric("lpm_cycles_kernel", "Kernel cycles as a percentage of all cy= cles", + d_ratio(cyc_k, cyc), "100%"), + Metric("lpm_cycles_guest", "Hypervisor guest cycles as a percentage = of all cycles", + d_ratio(cyc_g, cyc), "100%"), + ], description =3D "cycles breakdown per privilege level (users, kernel,= guest)") diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 7250e8c8eeba..eab69474e141 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -5,6 +5,7 @@ from metric import (d_ratio, has_event, max, source_count, = CheckPmu, Event, Literal, LoadEvents, Metric, MetricConstraint, MetricG= roup, MetricRef, Select) import argparse +from common_metrics import Cycles import json import math import os @@ -1069,6 +1070,7 @@ def main() -> None: LoadEvents(directory) =20 all_metrics =3D MetricGroup("", [ + Cycles(), Idle(), Rapl(), Smi(), diff --git a/tools/perf/pmu-events/metric.py b/tools/perf/pmu-events/metric= .py index b77485b47666..315350f3b6ed 100644 --- a/tools/perf/pmu-events/metric.py +++ b/tools/perf/pmu-events/metric.py @@ -23,6 +23,7 @@ def LoadEvents(directory: str) -> None: "duration_time", "instructions", "l2_itlb_misses", + "cpu\-cycles", } for file in os.listdir(os.fsencode(directory)): filename =3D os.fsdecode(file) --=20 2.51.0.318.gd7df087d1a-goog From nobody Fri Oct 3 14:29:34 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8024F2253A0 for ; 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Thu, 28 Aug 2025 22:32:51 -0700 (PDT) Date: Thu, 28 Aug 2025 22:32:35 -0700 In-Reply-To: <20250829053235.21994-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250829053235.21994-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.318.gd7df087d1a-goog Message-ID: <20250829053235.21994-4-irogers@google.com> Subject: [PATCH v5 3/3] perf jevents: Validate that all names given an Event From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Jing Zhang , Sandipan Das , Benjamin Gray , Leo Yan Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Validate they exist in a json file from one directory found from one directory above the model's json directory. This avoids broken fallback encodings being created. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/metric.py | 36 +++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/tools/perf/pmu-events/metric.py b/tools/perf/pmu-events/metric= .py index 315350f3b6ed..92dcd4cd9d54 100644 --- a/tools/perf/pmu-events/metric.py +++ b/tools/perf/pmu-events/metric.py @@ -11,12 +11,14 @@ from typing import Dict, List, Optional, Set, Tuple, Un= ion all_pmus =3D set() all_events =3D set() experimental_events =3D set() +all_events_all_models =3D set() =20 def LoadEvents(directory: str) -> None: """Populate a global set of all known events for the purpose of validati= ng Event names""" global all_pmus global all_events global experimental_events + global all_events_all_models all_events =3D { "context\-switches", "cycles", @@ -42,6 +44,20 @@ def LoadEvents(directory: str) -> None: # The generated directory may be the same as the input, which # causes partial json files. Ignore errors. pass + all_events_all_models =3D all_events.copy() + for root, dirs, files in os.walk(directory + ".."): + for filename in files: + if filename.endswith(".json"): + try: + for x in json.load(open(f"{root}/{filename}")): + if "EventName" in x: + all_events_all_models.add(x["EventName"]) + elif "ArchStdEvent" in x: + all_events_all_models.add(x["ArchStdEvent"]) + except json.decoder.JSONDecodeError: + # The generated directory may be the same as the input, which + # causes partial json files. Ignore errors. + pass =20 =20 def CheckPmu(name: str) -> bool: @@ -64,6 +80,25 @@ def CheckEvent(name: str) -> bool: =20 return name in all_events =20 +def CheckEveryEvent(*names: str) -> None: + """Check all the events exist in at least one json file""" + global all_events_all_models + if len(all_events_all_models) =3D=3D 0: + assert len(names) =3D=3D 1, f"Cannot determine valid events in {names}" + # No events loaded so assume any event is good. + return + + for name in names: + # Remove trailing modifier. + if ':' in name: + name =3D name[:name.find(':')] + elif '/' in name: + name =3D name[:name.find('/')] + if any([name.startswith(x) for x in ['amd', 'arm', 'cpu', 'msr', 'po= wer']]): + continue + if name not in all_events_all_models: + raise Exception(f"Is {name} a named json event?") + =20 def IsExperimentalEvent(name: str) -> bool: global experimental_events @@ -403,6 +438,7 @@ class Event(Expression): =20 def __init__(self, *args: str): error =3D "" + CheckEveryEvent(*args) for name in args: if CheckEvent(name): self.name =3D _FixEscapes(name) --=20 2.51.0.318.gd7df087d1a-goog