From nobody Fri Oct 3 14:29:31 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3167C322C9B; Fri, 29 Aug 2025 16:21:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.205.8.231 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756484555; cv=none; b=dKEAPz7bPCL/C27sOXuZ+UgyLSYhtOPIvq1RMB6n6wwsahvPxARrUeM/0HlxAxfpTWjMXz+enLClPl6aI5yD2gG+G1DbKW8cC+o8hBzSTbhgjroQS8Te4q0dbT6pqPkgMZsqNx69IKxlC1gotqnx5+XKH6dQMlSFHWiPDGgQvZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756484555; c=relaxed/simple; bh=Jv5PaARGZu6okRJJgZpKnXYroqtQSHqcc4g3VsEQcj4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RbcLDpZoY7nHJbNxU3Nll7uD67YnlEFaanOHYzJZsaplbFl1hka4GdXrRZMma+d3lTOxtz1RjtGcmiwP1u0HGuvuIWJgXoPtXAMEAVQQVigBBRoc9qv32funxt025uomGmUrUozg0WbWJ7PM4CskUq1yw2hrZ5+gCEAXcGmfh1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=dujemihanovic.xyz; spf=pass smtp.mailfrom=dujemihanovic.xyz; dkim=pass (2048-bit key) header.d=dujemihanovic.xyz header.i=@dujemihanovic.xyz header.b=i8P9jvJC; arc=none smtp.client-ip=37.205.8.231 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=dujemihanovic.xyz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dujemihanovic.xyz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dujemihanovic.xyz header.i=@dujemihanovic.xyz header.b="i8P9jvJC" DKIM-Signature: a=rsa-sha256; bh=gu0enXB+ArZGeFWjrEyem2PEeeOOWIQywdI0rseHg5M=; c=relaxed/relaxed; d=dujemihanovic.xyz; h=Subject:Subject:Sender:To:To:Cc:Cc:From:From:Date:Date:MIME-Version:MIME-Version:Content-Type:Content-Type:Content-Transfer-Encoding:Content-Transfer-Encoding:Reply-To:In-Reply-To:In-Reply-To:Message-Id:Message-Id:References:References:Autocrypt:Openpgp; i=@dujemihanovic.xyz; s=default; t=1756484469; v=1; x=1756916469; b=i8P9jvJCdKmX9Nq/+UtnHYj65FaoK9Tie2CdS1FehfS5l+OEIBU2t0+5OwKMGmGn4OFrAtzy nrS0jB70jyHVtTaZLT9I5INKreih9VIw3n/3T3SHG7JRK+n0JbGiepO+v57HJpTDVLoUz1awgRJ tJOzpmvc95O0VQsYgrXrL3KFBfaYPij7CMssRrx58sj2I5b/mkhl3G7iwmVXeUFv3oIZp3P0H1m V8KEm8JS1GW8Iarea7rtUHeOqmtzT0cp9DZWyLhxDRqTJEyJKc81xEERhwAKPiiTNKt3T8nAzvl 9Ju2jiYQ+H/WzcqrNLGv9Zx9kaqEfQCOMlDXtuNCoUIwQ== Received: by mx.olsak.net (envelope-sender ) with ESMTPS id c64a8848; Fri, 29 Aug 2025 18:21:09 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Fri, 29 Aug 2025 18:21:04 +0200 Subject: [PATCH v3 1/4] dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250829-pxa1908-genpd-v3-1-2aacaaaca271@dujemihanovic.xyz> References: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> In-Reply-To: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3482; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=Jv5PaARGZu6okRJJgZpKnXYroqtQSHqcc4g3VsEQcj4=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBkbLxdzN+zaoxTS/MN++YQZpnX6x25fD5KY3SORvVZou cXWRqW2jlIWBjEuBlkxRZbc/47XeD+LbN2evcwAZg4rE8gQBi5OAZhIkTDDP7t8g6jsvKbVrX71 e/cwffj59av6Wj5jK93WE0GKG210mBkZPi6c8f3pu63qUUHnq94ua7GfUK9qZWJXclB+y72NzNG LmQA= X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Add required syscon compatible and #power-domain-cells to the APMU controller. This is required for the SoC's power domain controller as the registers are shared. Device tree bindings for said power domains are also added. Reviewed-by: Rob Herring (Arm) Signed-off-by: Duje Mihanovi=C4=87 --- v3: - Squash power binding patch - Update trailers v2: - Drop simple-mfd - Add #power-domain-cells --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 30 +++++++++++++++++-= ---- MAINTAINERS | 1 + include/dt-bindings/power/marvell,pxa1908-power.h | 17 ++++++++++++ 3 files changed, 42 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b= /Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml index 4e78933232b6b925811425f853bedf6e9f01a27d..6f3a8578fe2a6810911fec5879c= 07c9ddb34565a 100644 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -19,11 +19,14 @@ description: | =20 properties: compatible: - enum: - - marvell,pxa1908-apbc - - marvell,pxa1908-apbcp - - marvell,pxa1908-mpmu - - marvell,pxa1908-apmu + oneOf: + - enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - items: + - const: marvell,pxa1908-apmu + - const: syscon =20 reg: maxItems: 1 @@ -31,6 +34,9 @@ properties: '#clock-cells': const: 1 =20 + '#power-domain-cells': + const: 1 + required: - compatible - reg @@ -38,11 +44,23 @@ required: =20 additionalProperties: false =20 +if: + not: + properties: + compatible: + contains: + const: marvell,pxa1908-apmu + +then: + properties: + '#power-domain-cells': false + examples: # APMU block: - | clock-controller@d4282800 { - compatible =3D "marvell,pxa1908-apmu"; + compatible =3D "marvell,pxa1908-apmu", "syscon"; reg =3D <0xd4282800 0x400>; #clock-cells =3D <1>; + #power-domain-cells =3D <1>; }; diff --git a/MAINTAINERS b/MAINTAINERS index fed6cd812d796a08cebc0c1fd540c8901d1bf448..88f7bd50686eb1f6bcd4f34c682= 7f27ad44ea4e8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2872,6 +2872,7 @@ S: Maintained F: arch/arm64/boot/dts/marvell/mmp/ F: drivers/clk/mmp/clk-pxa1908*.c F: include/dt-bindings/clock/marvell,pxa1908.h +F: include/dt-bindings/power/marvell,pxa1908-power.h =20 ARM/Mediatek RTC DRIVER M: Eddie Huang diff --git a/include/dt-bindings/power/marvell,pxa1908-power.h b/include/dt= -bindings/power/marvell,pxa1908-power.h new file mode 100644 index 0000000000000000000000000000000000000000..19b088351af138823505a774ff2= 7203429fe2d97 --- /dev/null +++ b/include/dt-bindings/power/marvell,pxa1908-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Marvell PXA1908 power domains + * + * Copyright 2025, Duje Mihanovi=C4=87 + */ + +#ifndef __DTS_MARVELL_PXA1908_POWER_H +#define __DTS_MARVELL_PXA1908_POWER_H + +#define PXA1908_POWER_DOMAIN_VPU 0 +#define PXA1908_POWER_DOMAIN_GPU 1 +#define PXA1908_POWER_DOMAIN_GPU2D 2 +#define PXA1908_POWER_DOMAIN_DSI 3 +#define PXA1908_POWER_DOMAIN_ISP 4 + +#endif --=20 2.51.0 From nobody Fri Oct 3 14:29:31 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31600322C9A; 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Fri, 29 Aug 2025 18:21:10 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Fri, 29 Aug 2025 18:21:05 +0200 Subject: [PATCH v3 2/4] pmdomain: marvell: Add PXA1908 power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250829-pxa1908-genpd-v3-2-2aacaaaca271@dujemihanovic.xyz> References: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> In-Reply-To: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11546; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=gaKwnEjy3q2LAzP0hxaYPN5rEw13O1EeGkCpOyoJKis=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBkbLxc7Jx00nSbQXxEjk3F9ueDPvbdCTt646zarWkIv7 eye95wWHaUsDGJcDLJiiiy5/x2v8X4W2bo9e5kBzBxWJpAhDFycAjCRY28Z/jtfdZ3xXjz+oPqh vh+zjS/zPptxwOPGjLOLn6ur/LGyXq/O8JOROeHE2ozzl76FvmfzmRixwHcdh6xDdSyvxwFOX/m jykwA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Marvell's PXA1908 SoC has a few power domains for its VPU, GPU, image processor and DSI PHY. Add a driver to control these. Signed-off-by: Duje Mihanovi=C4=87 --- v3: - Move driver back to pmdomain subsystem, use auxiliary bus to instantiate the driver - Drop redundant 'struct device' pointer in 'struct pxa1908_pd' - Fix pxa1908_pd_is_on() for DSI domain - Replace usleep_range() with fsleep() - Use dev_err_probe() where sensible v2: - Move to clk subsystem, instantiate the driver from the APMU clock driver - Drop clock handling - Squash MAINTAINERS patch --- MAINTAINERS | 1 + drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/Makefile | 1 + drivers/pmdomain/marvell/Kconfig | 18 ++ drivers/pmdomain/marvell/Makefile | 3 + .../pmdomain/marvell/pxa1908-power-controller.c | 268 +++++++++++++++++= ++++ 6 files changed, 292 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 88f7bd50686eb1f6bcd4f34c6827f27ad44ea4e8..34e5e218e83e0ed9882b111f525= 1601dd6549d4e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2871,6 +2871,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated fo= r non-subscribers) S: Maintained F: arch/arm64/boot/dts/marvell/mmp/ F: drivers/clk/mmp/clk-pxa1908*.c +F: drivers/pmdomain/marvell/ F: include/dt-bindings/clock/marvell,pxa1908.h F: include/dt-bindings/power/marvell,pxa1908-power.h =20 diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 91f04ace35d4b024fafdf6af4e26a179640eb82f..23076ae90e6641dea8e5dbc851d= 041cd7929cee6 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -7,6 +7,7 @@ source "drivers/pmdomain/apple/Kconfig" source "drivers/pmdomain/arm/Kconfig" source "drivers/pmdomain/bcm/Kconfig" source "drivers/pmdomain/imx/Kconfig" +source "drivers/pmdomain/marvell/Kconfig" source "drivers/pmdomain/mediatek/Kconfig" source "drivers/pmdomain/qcom/Kconfig" source "drivers/pmdomain/renesas/Kconfig" diff --git a/drivers/pmdomain/Makefile b/drivers/pmdomain/Makefile index 7030f44a49df9e91b1c9d1b6d12690a6248671fb..ebc802f13eb953db750f5a9507c= aa64c637a957a 100644 --- a/drivers/pmdomain/Makefile +++ b/drivers/pmdomain/Makefile @@ -5,6 +5,7 @@ obj-y +=3D apple/ obj-y +=3D arm/ obj-y +=3D bcm/ obj-y +=3D imx/ +obj-y +=3D marvell/ obj-y +=3D mediatek/ obj-y +=3D qcom/ obj-y +=3D renesas/ diff --git a/drivers/pmdomain/marvell/Kconfig b/drivers/pmdomain/marvell/Kc= onfig new file mode 100644 index 0000000000000000000000000000000000000000..6c4084c826670266b7d948438f6= e6d76acb416e2 --- /dev/null +++ b/drivers/pmdomain/marvell/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menu "Marvell PM Domains" + depends on ARCH_MMP || COMPILE_TEST + +config PXA1908_PM_DOMAINS + tristate "Marvell PXA1908 power domains" + depends on OF + depends on PM + default y if ARCH_MMP && ARM64 + select AUXILIARY_BUS + select MFD_SYSCON + select PM_GENERIC_DOMAINS + select PM_GENERIC_DOMAINS_OF + help + Say Y here to enable support for Marvell PXA1908's power domanis. + +endmenu diff --git a/drivers/pmdomain/marvell/Makefile b/drivers/pmdomain/marvell/M= akefile new file mode 100644 index 0000000000000000000000000000000000000000..22c25013f6c856a2ca01a121e83= 0279ee88eb0ed --- /dev/null +++ b/drivers/pmdomain/marvell/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_PXA1908_PM_DOMAINS) +=3D pxa1908-power-controller.o diff --git a/drivers/pmdomain/marvell/pxa1908-power-controller.c b/drivers/= pmdomain/marvell/pxa1908-power-controller.c new file mode 100644 index 0000000000000000000000000000000000000000..29134629861abcf46959f9dcc98= d3f05a4cc5b72 --- /dev/null +++ b/drivers/pmdomain/marvell/pxa1908-power-controller.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2025 Duje Mihanovi=C4=87 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* VPU, GPU, ISP */ +#define APMU_PWR_CTRL_REG 0xd8 +#define APMU_PWR_BLK_TMR_REG 0xdc +#define APMU_PWR_STATUS_REG 0xf0 + +/* DSI */ +#define APMU_DEBUG 0x88 +#define DSI_PHY_DVM_MASK BIT(31) + +#define POWER_ON_LATENCY_US 300 +#define POWER_OFF_LATENCY_US 20 + +#define NR_DOMAINS 5 + +struct pxa1908_pd_ctrl { + struct generic_pm_domain *domains[NR_DOMAINS]; + struct genpd_onecell_data onecell_data; + struct regmap *base; +}; + +struct pxa1908_pd_data { + u32 reg_clk_res_ctrl; + u32 pwr_state; + u32 hw_mode; + bool keep_on; + int id; +}; + +struct pxa1908_pd { + const struct pxa1908_pd_data data; + struct generic_pm_domain genpd; + bool initialized; +}; + +static inline bool pxa1908_pd_is_on(struct pxa1908_pd *pd) +{ + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(&pd->genpd.dev); + + return pd->data.id !=3D PXA1908_POWER_DOMAIN_DSI + ? regmap_test_bits(ctrl->base, APMU_PWR_STATUS_REG, pd->data.pwr_state) + : regmap_test_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK); +} + +static int pxa1908_pd_power_on(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd *pd =3D container_of(genpd, struct pxa1908_pd, genpd); + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(&genpd->dev); + const struct pxa1908_pd_data *data =3D &pd->data; + unsigned int status; + int ret =3D 0; + + regmap_set_bits(ctrl->base, data->reg_clk_res_ctrl, data->hw_mode); + if (data->id !=3D PXA1908_POWER_DOMAIN_ISP) + regmap_write(ctrl->base, APMU_PWR_BLK_TMR_REG, 0x20001fff); + regmap_set_bits(ctrl->base, APMU_PWR_CTRL_REG, data->pwr_state); + + fsleep(POWER_ON_LATENCY_US); + + ret =3D regmap_read_poll_timeout(ctrl->base, APMU_PWR_STATUS_REG, status, + status & data->pwr_state, 6, 25 * USEC_PER_MSEC); + if (ret =3D=3D -ETIMEDOUT) + dev_err(&genpd->dev, "timed out powering on domain '%s'\n", pd->genpd.na= me); + + return ret; +} + +static int pxa1908_pd_power_off(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd *pd =3D container_of(genpd, struct pxa1908_pd, genpd); + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(&genpd->dev); + const struct pxa1908_pd_data *data =3D &pd->data; + unsigned int status; + int ret; + + regmap_clear_bits(ctrl->base, APMU_PWR_CTRL_REG, data->pwr_state); + + fsleep(POWER_OFF_LATENCY_US); + + ret =3D regmap_read_poll_timeout(ctrl->base, APMU_PWR_STATUS_REG, status, + !(status & data->pwr_state), 6, 25 * USEC_PER_MSEC); + if (ret =3D=3D -ETIMEDOUT) { + dev_err(&genpd->dev, "timed out powering off domain '%s'\n", pd->genpd.n= ame); + return ret; + } + + return regmap_clear_bits(ctrl->base, data->reg_clk_res_ctrl, data->hw_mod= e); +} + +static inline int pxa1908_dsi_power_on(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(&genpd->dev); + + return regmap_set_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK); +} + +static inline int pxa1908_dsi_power_off(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(&genpd->dev); + + return regmap_clear_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK); +} + +#define DOMAIN(_id, _name, ctrl, mode, state) \ + [_id] =3D { \ + .data =3D { \ + .reg_clk_res_ctrl =3D ctrl, \ + .hw_mode =3D BIT(mode), \ + .pwr_state =3D BIT(state), \ + .id =3D _id, \ + }, \ + .genpd =3D { \ + .name =3D _name, \ + .power_on =3D pxa1908_pd_power_on, \ + .power_off =3D pxa1908_pd_power_off, \ + }, \ + } + +static struct pxa1908_pd domains[NR_DOMAINS] =3D { + DOMAIN(PXA1908_POWER_DOMAIN_VPU, "vpu", 0xa4, 19, 2), + DOMAIN(PXA1908_POWER_DOMAIN_GPU, "gpu", 0xcc, 11, 0), + DOMAIN(PXA1908_POWER_DOMAIN_GPU2D, "gpu2d", 0xf4, 11, 6), + DOMAIN(PXA1908_POWER_DOMAIN_ISP, "isp", 0x38, 15, 4), + [PXA1908_POWER_DOMAIN_DSI] =3D { + .genpd =3D { + .name =3D "dsi", + .power_on =3D pxa1908_dsi_power_on, + .power_off =3D pxa1908_dsi_power_off, + /* + * TODO: There is no DSI driver written yet and until then we probably + * don't want to power off the DSI PHY ever. + */ + .flags =3D GENPD_FLAG_ALWAYS_ON, + }, + .data =3D { + /* See above. */ + .keep_on =3D true, + }, + }, +}; + +static void pxa1908_pd_remove(struct auxiliary_device *auxdev) +{ + struct pxa1908_pd *pd; + int ret; + + for (int i =3D NR_DOMAINS - 1; i >=3D 0; i--) { + pd =3D &domains[i]; + + if (!pd->initialized) + continue; + + if (pxa1908_pd_is_on(pd) && !pd->data.keep_on) + pxa1908_pd_power_off(&pd->genpd); + + ret =3D pm_genpd_remove(&pd->genpd); + if (ret) + dev_err(&pd->genpd.dev, "failed to remove domain '%s': %d\n", + pd->genpd.name, ret); + } +} + +static int +pxa1908_pd_init(struct pxa1908_pd_ctrl *ctrl, int id, struct device *dev) +{ + struct pxa1908_pd *pd =3D &domains[id]; + int ret; + + ctrl->domains[id] =3D &pd->genpd; + + ret =3D pm_genpd_init(&pd->genpd, NULL, !pd->data.keep_on); + if (ret) + return dev_err_probe(dev, ret, "domain '%s' failed to initialize\n", + pd->genpd.name); + + dev_set_drvdata(&pd->genpd.dev, ctrl); + + /* Make sure the state of the hardware is synced with the domain table ab= ove. */ + if (pd->data.keep_on) { + ret =3D pd->genpd.power_on(&pd->genpd); + if (ret) + return dev_err_probe(dev, ret, "failed to power on domain '%s'\n", + pd->genpd.name); + } else { + if (pxa1908_pd_is_on(pd)) { + dev_warn(dev, + "domain '%s' is on despite being default off; powering off\n", + pd->genpd.name); + + ret =3D pd->genpd.power_off(&pd->genpd); + if (ret) + return dev_err_probe(dev, ret, + "failed to power off domain '%s'\n", + pd->genpd.name); + } + } + + pd->initialized =3D true; + + return 0; +} + +static int +pxa1908_pd_probe(struct auxiliary_device *auxdev, const struct auxiliary_d= evice_id *aux_id) +{ + struct pxa1908_pd_ctrl *ctrl; + struct device *dev =3D &auxdev->dev; + int ret; + + ctrl =3D devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + auxiliary_set_drvdata(auxdev, ctrl); + + ctrl->base =3D syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(ctrl->base)) + return dev_err_probe(dev, PTR_ERR(ctrl->base), "no regmap available\n"); + + ctrl->onecell_data.domains =3D ctrl->domains; + ctrl->onecell_data.num_domains =3D NR_DOMAINS; + + for (int i =3D 0; i < NR_DOMAINS; i++) { + ret =3D pxa1908_pd_init(ctrl, i, dev); + if (ret) + goto err; + } + + return of_genpd_add_provider_onecell(dev->parent->of_node, &ctrl->onecell= _data); + +err: + pxa1908_pd_remove(auxdev); + return ret; +} + +static const struct auxiliary_device_id pxa1908_pd_id[] =3D { + { .name =3D "clk_pxa1908_apmu.power" }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, pxa1908_pd_id); + +static struct auxiliary_driver pxa1908_pd_driver =3D { + .probe =3D pxa1908_pd_probe, + .remove =3D pxa1908_pd_remove, + .id_table =3D pxa1908_pd_id, +}; +module_auxiliary_driver(pxa1908_pd_driver); + +MODULE_AUTHOR("Duje Mihanovi=C4=87 "); +MODULE_DESCRIPTION("Marvell PXA1908 power domain driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Fri Oct 3 14:29:31 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44D41322DAA; Fri, 29 Aug 2025 16:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 29 Aug 2025 18:21:11 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Fri, 29 Aug 2025 18:21:06 +0200 Subject: [PATCH v3 3/4] clk: mmp: pxa1908: Instantiate power driver through auxiliary bus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250829-pxa1908-genpd-v3-3-2aacaaaca271@dujemihanovic.xyz> References: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> In-Reply-To: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4741; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=fPWhnGfubtatcWiWaKaUiAvygdrfiV2pPKAKsw2j7KQ=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBkbLxdvXb7nS5z1mZKHJ1aditrhwrsyem+jm9rzC6bf2 I+sKlh7sKOUhUGMi0FWTJEl97/jNd7PIlu3Zy8zgJnDygQyhIGLUwAmUj2L4X+F6hMd9trLAfNr p1w4umFW1YtdqwqOfvoRay2koVHjmfqO4X9K9YwKv4c3Fs6e3ZdYfkPtebZGK//+gn89V39xvpt 1cDEHAA== X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 The power domain driver shares the APMU clock controller's registers. Instantiate the power domain driver through the APMU clock driver using the auxiliary bus. Also create a separate Kconfig entry for the PXA1908 clock driver to allow (de)selecting the driver at will and selecting CONFIG_AUXILIARY_BUS. Signed-off-by: Duje Mihanovi=C4=87 --- v3: - Move driver back to pmdomain subsystem, use auxiliary bus to instantiate the driver v2: - Move to clk subsystem, instantiate the driver from the APMU clock driver - Drop clock handling - Squash MAINTAINERS patch --- MAINTAINERS | 2 ++ drivers/clk/Kconfig | 1 + drivers/clk/mmp/Kconfig | 10 ++++++++++ drivers/clk/mmp/Makefile | 5 ++++- drivers/clk/mmp/clk-pxa1908-apmu.c | 20 ++++++++++++++++++++ 5 files changed, 37 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 34e5e218e83e0ed9882b111f5251601dd6549d4e..88c0df09d7b354f95864f5a48da= ea3be14a90dc4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2869,7 +2869,9 @@ ARM/Marvell PXA1908 SOC support M: Duje Mihanovi=C4=87 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml F: arch/arm64/boot/dts/marvell/mmp/ +F: drivers/clk/mmp/Kconfig F: drivers/clk/mmp/clk-pxa1908*.c F: drivers/pmdomain/marvell/ F: include/dt-bindings/clock/marvell,pxa1908.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4d56475f94fc1e28823fe6aee626a96847d4e6d5..68a9641fc649a23013b2d8a9e9f= 5ecb31d623abb 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -511,6 +511,7 @@ source "drivers/clk/imx/Kconfig" source "drivers/clk/ingenic/Kconfig" source "drivers/clk/keystone/Kconfig" source "drivers/clk/mediatek/Kconfig" +source "drivers/clk/mmp/Kconfig" source "drivers/clk/meson/Kconfig" source "drivers/clk/mstar/Kconfig" source "drivers/clk/microchip/Kconfig" diff --git a/drivers/clk/mmp/Kconfig b/drivers/clk/mmp/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..b0d2fea3cda5de1284916ab75d3= af0412edcf57f --- /dev/null +++ b/drivers/clk/mmp/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config COMMON_CLK_PXA1908 + bool "Clock driver for Marvell PXA1908" + depends on ARCH_MMP || COMPILE_TEST + depends on OF + default y if ARCH_MMP && ARM64 + select AUXILIARY_BUS + help + This driver supports the Marvell PXA1908 SoC clocks. diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 062cd87fa8ddcc6808b6236f8c4dd524aaf02030..0a94f2f0856389c8e959981ccaf= bb02140a7733d 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,7 @@ obj-$(CONFIG_MACH_MMP_DT) +=3D clk-of-pxa168.o clk-of-pxa= 910.o obj-$(CONFIG_COMMON_CLK_MMP2) +=3D clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) +=3D clk-audio.o =20 -obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa190= 8-apbcp.o clk-pxa1908-apmu.o clk-pxa1908-mpmu.o +obj-$(CONFIG_COMMON_CLK_PXA1908) +=3D clk-pxa1908-apbc.o clk-pxa1908-apbcp= .o \ + clk-pxa1908-mpmu.o clk-pxa1908-apmu.o + +obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o diff --git a/drivers/clk/mmp/clk-pxa1908-apmu.c b/drivers/clk/mmp/clk-pxa19= 08-apmu.c index d3a070687fc5b9fb5338f377f82e7664ca0aac29..eab02c89c9153619ac53f7486ed= 811f2cae12a43 100644 --- a/drivers/clk/mmp/clk-pxa1908-apmu.c +++ b/drivers/clk/mmp/clk-pxa1908-apmu.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only +#include #include #include #include @@ -85,6 +86,8 @@ static void pxa1908_axi_periph_clk_init(struct pxa1908_cl= k_unit *pxa_unit) static int pxa1908_apmu_probe(struct platform_device *pdev) { struct pxa1908_clk_unit *pxa_unit; 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Fri, 29 Aug 2025 18:21:12 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Fri, 29 Aug 2025 18:21:07 +0200 Subject: [PATCH v3 4/4] arm64: dts: marvell: pxa1908: Add power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250829-pxa1908-genpd-v3-4-2aacaaaca271@dujemihanovic.xyz> References: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> In-Reply-To: <20250829-pxa1908-genpd-v3-0-2aacaaaca271@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2261; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=+LiKf5xAdZ3VQjErBPnxDlU3GQ3YyQ0Gx7TmBGM/obc=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBkbLxd7zLsy47VSwKc/9pcnyMjnK9vNVg7pFliw+P7z/ JkRngf3d5SyMIhxMciKKbLk/ne8xvtZZOv27GUGMHNYmUCGMHBxCsBEopoY/unWCxhsWfs6mzGo K/fx45e868okuZm45vpsFxP8/ll5kxXDX5makoAdSZrKUl4Ct4s+9BnKsadOOc5f3+N50zDhSzI bCwA= X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Update the APMU clock controller's compatible to allow the new power domain driver to probe. Also add the first two power domain consumers: IOMMU (fixes probing) and framebuffer. Signed-off-by: Duje Mihanovi=C4=87 --- v2: - Drop power controller node - &pd -> &apmu --- arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts | 1 + arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi | 5 +++= +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte= .dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts index 47a4f01a7077bfafe2cc50d0e59c37685ec9c2e9..d61922f326a4654a45ab4312ea5= 12ac1b8b01c50 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts @@ -23,6 +23,7 @@ chosen { fb0: framebuffer@17177000 { compatible =3D "simple-framebuffer"; reg =3D <0 0x17177000 0 (480 * 800 * 4)>; + power-domains =3D <&apmu PXA1908_POWER_DOMAIN_DSI>; width =3D <480>; height =3D <800>; stride =3D <(480 * 4)>; diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi b/arch/arm64/boot= /dts/marvell/mmp/pxa1908.dtsi index cf2b9109688ce560eec8a1397251ead68d78a239..ae85b90eeb408a8f4014ec7b600= 48ae1fd3d4044 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi @@ -3,6 +3,7 @@ =20 #include #include +#include =20 / { model =3D "Marvell Armada PXA1908"; @@ -79,6 +80,7 @@ smmu: iommu@c0010000 { #iommu-cells =3D <1>; interrupts =3D , ; + power-domains =3D <&apmu PXA1908_POWER_DOMAIN_VPU>; status =3D "disabled"; }; =20 @@ -291,9 +293,10 @@ sdh2: mmc@81000 { }; =20 apmu: clock-controller@82800 { - compatible =3D "marvell,pxa1908-apmu"; + compatible =3D "marvell,pxa1908-apmu", "syscon"; reg =3D <0x82800 0x400>; #clock-cells =3D <1>; + #power-domain-cells =3D <1>; }; }; }; --=20 2.51.0