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[34.125.3.185]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-32741503367sm4540727a91.0.2025.08.28.13.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 13:18:15 -0700 (PDT) From: Chia-I Wu To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: gpu: mali-valhall-csf: add asn-hash Date: Thu, 28 Aug 2025 13:18:05 -0700 Message-ID: <20250828201806.3541261-2-olvaffe@gmail.com> X-Mailer: git-send-email 2.51.0.318.gd7df087d1a-goog In-Reply-To: <20250828201806.3541261-1-olvaffe@gmail.com> References: <20250828201806.3541261-1-olvaffe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The values are written to ASN_HASH[0..2] registers. The property is called "l2-hash-values" in the downstream driver. Signed-off-by: Chia-I Wu --- .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yam= l b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index a5b4e00217587..258bcba66d1d1 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -85,6 +85,14 @@ properties: =20 dma-coherent: true =20 + asn-hash: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + The values are written to ASN_HASH[0..2] registers. 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[34.125.3.185]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-24905da478fsm3754525ad.65.2025.08.28.13.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 13:18:16 -0700 (PDT) From: Chia-I Wu To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] drm/panthor: add asn-hash support Date: Thu, 28 Aug 2025 13:18:06 -0700 Message-ID: <20250828201806.3541261-3-olvaffe@gmail.com> X-Mailer: git-send-email 2.51.0.318.gd7df087d1a-goog In-Reply-To: <20250828201806.3541261-1-olvaffe@gmail.com> References: <20250828201806.3541261-1-olvaffe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse asn-hash and enable custom ASN hash when the property exists. This is required on some socs such as mt8196. Signed-off-by: Chia-I Wu --- drivers/gpu/drm/panthor/panthor_device.c | 28 ++++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_device.h | 6 +++++ drivers/gpu/drm/panthor/panthor_gpu.c | 17 ++++++++++++++ drivers/gpu/drm/panthor/panthor_regs.h | 4 ++++ 4 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/pan= thor/panthor_device.c index 81df49880bd87..19423c495d8d7 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -41,6 +41,30 @@ static int panthor_gpu_coherency_init(struct panthor_dev= ice *ptdev) return -ENOTSUPP; } =20 +static int panthor_gpu_asn_hash_init(struct panthor_device *ptdev) +{ + int ret; + + ret =3D of_property_read_u32_array(ptdev->base.dev->of_node, "asn-hash", + ptdev->asn_hash, + ARRAY_SIZE(ptdev->asn_hash)); + if (ret) { + if (ret =3D=3D -EINVAL) + ret =3D 0; + return ret; + } + + if (GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) < 11) { + drm_err(&ptdev->base, + "Custom ASN hash not supported by the device"); + return -EOPNOTSUPP; + } + + ptdev->has_asn_hash =3D true; + + return 0; +} + static int panthor_clk_init(struct panthor_device *ptdev) { ptdev->clks.core =3D devm_clk_get(ptdev->base.dev, NULL); @@ -257,6 +281,10 @@ int panthor_device_init(struct panthor_device *ptdev) if (ret) goto err_unplug_gpu; =20 + ret =3D panthor_gpu_asn_hash_init(ptdev); + if (ret) + goto err_unplug_gpu; + ret =3D panthor_mmu_init(ptdev); if (ret) goto err_unplug_gpu; diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index 4fc7cf2aeed57..6f8e2b3b037e5 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -114,6 +114,12 @@ struct panthor_device { /** @coherent: True if the CPU/GPU are memory coherent. */ bool coherent; =20 + /** @has_asn_hash: True if custom ASN hash is enabled. */ + bool has_asn_hash; + + /** @asn_hash: ASN_HASH values for custom ASN hash */ + u32 asn_hash[3]; + /** @gpu_info: GPU information. */ struct drm_panthor_gpu_info gpu_info; =20 diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index db69449a5be09..f9222b67f314d 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -52,6 +52,22 @@ static void panthor_gpu_coherency_set(struct panthor_dev= ice *ptdev) ptdev->coherent ? GPU_COHERENCY_PROT_BIT(ACE_LITE) : GPU_COHERENCY_NONE); } =20 +static void panthor_gpu_asn_hash_set(struct panthor_device *ptdev) +{ + u32 l2_config; + u32 i; + + if (!ptdev->has_asn_hash) + return; + + for (i =3D 0; i < ARRAY_SIZE(ptdev->asn_hash); i++) + gpu_write(ptdev, ASN_HASH(i), ptdev->asn_hash[i]); + + l2_config =3D gpu_read(ptdev, L2_CONFIG); + l2_config |=3D L2_CONFIG_ASN_HASH_ENABLE; + gpu_write(ptdev, L2_CONFIG, l2_config); +} + static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 stat= us) { gpu_write(ptdev, GPU_INT_CLEAR, status); @@ -243,6 +259,7 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptde= v) =20 /* Set the desired coherency mode before the power up of L2 */ panthor_gpu_coherency_set(ptdev); + panthor_gpu_asn_hash_set(ptdev); =20 return panthor_gpu_power_on(ptdev, L2, 1, 20000); } diff --git a/drivers/gpu/drm/panthor/panthor_regs.h b/drivers/gpu/drm/panth= or/panthor_regs.h index 8bee76d01bf83..c9f795624e79b 100644 --- a/drivers/gpu/drm/panthor/panthor_regs.h +++ b/drivers/gpu/drm/panthor/panthor_regs.h @@ -64,6 +64,8 @@ =20 #define GPU_FAULT_STATUS 0x3C #define GPU_FAULT_ADDR 0x40 +#define L2_CONFIG 0x48 +#define L2_CONFIG_ASN_HASH_ENABLE BIT(24) =20 #define GPU_PWR_KEY 0x50 #define GPU_PWR_KEY_UNLOCK 0x2968A819 @@ -110,6 +112,8 @@ =20 #define GPU_REVID 0x280 =20 +#define ASN_HASH(n) (0x2C0 + ((n) * 4)) + #define GPU_COHERENCY_FEATURES 0x300 #define GPU_COHERENCY_PROT_BIT(name) BIT(GPU_COHERENCY_ ## name) =20 --=20 2.51.0.318.gd7df087d1a-goog